1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation. 3 * Copyright 2013-2014 6WIND S.A. 4 */ 5 6 #ifndef _RTE_BUS_PCI_H_ 7 #define _RTE_BUS_PCI_H_ 8 9 /** 10 * @file 11 * PCI device & driver interface 12 */ 13 14 #include <stdio.h> 15 #include <stdlib.h> 16 #include <limits.h> 17 #include <errno.h> 18 #include <stdint.h> 19 #include <inttypes.h> 20 21 #include <rte_compat.h> 22 #include <rte_debug.h> 23 #include <rte_interrupts.h> 24 #include <rte_pci.h> 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Forward declarations */ 31 struct rte_pci_device; 32 struct rte_pci_driver; 33 struct rte_pci_ioport; 34 35 struct rte_devargs; 36 37 /** 38 * Map the PCI device resources in user space virtual memory address 39 * 40 * Note that driver should not call this function when flag 41 * RTE_PCI_DRV_NEED_MAPPING is set, as EAL will do that for 42 * you when it's on. 43 * 44 * @param dev 45 * A pointer to a rte_pci_device structure describing the device 46 * to use 47 * 48 * @return 49 * 0 on success, negative on error and positive if no driver 50 * is found for the device. 51 */ 52 int rte_pci_map_device(struct rte_pci_device *dev); 53 54 /** 55 * Unmap this device 56 * 57 * @param dev 58 * A pointer to a rte_pci_device structure describing the device 59 * to use 60 */ 61 void rte_pci_unmap_device(struct rte_pci_device *dev); 62 63 /** 64 * Dump the content of the PCI bus. 65 * 66 * @param f 67 * A pointer to a file for output 68 */ 69 void rte_pci_dump(FILE *f); 70 71 /** 72 * Check whether this device has a PCI capability list. 73 * 74 * @param dev 75 * A pointer to rte_pci_device structure. 76 * 77 * @return 78 * true/false 79 */ 80 __rte_experimental 81 bool rte_pci_has_capability_list(const struct rte_pci_device *dev); 82 83 /** 84 * Find device's PCI capability. 85 * 86 * @param dev 87 * A pointer to rte_pci_device structure. 88 * 89 * @param cap 90 * Capability to be found, which can be any from 91 * RTE_PCI_CAP_ID_*, defined in librte_pci. 92 * 93 * @return 94 * > 0: The offset of the next matching capability structure 95 * within the device's PCI configuration space. 96 * < 0: An error in PCI config space read. 97 * = 0: Device does not support it. 98 */ 99 __rte_experimental 100 off_t rte_pci_find_capability(const struct rte_pci_device *dev, uint8_t cap); 101 102 /** 103 * Find device's PCI capability starting from a previous offset in PCI 104 * configuration space. 105 * 106 * @param dev 107 * A pointer to rte_pci_device structure. 108 * 109 * @param cap 110 * Capability to be found, which can be any from 111 * RTE_PCI_CAP_ID_*, defined in librte_pci. 112 * @param offset 113 * An offset in the PCI configuration space from which the capability is 114 * looked for. 115 * 116 * @return 117 * > 0: The offset of the next matching capability structure 118 * within the device's PCI configuration space. 119 * < 0: An error in PCI config space read. 120 * = 0: Device does not support it. 121 */ 122 __rte_experimental 123 off_t rte_pci_find_next_capability(const struct rte_pci_device *dev, uint8_t cap, off_t offset); 124 125 /** 126 * Find device's extended PCI capability. 127 * 128 * @param dev 129 * A pointer to rte_pci_device structure. 130 * 131 * @param cap 132 * Extended capability to be found, which can be any from 133 * RTE_PCI_EXT_CAP_ID_*, defined in librte_pci. 134 * 135 * @return 136 * > 0: The offset of the next matching extended capability structure 137 * within the device's PCI configuration space. 138 * < 0: An error in PCI config space read. 139 * = 0: Device does not support it. 140 */ 141 __rte_experimental 142 off_t rte_pci_find_ext_capability(const struct rte_pci_device *dev, uint32_t cap); 143 144 /** 145 * Enables/Disables Bus Master for device's PCI command register. 146 * 147 * @param dev 148 * A pointer to rte_pci_device structure. 149 * @param enable 150 * Enable or disable Bus Master. 151 * 152 * @return 153 * 0 on success, -1 on error in PCI config space read/write. 154 */ 155 __rte_experimental 156 int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable); 157 158 /** 159 * Enable/Disable PASID (Process Address Space ID). 160 * 161 * @param dev 162 * A pointer to a rte_pci_device structure. 163 * @param offset 164 * Offset of the PASID external capability structure. 165 * @param enable 166 * Flag to enable or disable PASID. 167 * 168 * @return 169 * 0 on success, -1 on error in PCI config space read/write. 170 */ 171 __rte_internal 172 int rte_pci_pasid_set_state(const struct rte_pci_device *dev, 173 off_t offset, bool enable); 174 175 /** 176 * Read PCI config space. 177 * 178 * @param device 179 * A pointer to a rte_pci_device structure describing the device 180 * to use 181 * @param buf 182 * A data buffer where the bytes should be read into 183 * @param len 184 * The length of the data buffer. 185 * @param offset 186 * The offset into PCI config space 187 * @return 188 * Number of bytes read on success, negative on error. 189 */ 190 int rte_pci_read_config(const struct rte_pci_device *device, 191 void *buf, size_t len, off_t offset); 192 193 /** 194 * Write PCI config space. 195 * 196 * @param device 197 * A pointer to a rte_pci_device structure describing the device 198 * to use 199 * @param buf 200 * A data buffer containing the bytes should be written 201 * @param len 202 * The length of the data buffer. 203 * @param offset 204 * The offset into PCI config space 205 */ 206 int rte_pci_write_config(const struct rte_pci_device *device, 207 const void *buf, size_t len, off_t offset); 208 209 /** 210 * @warning 211 * @b EXPERIMENTAL: this API may change without prior notice. 212 * 213 * Read from a MMIO PCI resource. 214 * 215 * @param device 216 * A pointer to a rte_pci_device structure describing the device 217 * to use. 218 * @param bar 219 * Index of the IO PCI resource we want to access. 220 * @param buf 221 * A data buffer where the bytes should be read into. 222 * @param len 223 * The length of the data buffer. 224 * @param offset 225 * The offset into MMIO space described by @bar. 226 * @return 227 * Number of bytes read on success, negative on error. 228 */ 229 __rte_experimental 230 int rte_pci_mmio_read(const struct rte_pci_device *device, int bar, 231 void *buf, size_t len, off_t offset); 232 233 /** 234 * @warning 235 * @b EXPERIMENTAL: this API may change without prior notice. 236 * 237 * Write to a MMIO PCI resource. 238 * 239 * @param device 240 * A pointer to a rte_pci_device structure describing the device 241 * to use. 242 * @param bar 243 * Index of the IO PCI resource we want to access. 244 * @param buf 245 * A data buffer containing the bytes should be written. 246 * @param len 247 * The length of the data buffer. 248 * @param offset 249 * The offset into MMIO space described by @bar. 250 * @return 251 * Number of bytes written on success, negative on error. 252 */ 253 __rte_experimental 254 int rte_pci_mmio_write(const struct rte_pci_device *device, int bar, 255 const void *buf, size_t len, off_t offset); 256 257 /** 258 * Initialize a rte_pci_ioport object for a pci device io resource. 259 * 260 * This object is then used to gain access to those io resources (see below). 261 * 262 * @param dev 263 * A pointer to a rte_pci_device structure describing the device 264 * to use. 265 * @param bar 266 * Index of the io pci resource we want to access. 267 * @param p 268 * The rte_pci_ioport object to be initialized. 269 * @return 270 * 0 on success, negative on error. 271 */ 272 int rte_pci_ioport_map(struct rte_pci_device *dev, int bar, 273 struct rte_pci_ioport *p); 274 275 /** 276 * Release any resources used in a rte_pci_ioport object. 277 * 278 * @param p 279 * The rte_pci_ioport object to be uninitialized. 280 * @return 281 * 0 on success, negative on error. 282 */ 283 int rte_pci_ioport_unmap(struct rte_pci_ioport *p); 284 285 /** 286 * Read from a io pci resource. 287 * 288 * @param p 289 * The rte_pci_ioport object from which we want to read. 290 * @param data 291 * A data buffer where the bytes should be read into 292 * @param len 293 * The length of the data buffer. 294 * @param offset 295 * The offset into the pci io resource. 296 */ 297 void rte_pci_ioport_read(struct rte_pci_ioport *p, 298 void *data, size_t len, off_t offset); 299 300 /** 301 * Write to a io pci resource. 302 * 303 * @param p 304 * The rte_pci_ioport object to which we want to write. 305 * @param data 306 * A data buffer where the bytes should be read into 307 * @param len 308 * The length of the data buffer. 309 * @param offset 310 * The offset into the pci io resource. 311 */ 312 void rte_pci_ioport_write(struct rte_pci_ioport *p, 313 const void *data, size_t len, off_t offset); 314 315 #ifdef __cplusplus 316 } 317 #endif 318 319 #endif /* _RTE_BUS_PCI_H_ */ 320