1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2010-2012 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright 2019-2020 NXP 6 * 7 */ 8 9 #ifndef __FMAN_H 10 #define __FMAN_H 11 12 #include <stdbool.h> 13 #include <net/if.h> 14 15 #include <ethdev_driver.h> 16 #include <rte_ether.h> 17 18 #include <compat.h> 19 #include <dpaa_list.h> 20 21 #ifndef FMAN_DEVICE_PATH 22 #define FMAN_DEVICE_PATH "/dev/mem" 23 #endif 24 25 #define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */ 26 27 /* Control and Configuration Register (COMMAND_CONFIG) for MEMAC */ 28 #define CMD_CFG_LOOPBACK_EN 0x00000400 29 /**< 21 XGMII/GMII loopback enable */ 30 #define CMD_CFG_PROMIS_EN 0x00000010 31 /**< 27 Promiscuous operation enable */ 32 #define CMD_CFG_PAUSE_IGNORE 0x00000100 33 /**< 23 Ignore Pause frame quanta */ 34 35 /* Statistics Configuration Register (STATN_CONFIG) */ 36 #define STATS_CFG_CLR 0x00000004 37 /**< 29 Reset all counters */ 38 #define STATS_CFG_CLR_ON_RD 0x00000002 39 /**< 30 Clear on read */ 40 #define STATS_CFG_SATURATE 0x00000001 41 /**< 31 Saturate at the maximum val */ 42 43 /**< Max receive frame length mask */ 44 #define MAXFRM_SIZE_MEMAC 0x00007fe0 45 #define MAXFRM_RX_MASK 0x0000ffff 46 47 /**< Interface Mode Register Register for MEMAC */ 48 #define IF_MODE_RLP 0x00000820 49 50 /**< Pool Limits */ 51 #define FMAN_PORT_MAX_EXT_POOLS_NUM 8 52 #define FMAN_PORT_OBS_EXT_POOLS_NUM 2 53 54 #define FMAN_PORT_CG_MAP_NUM 8 55 #define FMAN_PORT_PRS_RESULT_WORDS_NUM 8 56 #define FMAN_PORT_BMI_FIFO_UNITS 0x100 57 #define FMAN_PORT_IC_OFFSET_UNITS 0x10 58 59 #define FMAN_ENABLE_BPOOL_DEPLETION 0xF00000F0 60 61 #define HASH_CTRL_MCAST_EN 0x00000100 62 #define GROUP_ADDRESS 0x0000010000000000LL 63 #define HASH_CTRL_ADDR_MASK 0x0000003F 64 65 /* Pre definitions of FMAN interface and Bpool structures */ 66 struct __fman_if; 67 struct fman_if_bpool; 68 /* Lists of fman interfaces and bpools */ 69 TAILQ_HEAD(rte_fman_if_list, __fman_if); 70 71 /* Represents the different flavour of network interface */ 72 enum fman_mac_type { 73 fman_offline = 0, 74 fman_mac_1g, 75 fman_mac_10g, 76 fman_mac_2_5g, 77 }; 78 79 struct mac_addr { 80 uint32_t mac_addr_l; /**< Lower 32 bits of 48-bit MAC address */ 81 uint32_t mac_addr_u; /**< Upper 16 bits of 48-bit MAC address */ 82 }; 83 84 struct memac_regs { 85 /* General Control and Status */ 86 uint32_t res0000[2]; 87 uint32_t command_config; /**< 0x008 Ctrl and cfg */ 88 struct mac_addr mac_addr0; /**< 0x00C-0x010 MAC_ADDR_0...1 */ 89 uint32_t maxfrm; /**< 0x014 Max frame length */ 90 uint32_t res0018[5]; 91 uint32_t hashtable_ctrl; /**< 0x02C Hash table control */ 92 uint32_t res0030[4]; 93 uint32_t ievent; /**< 0x040 Interrupt event */ 94 uint32_t tx_ipg_length; 95 /**< 0x044 Transmitter inter-packet-gap */ 96 uint32_t res0048; 97 uint32_t imask; /**< 0x04C Interrupt mask */ 98 uint32_t res0050; 99 uint32_t pause_quanta[4]; /**< 0x054 Pause quanta */ 100 uint32_t pause_thresh[4]; /**< 0x064 Pause quanta threshold */ 101 uint32_t rx_pause_status; /**< 0x074 Receive pause status */ 102 uint32_t res0078[2]; 103 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS]; 104 /**< 0x80-0x0B4 mac padr */ 105 uint32_t lpwake_timer; 106 /**< 0x0B8 Low Power Wakeup Timer */ 107 uint32_t sleep_timer; 108 /**< 0x0BC Transmit EEE Low Power Timer */ 109 uint32_t res00c0[8]; 110 uint32_t statn_config; 111 /**< 0x0E0 Statistics configuration */ 112 uint32_t res00e4[7]; 113 /* Rx Statistics Counter */ 114 uint32_t reoct_l; /**<Rx Eth Octets Counter */ 115 uint32_t reoct_u; 116 uint32_t roct_l; /**<Rx Octet Counters */ 117 uint32_t roct_u; 118 uint32_t raln_l; /**<Rx Alignment Error Counter */ 119 uint32_t raln_u; 120 uint32_t rxpf_l; /**<Rx valid Pause Frame */ 121 uint32_t rxpf_u; 122 uint32_t rfrm_l; /**<Rx Frame counter */ 123 uint32_t rfrm_u; 124 uint32_t rfcs_l; /**<Rx frame check seq error */ 125 uint32_t rfcs_u; 126 uint32_t rvlan_l; /**<Rx Vlan Frame Counter */ 127 uint32_t rvlan_u; 128 uint32_t rerr_l; /**<Rx Frame error */ 129 uint32_t rerr_u; 130 uint32_t ruca_l; /**<Rx Unicast */ 131 uint32_t ruca_u; 132 uint32_t rmca_l; /**<Rx Multicast */ 133 uint32_t rmca_u; 134 uint32_t rbca_l; /**<Rx Broadcast */ 135 uint32_t rbca_u; 136 uint32_t rdrp_l; /**<Rx Dropper Packet */ 137 uint32_t rdrp_u; 138 uint32_t rpkt_l; /**<Rx packet */ 139 uint32_t rpkt_u; 140 uint32_t rund_l; /**<Rx undersized packets */ 141 uint32_t rund_u; 142 uint32_t r64_l; /**<Rx 64 byte */ 143 uint32_t r64_u; 144 uint32_t r127_l; 145 uint32_t r127_u; 146 uint32_t r255_l; 147 uint32_t r255_u; 148 uint32_t r511_l; 149 uint32_t r511_u; 150 uint32_t r1023_l; 151 uint32_t r1023_u; 152 uint32_t r1518_l; 153 uint32_t r1518_u; 154 uint32_t r1519x_l; 155 uint32_t r1519x_u; 156 uint32_t rovr_l; /**<Rx oversized but good */ 157 uint32_t rovr_u; 158 uint32_t rjbr_l; /**<Rx oversized with bad csum */ 159 uint32_t rjbr_u; 160 uint32_t rfrg_l; /**<Rx fragment Packet */ 161 uint32_t rfrg_u; 162 uint32_t rcnp_l; /**<Rx control packets (0x8808 */ 163 uint32_t rcnp_u; 164 uint32_t rdrntp_l; /**<Rx dropped due to FIFO overflow */ 165 uint32_t rdrntp_u; 166 uint32_t res01d0[12]; 167 /* Tx Statistics Counter */ 168 uint32_t teoct_l; /**<Tx eth octets */ 169 uint32_t teoct_u; 170 uint32_t toct_l; /**<Tx Octets */ 171 uint32_t toct_u; 172 uint32_t res0210[2]; 173 uint32_t txpf_l; /**<Tx valid pause frame */ 174 uint32_t txpf_u; 175 uint32_t tfrm_l; /**<Tx frame counter */ 176 uint32_t tfrm_u; 177 uint32_t tfcs_l; /**<Tx FCS error */ 178 uint32_t tfcs_u; 179 uint32_t tvlan_l; /**<Tx Vlan Frame */ 180 uint32_t tvlan_u; 181 uint32_t terr_l; /**<Tx frame error */ 182 uint32_t terr_u; 183 uint32_t tuca_l; /**<Tx Unicast */ 184 uint32_t tuca_u; 185 uint32_t tmca_l; /**<Tx Multicast */ 186 uint32_t tmca_u; 187 uint32_t tbca_l; /**<Tx Broadcast */ 188 uint32_t tbca_u; 189 uint32_t res0258[2]; 190 uint32_t tpkt_l; /**<Tx Packet */ 191 uint32_t tpkt_u; 192 uint32_t tund_l; /**<Tx Undersized */ 193 uint32_t tund_u; 194 uint32_t t64_l; 195 uint32_t t64_u; 196 uint32_t t127_l; 197 uint32_t t127_u; 198 uint32_t t255_l; 199 uint32_t t255_u; 200 uint32_t t511_l; 201 uint32_t t511_u; 202 uint32_t t1023_l; 203 uint32_t t1023_u; 204 uint32_t t1518_l; 205 uint32_t t1518_u; 206 uint32_t t1519x_l; 207 uint32_t t1519x_u; 208 uint32_t res02a8[6]; 209 uint32_t tcnp_l; /**<Tx Control Packet type - 0x8808 */ 210 uint32_t tcnp_u; 211 uint32_t res02c8[14]; 212 /* Line Interface Control */ 213 uint32_t if_mode; /**< 0x300 Interface Mode Control */ 214 uint32_t if_status; /**< 0x304 Interface Status */ 215 uint32_t res0308[14]; 216 /* HiGig/2 */ 217 uint32_t hg_config; /**< 0x340 Control and cfg */ 218 uint32_t res0344[3]; 219 uint32_t hg_pause_quanta; /**< 0x350 Pause quanta */ 220 uint32_t res0354[3]; 221 uint32_t hg_pause_thresh; /**< 0x360 Pause quanta threshold */ 222 uint32_t res0364[3]; 223 uint32_t hgrx_pause_status; /**< 0x370 Receive pause status */ 224 uint32_t hg_fifos_status; /**< 0x374 fifos status */ 225 uint32_t rhm; /**< 0x378 rx messages counter */ 226 uint32_t thm; /**< 0x37C tx messages counter */ 227 }; 228 229 #define BMI_PORT_CFG_FDOVR 0x02000000 230 231 struct rx_bmi_regs { 232 uint32_t fmbm_rcfg; /**< Rx Configuration */ 233 uint32_t fmbm_rst; /**< Rx Status */ 234 uint32_t fmbm_rda; /**< Rx DMA attributes*/ 235 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/ 236 uint32_t fmbm_rfed; /**< Rx Frame End Data*/ 237 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/ 238 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/ 239 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/ 240 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/ 241 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/ 242 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/ 243 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/ 244 uint32_t fmbm_rpp; /**< Rx Policer Profile */ 245 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */ 246 uint32_t fmbm_reth; /**< Rx Excessive Threshold */ 247 uint32_t reserved003c[1]; /**< (0x03C 0x03F) */ 248 uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; 249 /**< Rx Parse Results Array Init*/ 250 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/ 251 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/ 252 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/ 253 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/ 254 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */ 255 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */ 256 uint32_t fmbm_rcmne; 257 /**< Rx Frame Continuous Mode Next Engine */ 258 uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */ 259 uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; 260 /**< Buffer Manager pool Information-*/ 261 uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; 262 /**< Allocate Counter-*/ 263 uint32_t reserved0130[8]; 264 /**< 0x130/0x140 - 0x15F reserved -*/ 265 uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM]; 266 /**< Congestion Group Map*/ 267 uint32_t fmbm_mpd; /**< BM Pool Depletion */ 268 uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */ 269 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/ 270 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/ 271 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/ 272 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/ 273 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/ 274 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/ 275 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/ 276 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/ 277 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/ 278 uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */ 279 uint32_t fmbm_rpc; /**< Rx Performance Counters*/ 280 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/ 281 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/ 282 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/ 283 uint32_t fmbm_rrquc; 284 /**< Rx Receive Queue Utilization cntr*/ 285 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/ 286 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/ 287 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/ 288 uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */ 289 uint32_t fmbm_rdbg; /**< Rx Debug-*/ 290 }; 291 292 struct fman_port_qmi_regs { 293 uint32_t fmqm_pnc; /**< PortID n Configuration Register */ 294 uint32_t fmqm_pns; /**< PortID n Status Register */ 295 uint32_t fmqm_pnts; /**< PortID n Task Status Register */ 296 uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */ 297 uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */ 298 uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */ 299 uint32_t reserved024[2]; /**< 0xn024 - 0x02B */ 300 uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */ 301 uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */ 302 uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */ 303 uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */ 304 uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */ 305 }; 306 307 /* This struct exports parameters about an Fman network interface, determined 308 * from the device-tree. 309 */ 310 struct fman_if { 311 /* Which Fman this interface belongs to */ 312 uint8_t fman_idx; 313 /* The type/speed of the interface */ 314 enum fman_mac_type mac_type; 315 /* Boolean, set when mac type is memac */ 316 uint8_t is_memac; 317 /* Boolean, set when PHY is RGMII */ 318 uint8_t is_rgmii; 319 /* The index of this MAC (within the Fman it belongs to) */ 320 uint8_t mac_idx; 321 /* The MAC address */ 322 struct rte_ether_addr mac_addr; 323 /* The Qman channel to schedule Tx FQs to */ 324 u16 tx_channel_id; 325 326 uint8_t base_profile_id; 327 uint8_t num_profiles; 328 329 uint8_t is_shared_mac; 330 /* The hard-coded FQIDs for this interface. Note: this doesn't cover 331 * the PCD nor the "Rx default" FQIDs, which are configured via FMC 332 * and its XML-based configuration. 333 */ 334 uint32_t fqid_rx_def; 335 uint32_t fqid_rx_err; 336 uint32_t fqid_tx_err; 337 uint32_t fqid_tx_confirm; 338 339 struct list_head bpool_list; 340 /* The node for linking this interface into "fman_if_list" */ 341 struct list_head node; 342 }; 343 344 /* This struct exposes parameters for buffer pools, extracted from the network 345 * interface settings in the device tree. 346 */ 347 struct fman_if_bpool { 348 uint32_t bpid; 349 uint64_t count; 350 uint64_t size; 351 uint64_t addr; 352 /* The node for linking this bpool into fman_if::bpool_list */ 353 struct list_head node; 354 }; 355 356 /* Internal Context transfer params - FMBM_RICP*/ 357 struct fman_if_ic_params { 358 /*IC offset in the packet buffer */ 359 uint16_t iceof; 360 /*IC internal offset */ 361 uint16_t iciof; 362 /*IC size to copy */ 363 uint16_t icsz; 364 }; 365 366 /* The exported "struct fman_if" type contains the subset of fields we want 367 * exposed. This struct is embedded in a larger "struct __fman_if" which 368 * contains the extra bits we *don't* want exposed. 369 */ 370 struct __fman_if { 371 struct fman_if __if; 372 char node_name[IF_NAME_MAX_LEN]; 373 char node_path[PATH_MAX]; 374 uint64_t regs_size; 375 void *ccsr_map; 376 void *bmi_map; 377 void *qmi_map; 378 struct list_head node; 379 }; 380 381 /* And this is the base list node that the interfaces are added to. (See 382 * fman_if_enable_all_rx() below for an example of its use.) 383 */ 384 extern const struct list_head *fman_if_list; 385 386 extern int fman_ccsr_map_fd; 387 388 /* To iterate the "bpool_list" for an interface. Eg; 389 * struct fman_if *p = get_ptr_to_some_interface(); 390 * struct fman_if_bpool *bp; 391 * printf("Interface uses following BPIDs;\n"); 392 * fman_if_for_each_bpool(bp, p) { 393 * printf(" %d\n", bp->bpid); 394 * [...] 395 * } 396 */ 397 #define fman_if_for_each_bpool(bp, __if) \ 398 list_for_each_entry(bp, &(__if)->bpool_list, node) 399 400 #define FMAN_ERR(rc, fmt, args...) \ 401 do { \ 402 _errno = (rc); \ 403 DPAA_BUS_LOG(ERR, fmt "(%d)", ##args, errno); \ 404 } while (0) 405 406 #define FMAN_IP_REV_1 0xC30C4 407 #define FMAN_IP_REV_1_MAJOR_MASK 0x0000FF00 408 #define FMAN_IP_REV_1_MAJOR_SHIFT 8 409 #define FMAN_V3 0x06 410 #define FMAN_V3_CONTEXTA_EN_A2V 0x10000000 411 #define FMAN_V3_CONTEXTA_EN_OVOM 0x02000000 412 #define FMAN_V3_CONTEXTA_EN_EBD 0x80000000 413 #define FMAN_CONTEXTA_DIS_CHECKSUM 0x7ull 414 #define FMAN_CONTEXTA_SET_OPCODE11 0x2000000b00000000 415 extern u16 fman_ip_rev; 416 extern u32 fman_dealloc_bufs_mask_hi; 417 extern u32 fman_dealloc_bufs_mask_lo; 418 419 /** 420 * Initialize the FMAN driver 421 * 422 * @args void 423 * @return 424 * 0 for success; error OTHERWISE 425 */ 426 int fman_init(void); 427 428 /** 429 * Teardown the FMAN driver 430 * 431 * @args void 432 * @return void 433 */ 434 void fman_finish(void); 435 436 #endif /* __FMAN_H */ 437