1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2010-2012 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright 2019-2023 NXP 6 * 7 */ 8 9 #ifndef __FMAN_H 10 #define __FMAN_H 11 12 #include <stdbool.h> 13 #include <net/if.h> 14 15 #include <ethdev_driver.h> 16 #include <rte_ether.h> 17 18 #include <compat.h> 19 #include <dpaa_list.h> 20 21 #ifndef FMAN_DEVICE_PATH 22 #define FMAN_DEVICE_PATH "/dev/mem" 23 #endif 24 25 #define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */ 26 27 /* Control and Configuration Register (COMMAND_CONFIG) for MEMAC */ 28 #define CMD_CFG_LOOPBACK_EN 0x00000400 29 /**< 21 XGMII/GMII loopback enable */ 30 #define CMD_CFG_PROMIS_EN 0x00000010 31 /**< 27 Promiscuous operation enable */ 32 #define CMD_CFG_PAUSE_IGNORE 0x00000100 33 /**< 23 Ignore Pause frame quanta */ 34 35 /* Statistics Configuration Register (STATN_CONFIG) */ 36 #define STATS_CFG_CLR 0x00000004 37 /**< 29 Reset all counters */ 38 #define STATS_CFG_CLR_ON_RD 0x00000002 39 /**< 30 Clear on read */ 40 #define STATS_CFG_SATURATE 0x00000001 41 /**< 31 Saturate at the maximum val */ 42 43 /**< Max receive frame length mask */ 44 #define MAXFRM_SIZE_MEMAC 0x00007fe0 45 #define MAXFRM_RX_MASK 0x0000ffff 46 47 /**< Interface Mode Register Register for MEMAC */ 48 #define IF_MODE_RLP 0x00000820 49 50 /**< Pool Limits */ 51 #define FMAN_PORT_MAX_EXT_POOLS_NUM 8 52 #define FMAN_PORT_OBS_EXT_POOLS_NUM 2 53 54 #define FMAN_PORT_CG_MAP_NUM 8 55 #define FMAN_PORT_PRS_RESULT_WORDS_NUM 8 56 #define FMAN_PORT_BMI_FIFO_UNITS 0x100 57 #define FMAN_PORT_IC_OFFSET_UNITS 0x10 58 59 #define FMAN_BMI_COUNTERS_EN 0x80000000 60 61 #define FMAN_ENABLE_BPOOL_DEPLETION 0xF00000F0 62 63 #define HASH_CTRL_MCAST_EN 0x00000100 64 #define GROUP_ADDRESS 0x0000010000000000LL 65 #define HASH_CTRL_ADDR_MASK 0x0000003F 66 67 #define FMAN_RTC_MAX_NUM_OF_ALARMS 3 68 #define FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES 4 69 #define FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS 3 70 #define FMAN_IEEE_1588_OFFSET 0X1AFE000 71 #define FMAN_IEEE_1588_SIZE 4096 72 73 /* Pre definitions of FMAN interface and Bpool structures */ 74 struct __fman_if; 75 struct fman_if_bpool; 76 /* Lists of fman interfaces and bpools */ 77 TAILQ_HEAD(rte_fman_if_list, __fman_if); 78 79 /* Represents the different flavour of network interface */ 80 enum fman_mac_type { 81 fman_offline_internal = 0, 82 fman_mac_1g, 83 fman_mac_10g, 84 fman_mac_2_5g, 85 fman_onic, 86 }; 87 88 struct mac_addr { 89 uint32_t mac_addr_l; /**< Lower 32 bits of 48-bit MAC address */ 90 uint32_t mac_addr_u; /**< Upper 16 bits of 48-bit MAC address */ 91 }; 92 93 struct memac_regs { 94 /* General Control and Status */ 95 uint32_t res0000[2]; 96 uint32_t command_config; /**< 0x008 Ctrl and cfg */ 97 struct mac_addr mac_addr0; /**< 0x00C-0x010 MAC_ADDR_0...1 */ 98 uint32_t maxfrm; /**< 0x014 Max frame length */ 99 uint32_t res0018[5]; 100 uint32_t hashtable_ctrl; /**< 0x02C Hash table control */ 101 uint32_t res0030[4]; 102 uint32_t ievent; /**< 0x040 Interrupt event */ 103 uint32_t tx_ipg_length; 104 /**< 0x044 Transmitter inter-packet-gap */ 105 uint32_t res0048; 106 uint32_t imask; /**< 0x04C Interrupt mask */ 107 uint32_t res0050; 108 uint32_t pause_quanta[4]; /**< 0x054 Pause quanta */ 109 uint32_t pause_thresh[4]; /**< 0x064 Pause quanta threshold */ 110 uint32_t rx_pause_status; /**< 0x074 Receive pause status */ 111 uint32_t res0078[2]; 112 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS]; 113 /**< 0x80-0x0B4 mac padr */ 114 uint32_t lpwake_timer; 115 /**< 0x0B8 Low Power Wakeup Timer */ 116 uint32_t sleep_timer; 117 /**< 0x0BC Transmit EEE Low Power Timer */ 118 uint32_t res00c0[8]; 119 uint32_t statn_config; 120 /**< 0x0E0 Statistics configuration */ 121 uint32_t res00e4[7]; 122 /* Rx Statistics Counter */ 123 uint32_t reoct_l; /**<Rx Eth Octets Counter */ 124 uint32_t reoct_u; 125 uint32_t roct_l; /**<Rx Octet Counters */ 126 uint32_t roct_u; 127 uint32_t raln_l; /**<Rx Alignment Error Counter */ 128 uint32_t raln_u; 129 uint32_t rxpf_l; /**<Rx valid Pause Frame */ 130 uint32_t rxpf_u; 131 uint32_t rfrm_l; /**<Rx Frame counter */ 132 uint32_t rfrm_u; 133 uint32_t rfcs_l; /**<Rx frame check seq error */ 134 uint32_t rfcs_u; 135 uint32_t rvlan_l; /**<Rx Vlan Frame Counter */ 136 uint32_t rvlan_u; 137 uint32_t rerr_l; /**<Rx Frame error */ 138 uint32_t rerr_u; 139 uint32_t ruca_l; /**<Rx Unicast */ 140 uint32_t ruca_u; 141 uint32_t rmca_l; /**<Rx Multicast */ 142 uint32_t rmca_u; 143 uint32_t rbca_l; /**<Rx Broadcast */ 144 uint32_t rbca_u; 145 uint32_t rdrp_l; /**<Rx Dropper Packet */ 146 uint32_t rdrp_u; 147 uint32_t rpkt_l; /**<Rx packet */ 148 uint32_t rpkt_u; 149 uint32_t rund_l; /**<Rx undersized packets */ 150 uint32_t rund_u; 151 uint32_t r64_l; /**<Rx 64 byte */ 152 uint32_t r64_u; 153 uint32_t r127_l; 154 uint32_t r127_u; 155 uint32_t r255_l; 156 uint32_t r255_u; 157 uint32_t r511_l; 158 uint32_t r511_u; 159 uint32_t r1023_l; 160 uint32_t r1023_u; 161 uint32_t r1518_l; 162 uint32_t r1518_u; 163 uint32_t r1519x_l; 164 uint32_t r1519x_u; 165 uint32_t rovr_l; /**<Rx oversized but good */ 166 uint32_t rovr_u; 167 uint32_t rjbr_l; /**<Rx oversized with bad csum */ 168 uint32_t rjbr_u; 169 uint32_t rfrg_l; /**<Rx fragment Packet */ 170 uint32_t rfrg_u; 171 uint32_t rcnp_l; /**<Rx control packets (0x8808 */ 172 uint32_t rcnp_u; 173 uint32_t rdrntp_l; /**<Rx dropped due to FIFO overflow */ 174 uint32_t rdrntp_u; 175 uint32_t res01d0[12]; 176 /* Tx Statistics Counter */ 177 uint32_t teoct_l; /**<Tx eth octets */ 178 uint32_t teoct_u; 179 uint32_t toct_l; /**<Tx Octets */ 180 uint32_t toct_u; 181 uint32_t res0210[2]; 182 uint32_t txpf_l; /**<Tx valid pause frame */ 183 uint32_t txpf_u; 184 uint32_t tfrm_l; /**<Tx frame counter */ 185 uint32_t tfrm_u; 186 uint32_t tfcs_l; /**<Tx FCS error */ 187 uint32_t tfcs_u; 188 uint32_t tvlan_l; /**<Tx Vlan Frame */ 189 uint32_t tvlan_u; 190 uint32_t terr_l; /**<Tx frame error */ 191 uint32_t terr_u; 192 uint32_t tuca_l; /**<Tx Unicast */ 193 uint32_t tuca_u; 194 uint32_t tmca_l; /**<Tx Multicast */ 195 uint32_t tmca_u; 196 uint32_t tbca_l; /**<Tx Broadcast */ 197 uint32_t tbca_u; 198 uint32_t res0258[2]; 199 uint32_t tpkt_l; /**<Tx Packet */ 200 uint32_t tpkt_u; 201 uint32_t tund_l; /**<Tx Undersized */ 202 uint32_t tund_u; 203 uint32_t t64_l; 204 uint32_t t64_u; 205 uint32_t t127_l; 206 uint32_t t127_u; 207 uint32_t t255_l; 208 uint32_t t255_u; 209 uint32_t t511_l; 210 uint32_t t511_u; 211 uint32_t t1023_l; 212 uint32_t t1023_u; 213 uint32_t t1518_l; 214 uint32_t t1518_u; 215 uint32_t t1519x_l; 216 uint32_t t1519x_u; 217 uint32_t res02a8[6]; 218 uint32_t tcnp_l; /**<Tx Control Packet type - 0x8808 */ 219 uint32_t tcnp_u; 220 uint32_t res02c8[14]; 221 /* Line Interface Control */ 222 uint32_t if_mode; /**< 0x300 Interface Mode Control */ 223 uint32_t if_status; /**< 0x304 Interface Status */ 224 uint32_t res0308[14]; 225 /* HiGig/2 */ 226 uint32_t hg_config; /**< 0x340 Control and cfg */ 227 uint32_t res0344[3]; 228 uint32_t hg_pause_quanta; /**< 0x350 Pause quanta */ 229 uint32_t res0354[3]; 230 uint32_t hg_pause_thresh; /**< 0x360 Pause quanta threshold */ 231 uint32_t res0364[3]; 232 uint32_t hgrx_pause_status; /**< 0x370 Receive pause status */ 233 uint32_t hg_fifos_status; /**< 0x374 fifos status */ 234 uint32_t rhm; /**< 0x378 rx messages counter */ 235 uint32_t thm; /**< 0x37C tx messages counter */ 236 }; 237 238 #define BMI_PORT_CFG_FDOVR 0x02000000 239 240 struct rx_bmi_regs { 241 uint32_t fmbm_rcfg; /**< Rx Configuration */ 242 uint32_t fmbm_rst; /**< Rx Status */ 243 uint32_t fmbm_rda; /**< Rx DMA attributes*/ 244 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/ 245 uint32_t fmbm_rfed; /**< Rx Frame End Data*/ 246 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/ 247 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/ 248 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/ 249 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/ 250 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/ 251 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/ 252 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/ 253 uint32_t fmbm_rpp; /**< Rx Policer Profile */ 254 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */ 255 uint32_t fmbm_reth; /**< Rx Excessive Threshold */ 256 uint32_t reserved003c[1]; /**< (0x03C 0x03F) */ 257 uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; 258 /**< Rx Parse Results Array Init*/ 259 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/ 260 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/ 261 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/ 262 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/ 263 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */ 264 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */ 265 uint32_t fmbm_rcmne; 266 /**< Rx Frame Continuous Mode Next Engine */ 267 uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */ 268 uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; 269 /**< Buffer Manager pool Information-*/ 270 uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; 271 /**< Allocate Counter-*/ 272 uint32_t reserved0120[16]; 273 /**< 0x130/0x140 - 0x15F reserved -*/ 274 uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM]; 275 /**< Congestion Group Map*/ 276 uint32_t fmbm_mpd; /**< BM Pool Depletion */ 277 uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */ 278 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/ 279 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/ 280 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/ 281 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/ 282 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/ 283 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/ 284 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/ 285 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/ 286 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/ 287 uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */ 288 uint32_t fmbm_rpc; /**< Rx Performance Counters*/ 289 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/ 290 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/ 291 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/ 292 uint32_t fmbm_rrquc; 293 /**< Rx Receive Queue Utilization cntr*/ 294 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/ 295 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/ 296 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/ 297 uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */ 298 uint32_t fmbm_rdbg; /**< Rx Debug-*/ 299 }; 300 301 struct tx_bmi_regs { 302 uint32_t fmbm_tcfg; /**< Tx Configuration*/ 303 uint32_t fmbm_tst; /**< Tx Status*/ 304 uint32_t fmbm_tda; /**< Tx DMA attributes*/ 305 uint32_t fmbm_tfp; /**< Tx FIFO Parameters*/ 306 uint32_t fmbm_tfed; /**< Tx Frame End Data*/ 307 uint32_t fmbm_ticp; /**< Tx Internal Context Parameters*/ 308 uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine*/ 309 uint32_t fmbm_tfca; /**< Tx Frame Attributes*/ 310 uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID*/ 311 uint32_t fmbm_tefqid; /**< Tx Error Frame Queue ID*/ 312 uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine*/ 313 uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale*/ 314 uint32_t fmbm_trlmt; /**< Tx Rate Limiter*/ 315 }; 316 317 /* Description FM RTC timer alarm */ 318 struct t_tmr_alarm { 319 uint32_t tmr_alarm_h; 320 uint32_t tmr_alarm_l; 321 }; 322 323 /* Description FM RTC timer Ex trigger */ 324 struct t_tmr_ext_trigger { 325 uint32_t tmr_etts_h; 326 uint32_t tmr_etts_l; 327 }; 328 329 struct rtc_regs { 330 uint32_t tmr_id; /* 0x000 Module ID register */ 331 uint32_t tmr_id2; /* 0x004 Controller ID register */ 332 uint32_t reserved0008[30]; 333 uint32_t tmr_ctrl; /* 0x0080 timer control register */ 334 uint32_t tmr_tevent; /* 0x0084 timer event register */ 335 uint32_t tmr_temask; /* 0x0088 timer event mask register */ 336 uint32_t reserved008c[3]; 337 uint32_t tmr_cnt_h; /* 0x0098 timer counter high register */ 338 uint32_t tmr_cnt_l; /* 0x009c timer counter low register */ 339 uint32_t tmr_add; /* 0x00a0 timer drift compensation addend register */ 340 uint32_t tmr_acc; /* 0x00a4 timer accumulator register */ 341 uint32_t tmr_prsc; /* 0x00a8 timer prescale */ 342 uint32_t reserved00ac; 343 uint32_t tmr_off_h; /* 0x00b0 timer offset high */ 344 uint32_t tmr_off_l; /* 0x00b4 timer offset low */ 345 struct t_tmr_alarm tmr_alarm[FMAN_RTC_MAX_NUM_OF_ALARMS]; 346 /* 0x00b8 timer alarm */ 347 uint32_t tmr_fiper[FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES]; 348 /* 0x00d0 timer fixed period interval */ 349 struct t_tmr_ext_trigger tmr_etts[FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS]; 350 /* 0x00e0 time stamp general purpose external */ 351 uint32_t reserved00f0[4]; 352 }; 353 354 struct fman_port_qmi_regs { 355 uint32_t fmqm_pnc; /**< PortID n Configuration Register */ 356 uint32_t fmqm_pns; /**< PortID n Status Register */ 357 uint32_t fmqm_pnts; /**< PortID n Task Status Register */ 358 uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */ 359 uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */ 360 uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */ 361 uint32_t reserved024[2]; /**< 0xn024 - 0x02B */ 362 uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */ 363 uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */ 364 uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */ 365 uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */ 366 uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */ 367 }; 368 369 struct onic_port_cfg { 370 char macless_name[IF_NAME_MAX_LEN]; 371 uint32_t rx_start; 372 uint32_t rx_count; 373 uint32_t tx_start; 374 uint32_t tx_count; 375 struct rte_ether_addr src_mac; 376 struct rte_ether_addr peer_mac; 377 }; 378 379 /* This struct exports parameters about an Fman network interface, determined 380 * from the device-tree. 381 */ 382 struct fman_if { 383 /* Which Fman this interface belongs to */ 384 uint8_t fman_idx; 385 /* The type/speed of the interface */ 386 enum fman_mac_type mac_type; 387 /* Boolean, set when mac type is memac */ 388 uint8_t is_memac; 389 /* Boolean, set when PHY is RGMII */ 390 uint8_t is_rgmii; 391 /* The index of this MAC (within the Fman it belongs to) */ 392 uint8_t mac_idx; 393 /* The MAC address */ 394 struct rte_ether_addr mac_addr; 395 /* The Qman channel to schedule Tx FQs to */ 396 u16 tx_channel_id; 397 398 uint8_t base_profile_id; 399 uint8_t num_profiles; 400 401 uint8_t is_shared_mac; 402 /* The hard-coded FQIDs for this interface. Note: this doesn't cover 403 * the PCD nor the "Rx default" FQIDs, which are configured via FMC 404 * and its XML-based configuration. These values are being parsed from 405 * kernel device tree. 406 */ 407 uint32_t fqid_rx_pcd; 408 uint32_t fqid_rx_pcd_count; 409 uint32_t fqid_rx_def; 410 uint32_t fqid_rx_err; 411 uint32_t fqid_tx_err; 412 uint32_t fqid_tx_confirm; 413 414 /* oNIC port info */ 415 struct onic_port_cfg onic_info; 416 417 struct list_head bpool_list; 418 /* The node for linking this interface into "fman_if_list" */ 419 struct list_head node; 420 }; 421 422 /* This struct exposes parameters for buffer pools, extracted from the network 423 * interface settings in the device tree. 424 */ 425 struct fman_if_bpool { 426 uint32_t bpid; 427 uint64_t count; 428 uint64_t size; 429 uint64_t addr; 430 /* The node for linking this bpool into fman_if::bpool_list */ 431 struct list_head node; 432 }; 433 434 /* Internal Context transfer params - FMBM_RICP*/ 435 struct fman_if_ic_params { 436 /*IC offset in the packet buffer */ 437 uint16_t iceof; 438 /*IC internal offset */ 439 uint16_t iciof; 440 /*IC size to copy */ 441 uint16_t icsz; 442 }; 443 444 /* The exported "struct fman_if" type contains the subset of fields we want 445 * exposed. This struct is embedded in a larger "struct __fman_if" which 446 * contains the extra bits we *don't* want exposed. 447 */ 448 struct __fman_if { 449 struct fman_if __if; 450 char node_name[IF_NAME_MAX_LEN]; 451 char node_path[PATH_MAX]; 452 uint64_t regs_size; 453 void *ccsr_map; 454 void *bmi_map; 455 void *tx_bmi_map; 456 void *rtc_map; 457 void *qmi_map; 458 struct list_head node; 459 }; 460 461 /* And this is the base list node that the interfaces are added to. (See 462 * fman_if_enable_all_rx() below for an example of its use.) 463 */ 464 extern const struct list_head *fman_if_list; 465 466 extern int fman_ccsr_map_fd; 467 468 /* To iterate the "bpool_list" for an interface. Eg; 469 * struct fman_if *p = get_ptr_to_some_interface(); 470 * struct fman_if_bpool *bp; 471 * printf("Interface uses following BPIDs;\n"); 472 * fman_if_for_each_bpool(bp, p) { 473 * printf(" %d\n", bp->bpid); 474 * [...] 475 * } 476 */ 477 #define fman_if_for_each_bpool(bp, __if) \ 478 list_for_each_entry(bp, &(__if)->bpool_list, node) 479 480 #define FMAN_ERR(rc, fmt, ...) \ 481 do { \ 482 _errno = (rc); \ 483 RTE_LOG_LINE(ERR, DPAA_BUS, fmt "(%d)", ##__VA_ARGS__, errno); \ 484 } while (0) 485 486 #define FMAN_IP_REV_1 0xC30C4 487 #define FMAN_IP_REV_1_MAJOR_MASK 0x0000FF00 488 #define FMAN_IP_REV_1_MAJOR_SHIFT 8 489 #define FMAN_V3 0x06 490 491 #define DPAA_FQD_CTX_A_SHIFT_BITS 24 492 #define DPAA_FQD_CTX_B_SHIFT_BITS 24 493 494 /* Following flags are used to set in context A hi field of FQD */ 495 #define DPAA_FQD_CTX_A_OVERRIDE_FQ (0x80 << DPAA_FQD_CTX_A_SHIFT_BITS) 496 #define DPAA_FQD_CTX_A_IGNORE_CMD (0x40 << DPAA_FQD_CTX_A_SHIFT_BITS) 497 #define DPAA_FQD_CTX_A_A1_FIELD_VALID (0x20 << DPAA_FQD_CTX_A_SHIFT_BITS) 498 #define DPAA_FQD_CTX_A_A2_FIELD_VALID (0x10 << DPAA_FQD_CTX_A_SHIFT_BITS) 499 #define DPAA_FQD_CTX_A_A0_FIELD_VALID (0x08 << DPAA_FQD_CTX_A_SHIFT_BITS) 500 #define DPAA_FQD_CTX_A_B0_FIELD_VALID (0x04 << DPAA_FQD_CTX_A_SHIFT_BITS) 501 #define DPAA_FQD_CTX_A_OVERRIDE_OMB (0x02 << DPAA_FQD_CTX_A_SHIFT_BITS) 502 #define DPAA_FQD_CTX_A_RESERVED (0x01 << DPAA_FQD_CTX_A_SHIFT_BITS) 503 504 /* Following flags are used to set in context A lo field of FQD */ 505 #define DPAA_FQD_CTX_A2_EBD_BIT (0x80 << DPAA_FQD_CTX_A_SHIFT_BITS) 506 #define DPAA_FQD_CTX_A2_EBAD_BIT (0x40 << DPAA_FQD_CTX_A_SHIFT_BITS) 507 #define DPAA_FQD_CTX_A2_FWD_BIT (0x20 << DPAA_FQD_CTX_A_SHIFT_BITS) 508 #define DPAA_FQD_CTX_A2_NL_BIT (0x10 << DPAA_FQD_CTX_A_SHIFT_BITS) 509 #define DPAA_FQD_CTX_A2_CWD_BIT (0x08 << DPAA_FQD_CTX_A_SHIFT_BITS) 510 #define DPAA_FQD_CTX_A2_NENQ_BIT (0x04 << DPAA_FQD_CTX_A_SHIFT_BITS) 511 #define DPAA_FQD_CTX_A2_RESERVED_BIT (0x02 << DPAA_FQD_CTX_A_SHIFT_BITS) 512 #define DPAA_FQD_CTX_A2_VSPE_BIT (0x01 << DPAA_FQD_CTX_A_SHIFT_BITS) 513 514 extern u16 fman_ip_rev; 515 extern u32 fman_dealloc_bufs_mask_hi; 516 extern u32 fman_dealloc_bufs_mask_lo; 517 518 /** 519 * Initialize the FMAN driver 520 * 521 * @args void 522 * @return 523 * 0 for success; error OTHERWISE 524 */ 525 int fman_init(void); 526 527 /** 528 * Teardown the FMAN driver 529 * 530 * @args void 531 * @return void 532 */ 533 void fman_finish(void); 534 535 #endif /* __FMAN_H */ 536