1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2022 Intel Corporation 3 */ 4 5 #ifndef _VC_5GNR_PMD_H_ 6 #define _VC_5GNR_PMD_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 /* VC 5GNR FPGA FEC PCI vendor & device IDs. */ 12 #define VC_5GNR_VENDOR_ID (0x8086) 13 #define VC_5GNR_PF_DEVICE_ID (0x0D8F) 14 #define VC_5GNR_VF_DEVICE_ID (0x0D90) 15 16 #define VC_5GNR_NUM_UL_QUEUES (32) 17 #define VC_5GNR_NUM_DL_QUEUES (32) 18 #define VC_5GNR_TOTAL_NUM_QUEUES (VC_5GNR_NUM_UL_QUEUES + VC_5GNR_NUM_DL_QUEUES) 19 20 /* VC 5GNR Ring size is in 256 bits (32 bytes) units. */ 21 #define VC_5GNR_RING_DESC_LEN_UNIT_BYTES (32) 22 23 /* Align DMA descriptors to 256 bytes - cache-aligned. */ 24 #define VC_5GNR_RING_DESC_ENTRY_LENGTH (8) 25 26 /* VC 5GNR FPGA Register mapping on BAR0. */ 27 enum { 28 VC_5GNR_CONFIGURATION = 0x00000004, /* len: 2B. */ 29 VC_5GNR_QUEUE_MAP = 0x00000040 /* len: 256B. */ 30 }; 31 32 /* VC 5GNR FPGA FEC DESCRIPTOR ERROR. */ 33 enum { 34 VC_5GNR_DESC_ERR_NO_ERR = 0x0, 35 VC_5GNR_DESC_ERR_K_P_OUT_OF_RANGE = 0x1, 36 VC_5GNR_DESC_ERR_Z_C_NOT_LEGAL = 0x2, 37 VC_5GNR_DESC_ERR_DESC_OFFSET_ERR = 0x3, 38 VC_5GNR_DESC_ERR_DESC_READ_FAIL = 0x8, 39 VC_5GNR_DESC_ERR_DESC_READ_TIMEOUT = 0x9, 40 VC_5GNR_DESC_ERR_DESC_READ_TLP_POISONED = 0xA, 41 VC_5GNR_DESC_ERR_HARQ_INPUT_LEN = 0xB, 42 VC_5GNR_DESC_ERR_CB_READ_FAIL = 0xC, 43 VC_5GNR_DESC_ERR_CB_READ_TIMEOUT = 0xD, 44 VC_5GNR_DESC_ERR_CB_READ_TLP_POISONED = 0xE, 45 VC_5GNR_DESC_ERR_HBSTORE_ERR = 0xF 46 }; 47 48 /* VC 5GNR FPGA FEC DMA Encoding Request Descriptor. */ 49 struct __rte_packed_begin vc_5gnr_dma_enc_desc { 50 uint32_t done:1, 51 rsrvd0:7, 52 error:4, 53 rsrvd1:4, 54 num_null:10, 55 rsrvd2:6; 56 uint32_t ncb:15, 57 rsrvd3:1, 58 k0:16; 59 uint32_t irq_en:1, 60 crc_en:1, 61 rsrvd4:1, 62 qm_idx:3, 63 bg_idx:1, 64 zc:9, 65 desc_idx:10, 66 rsrvd5:6; 67 uint16_t rm_e; 68 uint16_t k_; 69 uint32_t out_addr_lw; 70 uint32_t out_addr_hi; 71 uint32_t in_addr_lw; 72 uint32_t in_addr_hi; 73 74 union { 75 struct { 76 /** Virtual addresses used to retrieve SW context info. */ 77 void *op_addr; 78 /** Stores information about total number of Code Blocks 79 * in currently processed Transport Block. 80 */ 81 uint64_t cbs_in_op; 82 }; 83 84 uint8_t sw_ctxt[VC_5GNR_RING_DESC_LEN_UNIT_BYTES * 85 (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; 86 }; 87 } __rte_packed_end; 88 89 /* VC 5GNR FPGA DPC FEC DMA Decoding Request Descriptor. */ 90 struct __rte_packed_begin vc_5gnr_dma_dec_desc { 91 uint32_t done:1, 92 iter:5, 93 et_pass:1, 94 crcb_pass:1, 95 error:4, 96 qm_idx:3, 97 max_iter:5, 98 bg_idx:1, 99 rsrvd0:1, 100 harqin_en:1, 101 zc:9; 102 uint32_t hbstroe_offset:22, 103 num_null:10; 104 uint32_t irq_en:1, 105 ncb:15, 106 desc_idx:10, 107 drop_crc24b:1, 108 crc24b_ind:1, 109 rv:2, 110 et_dis:1, 111 rsrvd2:1; 112 uint32_t harq_input_length:16, 113 rm_e:16; /**< the inbound data byte length. */ 114 uint32_t out_addr_lw; 115 uint32_t out_addr_hi; 116 uint32_t in_addr_lw; 117 uint32_t in_addr_hi; 118 119 union { 120 struct { 121 /** Virtual addresses used to retrieve SW context info. */ 122 void *op_addr; 123 /** Stores information about total number of Code Blocks 124 * in currently processed Transport Block. 125 */ 126 uint8_t cbs_in_op; 127 }; 128 129 uint32_t sw_ctxt[8 * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; 130 }; 131 } __rte_packed_end; 132 133 /* Vista Creek 5GNR DMA Descriptor. */ 134 union vc_5gnr_dma_desc { 135 struct vc_5gnr_dma_enc_desc enc_req; 136 struct vc_5gnr_dma_dec_desc dec_req; 137 }; 138 139 #endif /* _VC_5GNR_PMD_H_ */ 140