12d430643SNicolas Chautru /* SPDX-License-Identifier: BSD-3-Clause 22d430643SNicolas Chautru * Copyright(c) 2020 Intel Corporation 32d430643SNicolas Chautru */ 42d430643SNicolas Chautru 52d430643SNicolas Chautru #ifndef _RTE_PMD_FPGA_5GNR_FEC_H_ 62d430643SNicolas Chautru #define _RTE_PMD_FPGA_5GNR_FEC_H_ 72d430643SNicolas Chautru 82d430643SNicolas Chautru #include <stdint.h> 92d430643SNicolas Chautru #include <stdbool.h> 102d430643SNicolas Chautru 111094dd94SDavid Marchand #include <rte_compat.h> 121094dd94SDavid Marchand 132d430643SNicolas Chautru /** 142d430643SNicolas Chautru * @file rte_pmd_fpga_5gnr_fec.h 152d430643SNicolas Chautru * 16*10829ff2SHernan Vargas * Functions for configuring VC 5GNR and AGX100 HW, exposed directly to applications. 17*10829ff2SHernan Vargas * Configuration related to encoding/decoding is done through the 182d430643SNicolas Chautru * librte_bbdev library. 192d430643SNicolas Chautru * 202d430643SNicolas Chautru * @warning 212d430643SNicolas Chautru * @b EXPERIMENTAL: this API may change without prior notice 222d430643SNicolas Chautru */ 232d430643SNicolas Chautru 242d430643SNicolas Chautru #ifdef __cplusplus 252d430643SNicolas Chautru extern "C" { 262d430643SNicolas Chautru #endif 272d430643SNicolas Chautru 28*10829ff2SHernan Vargas /** Number of Virtual Functions FPGA 5GNR FEC supports */ 292d430643SNicolas Chautru #define FPGA_5GNR_FEC_NUM_VFS 8 302d430643SNicolas Chautru 312d430643SNicolas Chautru /** 32*10829ff2SHernan Vargas * Structure to pass FPGA 5GNR FEC configuration. 332d430643SNicolas Chautru */ 347adbb468SMaxime Coquelin struct rte_fpga_5gnr_fec_conf { 352d430643SNicolas Chautru /** 1 if PF is used for dataplane, 0 for VFs */ 362d430643SNicolas Chautru bool pf_mode_en; 372d430643SNicolas Chautru /** Number of UL queues per VF */ 382d430643SNicolas Chautru uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS]; 392d430643SNicolas Chautru /** Number of DL queues per VF */ 402d430643SNicolas Chautru uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS]; 41*10829ff2SHernan Vargas /** UL bandwidth. Needed only for VC schedule algorithm */ 422d430643SNicolas Chautru uint8_t ul_bandwidth; 43*10829ff2SHernan Vargas /** DL bandwidth. Needed only for VC schedule algorithm */ 442d430643SNicolas Chautru uint8_t dl_bandwidth; 452d430643SNicolas Chautru /** UL Load Balance */ 462d430643SNicolas Chautru uint8_t ul_load_balance; 472d430643SNicolas Chautru /** DL Load Balance */ 482d430643SNicolas Chautru uint8_t dl_load_balance; 492d430643SNicolas Chautru }; 502d430643SNicolas Chautru 512d430643SNicolas Chautru /** 52*10829ff2SHernan Vargas * Configure a FPGA 5GNR device in PF mode notably for bbdev-test 532d430643SNicolas Chautru * 542d430643SNicolas Chautru * @param dev_name 552d430643SNicolas Chautru * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. 562d430643SNicolas Chautru * It can also be retrieved for a bbdev device from the dev_name field in the 572d430643SNicolas Chautru * rte_bbdev_info structure returned by rte_bbdev_info_get(). 582d430643SNicolas Chautru * @param conf 59*10829ff2SHernan Vargas * Configuration to apply to FPGA 5GNR FEC. 602d430643SNicolas Chautru * 612d430643SNicolas Chautru * @return 622d430643SNicolas Chautru * Zero on success, negative value on failure. 632d430643SNicolas Chautru */ 642d430643SNicolas Chautru __rte_experimental 652d430643SNicolas Chautru int 667adbb468SMaxime Coquelin rte_fpga_5gnr_fec_configure(const char *dev_name, 677adbb468SMaxime Coquelin const struct rte_fpga_5gnr_fec_conf *conf); 682d430643SNicolas Chautru 692d430643SNicolas Chautru #ifdef __cplusplus 702d430643SNicolas Chautru } 712d430643SNicolas Chautru #endif 722d430643SNicolas Chautru 732d430643SNicolas Chautru #endif /* _RTE_PMD_FPGA_5GNR_FEC_H_ */ 74