1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #ifndef _RTE_PMD_FPGA_5GNR_FEC_H_ 6 #define _RTE_PMD_FPGA_5GNR_FEC_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include <rte_compat.h> 12 13 /** 14 * @file rte_pmd_fpga_5gnr_fec.h 15 * 16 * Functions for configuring VC 5GNR and AGX100 HW, exposed directly to applications. 17 * Configuration related to encoding/decoding is done through the 18 * librte_bbdev library. 19 * 20 * @warning 21 * @b EXPERIMENTAL: this API may change without prior notice 22 */ 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /** Number of Virtual Functions FPGA 5GNR FEC supports */ 29 #define FPGA_5GNR_FEC_NUM_VFS 8 30 31 /** 32 * Structure to pass FPGA 5GNR FEC configuration. 33 */ 34 struct rte_fpga_5gnr_fec_conf { 35 /** 1 if PF is used for dataplane, 0 for VFs */ 36 bool pf_mode_en; 37 /** Number of UL queues per VF */ 38 uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS]; 39 /** Number of DL queues per VF */ 40 uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS]; 41 /** UL bandwidth. Needed only for VC schedule algorithm */ 42 uint8_t ul_bandwidth; 43 /** DL bandwidth. Needed only for VC schedule algorithm */ 44 uint8_t dl_bandwidth; 45 /** UL Load Balance */ 46 uint8_t ul_load_balance; 47 /** DL Load Balance */ 48 uint8_t dl_load_balance; 49 }; 50 51 /** 52 * Configure a FPGA 5GNR device in PF mode notably for bbdev-test 53 * 54 * @param dev_name 55 * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. 56 * It can also be retrieved for a bbdev device from the dev_name field in the 57 * rte_bbdev_info structure returned by rte_bbdev_info_get(). 58 * @param conf 59 * Configuration to apply to FPGA 5GNR FEC. 60 * 61 * @return 62 * Zero on success, negative value on failure. 63 */ 64 __rte_experimental 65 int 66 rte_fpga_5gnr_fec_configure(const char *dev_name, 67 const struct rte_fpga_5gnr_fec_conf *conf); 68 69 #ifdef __cplusplus 70 } 71 #endif 72 73 #endif /* _RTE_PMD_FPGA_5GNR_FEC_H_ */ 74