1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #ifndef _FPGA_5GNR_FEC_H_ 6 #define _FPGA_5GNR_FEC_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include "agx100_pmd.h" 12 #include "vc_5gnr_pmd.h" 13 14 /* Helper macro for logging */ 15 #define rte_bbdev_log(level, fmt, ...) \ 16 rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \ 17 ##__VA_ARGS__) 18 19 #ifdef RTE_LIBRTE_BBDEV_DEBUG 20 #define rte_bbdev_log_debug(fmt, ...) \ 21 rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \ 22 ##__VA_ARGS__) 23 #else 24 #define rte_bbdev_log_debug(fmt, ...) 25 #endif 26 27 /* FPGA 5GNR FEC driver names */ 28 #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf 29 #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf 30 31 #define FPGA_5GNR_INVALID_HW_QUEUE_ID (0xFFFFFFFF) 32 #define FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US (1000) 33 #define FPGA_5GNR_HARQ_RDY_TIMEOUT (10) 34 #define FPGA_5GNR_TIMEOUT_CHECK_INTERVAL (5) 35 #define FPGA_5GNR_DDR_OVERFLOW (0x10) 36 #define FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES 8 37 #define FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES 8 38 /* Align DMA descriptors to 256 bytes - cache-aligned. */ 39 #define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8) 40 /* Maximum size of queue. */ 41 #define FPGA_5GNR_RING_MAX_SIZE (1024) 42 43 #define VC_5GNR_FPGA_VARIANT 0 44 #define AGX100_FPGA_VARIANT 1 45 46 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ 47 #define N_ZC_1 66 /* N = 66 Zc for BG 1 */ 48 #define N_ZC_2 50 /* N = 50 Zc for BG 2 */ 49 #define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ 50 #define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ 51 #define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ 52 #define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */ 53 #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ 54 #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ 55 56 /* FPGA 5GNR Ring Control Registers. */ 57 enum { 58 FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008, 59 FPGA_5GNR_FEC_RING_SIZE = 0x00000010, 60 FPGA_5GNR_FEC_RING_MISC = 0x00000014, 61 FPGA_5GNR_FEC_RING_ENABLE = 0x00000015, 62 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016, 63 FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018, 64 FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C 65 }; 66 67 /* VC 5GNR and AGX100 common register mapping on BAR0. */ 68 enum { 69 FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */ 70 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */ 71 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */ 72 FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */ 73 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */ 74 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */ 75 FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */ 76 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */ 77 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */ 78 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */ 79 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */ 80 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */ 81 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */ 82 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */ 83 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */ 84 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */ 85 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */ 86 FPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */ 87 FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /**< len: 4B. */ 88 }; 89 90 /* FPGA 5GNR Ring Control Register. */ 91 struct __rte_packed fpga_5gnr_ring_ctrl_reg { 92 uint64_t ring_base_addr; 93 uint64_t ring_head_addr; 94 uint16_t ring_size:11; 95 uint16_t rsrvd0; 96 union { /* Miscellaneous register */ 97 uint8_t misc; 98 uint8_t max_ul_dec:5, 99 max_ul_dec_en:1, 100 rsrvd1:2; 101 }; 102 uint8_t enable; 103 uint8_t flush_queue_en; 104 uint8_t rsrvd2; 105 uint16_t shadow_tail; 106 uint16_t rsrvd3; 107 uint16_t head_point; 108 uint16_t rsrvd4; 109 }; 110 111 /* Private data structure for each FPGA 5GNR device. */ 112 struct fpga_5gnr_fec_device { 113 /** Base address of MMIO registers (BAR0). */ 114 void *mmio_base; 115 /** Base address of memory for sw rings. */ 116 void *sw_rings; 117 /** Physical address of sw_rings. */ 118 rte_iova_t sw_rings_phys; 119 /** Number of bytes available for each queue in device. */ 120 uint32_t sw_ring_size; 121 /** Max number of entries available for each queue in device. */ 122 uint32_t sw_ring_max_depth; 123 /** Base address of response tail pointer buffer. */ 124 uint32_t *tail_ptrs; 125 /** Physical address of tail pointers. */ 126 rte_iova_t tail_ptr_phys; 127 /** Queues flush completion flag. */ 128 uint64_t *flush_queue_status; 129 /** Bitmap capturing which Queues are bound to the PF/VF. */ 130 uint64_t q_bound_bit_map; 131 /** Bitmap capturing which Queues have already been assigned. */ 132 uint64_t q_assigned_bit_map; 133 /** True if this is a PF FPGA 5GNR device. */ 134 bool pf_device; 135 /** Maximum number of possible queues for this device. */ 136 uint8_t total_num_queues; 137 /** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1. */ 138 uint8_t fpga_variant; 139 }; 140 141 /** Structure associated with each queue. */ 142 struct __rte_cache_aligned fpga_5gnr_queue { 143 struct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg; /**< Ring Control Register */ 144 union { 145 /** Virtual address of VC 5GNR software ring. */ 146 union vc_5gnr_dma_desc *vc_5gnr_ring_addr; 147 /** Virtual address of AGX100 software ring. */ 148 union agx100_dma_desc *agx100_ring_addr; 149 }; 150 uint64_t *ring_head_addr; /* Virtual address of completion_head */ 151 uint64_t shadow_completion_head; /* Shadow completion head value */ 152 uint16_t head_free_desc; /* Ring head */ 153 uint16_t tail; /* Ring tail */ 154 /* Mask used to wrap enqueued descriptors on the sw ring */ 155 uint32_t sw_ring_wrap_mask; 156 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ 157 uint8_t q_idx; /* Queue index */ 158 /** uuid used for MUTEX acquision for DDR */ 159 uint16_t ddr_mutex_uuid; 160 struct fpga_5gnr_fec_device *d; 161 /* MMIO register of shadow_tail used to enqueue descriptors */ 162 void *shadow_tail_addr; 163 }; 164 165 /* Write to 16 bit MMIO register address. */ 166 static inline void 167 mmio_write_16(void *addr, uint16_t value) 168 { 169 *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value); 170 } 171 172 /* Write to 32 bit MMIO register address. */ 173 static inline void 174 mmio_write_32(void *addr, uint32_t value) 175 { 176 *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value); 177 } 178 179 /* Write to 64 bit MMIO register address. */ 180 static inline void 181 mmio_write_64(void *addr, uint64_t value) 182 { 183 *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value); 184 } 185 186 /* Write a 8 bit register of a FPGA 5GNR device. */ 187 static inline void 188 fpga_5gnr_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload) 189 { 190 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 191 *((volatile uint8_t *)(reg_addr)) = payload; 192 } 193 194 /* Write a 16 bit register of a FPGA 5GNR device. */ 195 static inline void 196 fpga_5gnr_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload) 197 { 198 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 199 mmio_write_16(reg_addr, payload); 200 } 201 202 /* Write a 32 bit register of a FPGA 5GNR device. */ 203 static inline void 204 fpga_5gnr_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload) 205 { 206 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 207 mmio_write_32(reg_addr, payload); 208 } 209 210 /* Write a 64 bit register of a FPGA 5GNR device. */ 211 static inline void 212 fpga_5gnr_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload) 213 { 214 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 215 mmio_write_64(reg_addr, payload); 216 } 217 218 /* Write a ring control register of a FPGA 5GNR device. */ 219 static inline void 220 fpga_ring_reg_write(void *mmio_base, uint32_t offset, struct fpga_5gnr_ring_ctrl_reg payload) 221 { 222 fpga_5gnr_reg_write_64(mmio_base, offset, payload.ring_base_addr); 223 fpga_5gnr_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR, 224 payload.ring_head_addr); 225 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE, payload.ring_size); 226 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, 227 payload.head_point); 228 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, 229 payload.flush_queue_en); 230 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, 231 payload.shadow_tail); 232 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC, payload.misc); 233 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload.enable); 234 } 235 236 /* Read a register of FPGA 5GNR device. */ 237 static inline uint32_t 238 fpga_5gnr_reg_read_32(void *mmio_base, uint32_t offset) 239 { 240 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 241 uint32_t ret = *((volatile uint32_t *)(reg_addr)); 242 return rte_le_to_cpu_32(ret); 243 } 244 245 #ifdef RTE_LIBRTE_BBDEV_DEBUG 246 247 /* Read a register of FPGA 5GNR device. */ 248 static inline uint16_t 249 fpga_5gnr_reg_read_16(void *mmio_base, uint32_t offset) 250 { 251 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 252 uint16_t ret = *((volatile uint16_t *)(reg_addr)); 253 return rte_le_to_cpu_16(ret); 254 } 255 256 #endif 257 258 /* Read a register of FPGA 5GNR device. */ 259 static inline uint8_t 260 fpga_5gnr_reg_read_8(void *mmio_base, uint32_t offset) 261 { 262 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 263 return *((volatile uint8_t *)(reg_addr)); 264 } 265 266 /* Read a register of FPGA 5GNR device. */ 267 static inline uint64_t 268 fpga_5gnr_reg_read_64(void *mmio_base, uint32_t offset) 269 { 270 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 271 uint64_t ret = *((volatile uint64_t *)(reg_addr)); 272 return rte_le_to_cpu_64(ret); 273 } 274 275 #endif /* _FPGA_5GNR_FEC_H_ */ 276