1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #ifndef _FPGA_5GNR_FEC_H_ 6 #define _FPGA_5GNR_FEC_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include "agx100_pmd.h" 12 #include "vc_5gnr_pmd.h" 13 14 extern int fpga_5gnr_fec_logtype; 15 #define RTE_LOGTYPE_FPGA_5GNR_FEC fpga_5gnr_fec_logtype 16 17 /* Helper macro for logging */ 18 #define rte_bbdev_log(level, ...) \ 19 RTE_LOG_LINE(level, FPGA_5GNR_FEC, __VA_ARGS__) 20 21 #ifdef RTE_LIBRTE_BBDEV_DEBUG 22 #define rte_bbdev_log_debug(...) \ 23 rte_bbdev_log(DEBUG, __VA_ARGS__) 24 #else 25 #define rte_bbdev_log_debug(...) 26 #endif 27 28 /* FPGA 5GNR FEC driver names */ 29 #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf 30 #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf 31 32 #define FPGA_5GNR_INVALID_HW_QUEUE_ID (0xFFFFFFFF) 33 #define FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US (1000) 34 #define FPGA_5GNR_HARQ_RDY_TIMEOUT (10) 35 #define FPGA_5GNR_TIMEOUT_CHECK_INTERVAL (5) 36 #define FPGA_5GNR_DDR_OVERFLOW (0x10) 37 #define FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES 8 38 #define FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES 8 39 /* Align DMA descriptors to 256 bytes - cache-aligned. */ 40 #define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8) 41 /* Maximum size of queue. */ 42 #define FPGA_5GNR_RING_MAX_SIZE (1024) 43 44 #define VC_5GNR_FPGA_VARIANT 0 45 #define AGX100_FPGA_VARIANT 1 46 47 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ 48 #define N_ZC_1 66 /* N = 66 Zc for BG 1 */ 49 #define N_ZC_2 50 /* N = 50 Zc for BG 2 */ 50 #define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ 51 #define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ 52 #define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ 53 #define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */ 54 #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ 55 #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ 56 57 /* FPGA 5GNR Ring Control Registers. */ 58 enum { 59 FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008, 60 FPGA_5GNR_FEC_RING_SIZE = 0x00000010, 61 FPGA_5GNR_FEC_RING_MISC = 0x00000014, 62 FPGA_5GNR_FEC_RING_ENABLE = 0x00000015, 63 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016, 64 FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018, 65 FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C 66 }; 67 68 /* VC 5GNR and AGX100 common register mapping on BAR0. */ 69 enum { 70 FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */ 71 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */ 72 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */ 73 FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */ 74 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */ 75 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */ 76 FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */ 77 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */ 78 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */ 79 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */ 80 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */ 81 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */ 82 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */ 83 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */ 84 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */ 85 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */ 86 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */ 87 FPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */ 88 FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /**< len: 4B. */ 89 }; 90 91 /* FPGA 5GNR Ring Control Register. */ 92 struct __rte_packed_begin fpga_5gnr_ring_ctrl_reg { 93 uint64_t ring_base_addr; 94 uint64_t ring_head_addr; 95 uint16_t ring_size:11; 96 uint16_t rsrvd0; 97 union { /* Miscellaneous register */ 98 uint8_t misc; 99 uint8_t max_ul_dec:5, 100 max_ul_dec_en:1, 101 rsrvd1:2; 102 }; 103 uint8_t enable; 104 uint8_t flush_queue_en; 105 uint8_t rsrvd2; 106 uint16_t shadow_tail; 107 uint16_t rsrvd3; 108 uint16_t head_point; 109 uint16_t rsrvd4; 110 } __rte_packed_end; 111 112 /* Private data structure for each FPGA 5GNR device. */ 113 struct fpga_5gnr_fec_device { 114 /** Base address of MMIO registers (BAR0). */ 115 void *mmio_base; 116 /** Base address of memory for sw rings. */ 117 void *sw_rings; 118 /** Physical address of sw_rings. */ 119 rte_iova_t sw_rings_phys; 120 /** Number of bytes available for each queue in device. */ 121 uint32_t sw_ring_size; 122 /** Max number of entries available for each queue in device. */ 123 uint32_t sw_ring_max_depth; 124 /** Base address of response tail pointer buffer. */ 125 uint32_t *tail_ptrs; 126 /** Physical address of tail pointers. */ 127 rte_iova_t tail_ptr_phys; 128 /** Queues flush completion flag. */ 129 uint64_t *flush_queue_status; 130 /** Bitmap capturing which Queues are bound to the PF/VF. */ 131 uint64_t q_bound_bit_map; 132 /** Bitmap capturing which Queues have already been assigned. */ 133 uint64_t q_assigned_bit_map; 134 /** True if this is a PF FPGA 5GNR device. */ 135 bool pf_device; 136 /** Maximum number of possible queues for this device. */ 137 uint8_t total_num_queues; 138 /** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1. */ 139 uint8_t fpga_variant; 140 }; 141 142 /** Structure associated with each queue. */ 143 struct __rte_cache_aligned fpga_5gnr_queue { 144 struct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg; /**< Ring Control Register */ 145 union { 146 /** Virtual address of VC 5GNR software ring. */ 147 union vc_5gnr_dma_desc *vc_5gnr_ring_addr; 148 /** Virtual address of AGX100 software ring. */ 149 union agx100_dma_desc *agx100_ring_addr; 150 }; 151 uint64_t *ring_head_addr; /* Virtual address of completion_head */ 152 uint64_t shadow_completion_head; /* Shadow completion head value */ 153 uint16_t head_free_desc; /* Ring head */ 154 uint16_t tail; /* Ring tail */ 155 /* Mask used to wrap enqueued descriptors on the sw ring */ 156 uint32_t sw_ring_wrap_mask; 157 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ 158 uint8_t q_idx; /* Queue index */ 159 /** uuid used for MUTEX acquision for DDR */ 160 uint16_t ddr_mutex_uuid; 161 struct fpga_5gnr_fec_device *d; 162 /* MMIO register of shadow_tail used to enqueue descriptors */ 163 void *shadow_tail_addr; 164 }; 165 166 /* Write to 16 bit MMIO register address. */ 167 static inline void 168 mmio_write_16(void *addr, uint16_t value) 169 { 170 *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value); 171 } 172 173 /* Write to 32 bit MMIO register address. */ 174 static inline void 175 mmio_write_32(void *addr, uint32_t value) 176 { 177 *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value); 178 } 179 180 /* Write to 64 bit MMIO register address. */ 181 static inline void 182 mmio_write_64(void *addr, uint64_t value) 183 { 184 *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value); 185 } 186 187 /* Write a 8 bit register of a FPGA 5GNR device. */ 188 static inline void 189 fpga_5gnr_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload) 190 { 191 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 192 *((volatile uint8_t *)(reg_addr)) = payload; 193 } 194 195 /* Write a 16 bit register of a FPGA 5GNR device. */ 196 static inline void 197 fpga_5gnr_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload) 198 { 199 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 200 mmio_write_16(reg_addr, payload); 201 } 202 203 /* Write a 32 bit register of a FPGA 5GNR device. */ 204 static inline void 205 fpga_5gnr_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload) 206 { 207 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 208 mmio_write_32(reg_addr, payload); 209 } 210 211 /* Write a 64 bit register of a FPGA 5GNR device. */ 212 static inline void 213 fpga_5gnr_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload) 214 { 215 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 216 mmio_write_64(reg_addr, payload); 217 } 218 219 /* Write a ring control register of a FPGA 5GNR device. */ 220 static inline void 221 fpga_ring_reg_write(void *mmio_base, uint32_t offset, struct fpga_5gnr_ring_ctrl_reg payload) 222 { 223 fpga_5gnr_reg_write_64(mmio_base, offset, payload.ring_base_addr); 224 fpga_5gnr_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR, 225 payload.ring_head_addr); 226 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE, payload.ring_size); 227 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, 228 payload.head_point); 229 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, 230 payload.flush_queue_en); 231 fpga_5gnr_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, 232 payload.shadow_tail); 233 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC, payload.misc); 234 fpga_5gnr_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload.enable); 235 } 236 237 /* Read a register of FPGA 5GNR device. */ 238 static inline uint32_t 239 fpga_5gnr_reg_read_32(void *mmio_base, uint32_t offset) 240 { 241 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 242 uint32_t ret = *((volatile uint32_t *)(reg_addr)); 243 return rte_le_to_cpu_32(ret); 244 } 245 246 #ifdef RTE_LIBRTE_BBDEV_DEBUG 247 248 /* Read a register of FPGA 5GNR device. */ 249 static inline uint16_t 250 fpga_5gnr_reg_read_16(void *mmio_base, uint32_t offset) 251 { 252 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 253 uint16_t ret = *((volatile uint16_t *)(reg_addr)); 254 return rte_le_to_cpu_16(ret); 255 } 256 257 #endif 258 259 /* Read a register of FPGA 5GNR device. */ 260 static inline uint8_t 261 fpga_5gnr_reg_read_8(void *mmio_base, uint32_t offset) 262 { 263 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 264 return *((volatile uint8_t *)(reg_addr)); 265 } 266 267 /* Read a register of FPGA 5GNR device. */ 268 static inline uint64_t 269 fpga_5gnr_reg_read_64(void *mmio_base, uint32_t offset) 270 { 271 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 272 uint64_t ret = *((volatile uint64_t *)(reg_addr)); 273 return rte_le_to_cpu_64(ret); 274 } 275 276 #endif /* _FPGA_5GNR_FEC_H_ */ 277