1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #ifndef _FPGA_5GNR_FEC_H_ 6 #define _FPGA_5GNR_FEC_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 /* Helper macro for logging */ 12 #define rte_bbdev_log(level, fmt, ...) \ 13 rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \ 14 ##__VA_ARGS__) 15 16 #ifdef RTE_LIBRTE_BBDEV_DEBUG 17 #define rte_bbdev_log_debug(fmt, ...) \ 18 rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \ 19 ##__VA_ARGS__) 20 #else 21 #define rte_bbdev_log_debug(fmt, ...) 22 #endif 23 24 /* FPGA 5GNR FEC driver names */ 25 #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf 26 #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf 27 28 /* FPGA 5GNR FEC PCI vendor & device IDs */ 29 #define FPGA_5GNR_FEC_VENDOR_ID (0x8086) 30 #define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F) 31 #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90) 32 33 /* Align DMA descriptors to 256 bytes - cache-aligned */ 34 #define FPGA_RING_DESC_ENTRY_LENGTH (8) 35 /* Ring size is in 256 bits (32 bytes) units */ 36 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32) 37 /* Maximum size of queue */ 38 #define FPGA_RING_MAX_SIZE (1024) 39 40 #define FPGA_NUM_UL_QUEUES (32) 41 #define FPGA_NUM_DL_QUEUES (32) 42 #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES) 43 #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET) 44 45 #define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF) 46 47 #define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000) 48 #define FPGA_HARQ_RDY_TIMEOUT (10) 49 #define FPGA_TIMEOUT_CHECK_INTERVAL (5) 50 #define FPGA_DDR_OVERFLOW (0x10) 51 52 #define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8 53 #define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8 54 55 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ 56 #define N_ZC_1 66 /* N = 66 Zc for BG 1 */ 57 #define N_ZC_2 50 /* N = 50 Zc for BG 2 */ 58 #define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ 59 #define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ 60 #define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ 61 #define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */ 62 #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ 63 #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ 64 65 /* FPGA 5GNR FEC Register mapping on BAR0 */ 66 enum { 67 FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */ 68 FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */ 69 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ 70 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ 71 FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ 72 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ 73 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ 74 FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ 75 FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */ 76 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */ 77 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */ 78 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */ 79 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */ 80 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */ 81 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */ 82 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */ 83 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */ 84 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */ 85 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /* len: 4B */ 86 FPGA_5GNR_FEC_MUTEX = 0x00000A60, /* len: 4B */ 87 FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /* len: 4B */ 88 }; 89 90 /* FPGA 5GNR FEC Ring Control Registers */ 91 enum { 92 FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008, 93 FPGA_5GNR_FEC_RING_SIZE = 0x00000010, 94 FPGA_5GNR_FEC_RING_MISC = 0x00000014, 95 FPGA_5GNR_FEC_RING_ENABLE = 0x00000015, 96 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016, 97 FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018, 98 FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C 99 }; 100 101 /* FPGA 5GNR FEC DESCRIPTOR ERROR */ 102 enum { 103 DESC_ERR_NO_ERR = 0x0, 104 DESC_ERR_K_P_OUT_OF_RANGE = 0x1, 105 DESC_ERR_Z_C_NOT_LEGAL = 0x2, 106 DESC_ERR_DESC_OFFSET_ERR = 0x3, 107 DESC_ERR_DESC_READ_FAIL = 0x8, 108 DESC_ERR_DESC_READ_TIMEOUT = 0x9, 109 DESC_ERR_DESC_READ_TLP_POISONED = 0xA, 110 DESC_ERR_HARQ_INPUT_LEN = 0xB, 111 DESC_ERR_CB_READ_FAIL = 0xC, 112 DESC_ERR_CB_READ_TIMEOUT = 0xD, 113 DESC_ERR_CB_READ_TLP_POISONED = 0xE, 114 DESC_ERR_HBSTORE_ERR = 0xF 115 }; 116 117 118 /* FPGA 5GNR FEC DMA Encoding Request Descriptor */ 119 struct __rte_packed fpga_dma_enc_desc { 120 uint32_t done:1, 121 rsrvd0:7, 122 error:4, 123 rsrvd1:4, 124 num_null:10, 125 rsrvd2:6; 126 uint32_t ncb:15, 127 rsrvd3:1, 128 k0:16; 129 uint32_t irq_en:1, 130 crc_en:1, 131 rsrvd4:1, 132 qm_idx:3, 133 bg_idx:1, 134 zc:9, 135 desc_idx:10, 136 rsrvd5:6; 137 uint16_t rm_e; 138 uint16_t k_; 139 uint32_t out_addr_lw; 140 uint32_t out_addr_hi; 141 uint32_t in_addr_lw; 142 uint32_t in_addr_hi; 143 144 union { 145 struct { 146 /* Virtual addresses used to retrieve SW context info */ 147 void *op_addr; 148 /* Stores information about total number of Code Blocks 149 * in currently processed Transport Block 150 */ 151 uint64_t cbs_in_op; 152 }; 153 154 uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES * 155 (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; 156 }; 157 }; 158 159 160 /* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */ 161 struct __rte_packed fpga_dma_dec_desc { 162 uint32_t done:1, 163 iter:5, 164 et_pass:1, 165 crcb_pass:1, 166 error:4, 167 qm_idx:3, 168 max_iter:5, 169 bg_idx:1, 170 rsrvd0:1, 171 harqin_en:1, 172 zc:9; 173 uint32_t hbstroe_offset:22, 174 num_null:10; 175 uint32_t irq_en:1, 176 ncb:15, 177 desc_idx:10, 178 drop_crc24b:1, 179 crc24b_ind:1, 180 rv:2, 181 et_dis:1, 182 rsrvd2:1; 183 uint32_t harq_input_length:16, 184 rm_e:16;/*the inbound data byte length*/ 185 uint32_t out_addr_lw; 186 uint32_t out_addr_hi; 187 uint32_t in_addr_lw; 188 uint32_t in_addr_hi; 189 190 union { 191 struct { 192 /* Virtual addresses used to retrieve SW context info */ 193 void *op_addr; 194 /* Stores information about total number of Code Blocks 195 * in currently processed Transport Block 196 */ 197 uint8_t cbs_in_op; 198 }; 199 200 uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; 201 }; 202 }; 203 204 /* FPGA 5GNR DMA Descriptor */ 205 union fpga_dma_desc { 206 struct fpga_dma_enc_desc enc_req; 207 struct fpga_dma_dec_desc dec_req; 208 }; 209 210 /* FPGA 5GNR FEC Ring Control Register */ 211 struct __rte_packed fpga_ring_ctrl_reg { 212 uint64_t ring_base_addr; 213 uint64_t ring_head_addr; 214 uint16_t ring_size:11; 215 uint16_t rsrvd0; 216 union { /* Miscellaneous register */ 217 uint8_t misc; 218 uint8_t max_ul_dec:5, 219 max_ul_dec_en:1, 220 rsrvd1:2; 221 }; 222 uint8_t enable; 223 uint8_t flush_queue_en; 224 uint8_t rsrvd2; 225 uint16_t shadow_tail; 226 uint16_t rsrvd3; 227 uint16_t head_point; 228 uint16_t rsrvd4; 229 230 }; 231 232 /* Private data structure for each FPGA FEC device */ 233 struct fpga_5gnr_fec_device { 234 /** Base address of MMIO registers (BAR0) */ 235 void *mmio_base; 236 /** Base address of memory for sw rings */ 237 void *sw_rings; 238 /** Physical address of sw_rings */ 239 rte_iova_t sw_rings_phys; 240 /** Number of bytes available for each queue in device. */ 241 uint32_t sw_ring_size; 242 /** Max number of entries available for each queue in device */ 243 uint32_t sw_ring_max_depth; 244 /** Base address of response tail pointer buffer */ 245 uint32_t *tail_ptrs; 246 /** Physical address of tail pointers */ 247 rte_iova_t tail_ptr_phys; 248 /** Queues flush completion flag */ 249 uint64_t *flush_queue_status; 250 /* Bitmap capturing which Queues are bound to the PF/VF */ 251 uint64_t q_bound_bit_map; 252 /* Bitmap capturing which Queues have already been assigned */ 253 uint64_t q_assigned_bit_map; 254 /** True if this is a PF FPGA FEC device */ 255 bool pf_device; 256 }; 257 258 /* Structure associated with each queue. */ 259 struct __rte_cache_aligned fpga_queue { 260 struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */ 261 union fpga_dma_desc *ring_addr; /* Virtual address of software ring */ 262 uint64_t *ring_head_addr; /* Virtual address of completion_head */ 263 uint64_t shadow_completion_head; /* Shadow completion head value */ 264 uint16_t head_free_desc; /* Ring head */ 265 uint16_t tail; /* Ring tail */ 266 /* Mask used to wrap enqueued descriptors on the sw ring */ 267 uint32_t sw_ring_wrap_mask; 268 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ 269 uint8_t q_idx; /* Queue index */ 270 /** uuid used for MUTEX acquision for DDR */ 271 uint16_t ddr_mutex_uuid; 272 struct fpga_5gnr_fec_device *d; 273 /* MMIO register of shadow_tail used to enqueue descriptors */ 274 void *shadow_tail_addr; 275 }; 276 277 /* Write to 16 bit MMIO register address */ 278 static inline void 279 mmio_write_16(void *addr, uint16_t value) 280 { 281 *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value); 282 } 283 284 /* Write to 32 bit MMIO register address */ 285 static inline void 286 mmio_write_32(void *addr, uint32_t value) 287 { 288 *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value); 289 } 290 291 /* Write to 64 bit MMIO register address */ 292 static inline void 293 mmio_write_64(void *addr, uint64_t value) 294 { 295 *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value); 296 } 297 298 /* Write a 8 bit register of a FPGA 5GNR FEC device */ 299 static inline void 300 fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload) 301 { 302 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 303 *((volatile uint8_t *)(reg_addr)) = payload; 304 } 305 306 /* Write a 16 bit register of a FPGA 5GNR FEC device */ 307 static inline void 308 fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload) 309 { 310 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 311 mmio_write_16(reg_addr, payload); 312 } 313 314 /* Write a 32 bit register of a FPGA 5GNR FEC device */ 315 static inline void 316 fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload) 317 { 318 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 319 mmio_write_32(reg_addr, payload); 320 } 321 322 /* Write a 64 bit register of a FPGA 5GNR FEC device */ 323 static inline void 324 fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload) 325 { 326 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 327 mmio_write_64(reg_addr, payload); 328 } 329 330 /* Write a ring control register of a FPGA 5GNR FEC device */ 331 static inline void 332 fpga_ring_reg_write(void *mmio_base, uint32_t offset, 333 struct fpga_ring_ctrl_reg payload) 334 { 335 fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr); 336 fpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR, 337 payload.ring_head_addr); 338 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE, 339 payload.ring_size); 340 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, 341 payload.head_point); 342 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, 343 payload.flush_queue_en); 344 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, 345 payload.shadow_tail); 346 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC, 347 payload.misc); 348 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, 349 payload.enable); 350 } 351 352 /* Read a register of FPGA 5GNR FEC device */ 353 static inline uint32_t 354 fpga_reg_read_32(void *mmio_base, uint32_t offset) 355 { 356 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 357 uint32_t ret = *((volatile uint32_t *)(reg_addr)); 358 return rte_le_to_cpu_32(ret); 359 } 360 361 #ifdef RTE_LIBRTE_BBDEV_DEBUG 362 363 /* Read a register of FPGA 5GNR FEC device */ 364 static inline uint16_t 365 fpga_reg_read_16(void *mmio_base, uint32_t offset) 366 { 367 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 368 uint16_t ret = *((volatile uint16_t *)(reg_addr)); 369 return rte_le_to_cpu_16(ret); 370 } 371 372 #endif 373 374 /* Read a register of FPGA 5GNR FEC device */ 375 static inline uint8_t 376 fpga_reg_read_8(void *mmio_base, uint32_t offset) 377 { 378 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 379 return *((volatile uint8_t *)(reg_addr)); 380 } 381 382 /* Read a register of FPGA 5GNR FEC device */ 383 static inline uint64_t 384 fpga_reg_read_64(void *mmio_base, uint32_t offset) 385 { 386 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); 387 uint64_t ret = *((volatile uint64_t *)(reg_addr)); 388 return rte_le_to_cpu_64(ret); 389 } 390 391 #endif /* _FPGA_5GNR_FEC_H_ */ 392