1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2022 Intel Corporation 3 */ 4 5 #ifndef _AGX100_H_ 6 #define _AGX100_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 /* AGX100 PCI vendor & device IDs. */ 12 #define AGX100_VENDOR_ID (0x8086) 13 #define AGX100_PF_DEVICE_ID (0x5799) 14 #define AGX100_VF_DEVICE_ID (0x579A) 15 16 /* Maximum number of possible queues supported on device. */ 17 #define AGX100_MAXIMUM_QUEUES_SUPPORTED (64) 18 19 /* AGX100 Ring size is in 256 bits (64 bytes) units. */ 20 #define AGX100_RING_DESC_LEN_UNIT_BYTES (64) 21 22 /* Align DMA descriptors to 256 bytes - cache-aligned. */ 23 #define AGX100_RING_DESC_ENTRY_LENGTH (8) 24 25 /* AGX100 Register mapping on BAR0. */ 26 enum { 27 AGX100_FLR_TIME_OUT = 0x0000000E, /* len: 2B. */ 28 AGX100_QUEUE_MAP = 0x00000100 /* len: 256B. */ 29 }; 30 31 /* AGX100 DESCRIPTOR ERROR. */ 32 enum { 33 AGX100_DESC_ERR_NO_ERR = 0x00, /**< 4'b0000 2'b00. */ 34 AGX100_DESC_ERR_E_NOT_LEGAL = 0x11, /**< 4'b0001 2'b01. */ 35 AGX100_DESC_ERR_K_P_OUT_OF_RANGE = 0x21, /**< 4'b0010 2'b01. */ 36 AGX100_DESC_ERR_NCB_OUT_OF_RANGE = 0x31, /**< 4'b0011 2'b01. */ 37 AGX100_DESC_ERR_Z_C_NOT_LEGAL = 0x41, /**< 4'b0100 2'b01. */ 38 AGX100_DESC_ERR_DESC_INDEX_ERR = 0x03, /**< 4'b0000 2'b11. */ 39 AGX100_DESC_ERR_HARQ_INPUT_LEN_A = 0x51, /**< 4'b0101 2'b01. */ 40 AGX100_DESC_ERR_HARQ_INPUT_LEN_B = 0x61, /**< 4'b0110 2'b01. */ 41 AGX100_DESC_ERR_HBSTORE_OFFSET_ERR = 0x71, /**< 4'b0111 2'b01. */ 42 AGX100_DESC_ERR_TB_CBG_ERR = 0x81, /**< 4'b1000 2'b01. */ 43 AGX100_DESC_ERR_CBG_OUT_OF_RANGE = 0x91, /**< 4'b1001 2'b01. */ 44 AGX100_DESC_ERR_CW_RM_NOT_LEGAL = 0xA1, /**< 4'b1010 2'b01. */ 45 AGX100_DESC_ERR_UNSUPPORTED_REQ = 0x12, /**< 4'b0000 2'b10. */ 46 AGX100_DESC_ERR_RESERVED = 0x22, /**< 4'b0010 2'b10. */ 47 AGX100_DESC_ERR_DESC_ABORT = 0x42, /**< 4'b0100 2'b10. */ 48 AGX100_DESC_ERR_DESC_READ_TLP_POISONED = 0x82 /**< 4'b1000 2'b10. */ 49 }; 50 51 /* AGX100 TX Slice Descriptor. */ 52 struct __rte_packed_begin agx100_input_slice_desc { 53 uint32_t input_start_addr_lo; 54 uint32_t input_start_addr_hi; 55 uint32_t input_slice_length:21, 56 rsrvd0:9, 57 end_of_pkt:1, 58 start_of_pkt:1; 59 uint32_t input_slice_time_stamp:31, 60 input_c:1; 61 } __rte_packed_end; 62 63 /* AGX100 RX Slice Descriptor. */ 64 struct __rte_packed_begin agx100_output_slice_desc { 65 uint32_t output_start_addr_lo; 66 uint32_t output_start_addr_hi; 67 uint32_t output_slice_length:21, 68 rsrvd0:9, 69 end_of_pkt:1, 70 start_of_pkt:1; 71 uint32_t output_slice_time_stamp:31, 72 output_c:1; 73 } __rte_packed_end; 74 75 /* AGX100 DL DMA Encoding Request Descriptor. */ 76 struct __rte_packed_begin agx100_dma_enc_desc { 77 uint32_t done:1, /**< 0: not completed 1: completed. */ 78 rsrvd0:17, 79 error_msg:2, 80 error_code:4, 81 rsrvd1:8; 82 uint32_t ncb:16, /**< Limited circular buffer size. */ 83 bg_idx:1, /**< Base Graph 0: BG1 1: BG2.*/ 84 qm_idx:3, /**< 0: BPSK; 1: QPSK; 2: 16QAM; 3: 64QAM; 4: 256QAM. */ 85 zc:9, /**< Lifting size. */ 86 rv:2, /**< Redundancy version number. */ 87 int_en:1; /**< Interrupt enable. */ 88 uint32_t max_cbg:4, /**< Only valid when workload is TB or CBGs. */ 89 rsrvd2:4, 90 cbgti:8, /**< CBG bitmap. */ 91 rsrvd3:4, 92 cbgs:1, /**< 0: TB or CB 1: CBGs. */ 93 desc_idx:11; /**< Sequence number of the descriptor. */ 94 uint32_t ca:10, /**< Code block number with Ea in TB or CBG. */ 95 c:10, /**< Total code block number in TB or CBG. */ 96 rsrvd4:2, 97 num_null:10; /**< Number of null bits. */ 98 uint32_t ea:21, /**< Value of E when workload is CB. */ 99 rsrvd5:11; 100 uint32_t eb:21, /**< Only valid when workload is TB or CBGs. */ 101 rsrvd6:11; 102 uint32_t k_:16, /**< Code block length without null bits. */ 103 rsrvd7:8, 104 en_slice_ts:1, /**< Enable slice descriptor timestamp. */ 105 en_host_ts:1, /**< Enable host descriptor timestamp. */ 106 en_cb_wr_status:1, /**< Enable code block write back status. */ 107 en_output_sg:1, /**< Enable RX scatter-gather. */ 108 en_input_sg:1, /**< Enable TX scatter-gather. */ 109 tb_cb:1, /**< 2'b10: the descriptor is for a TrBlk. 110 * 2'b00: the descriptor is for a CBlk. 111 * 2'b11 or 01: the descriptor is for a CBGs. 112 */ 113 crc_en:1, /**< 1: CB CRC enabled 0: CB CRC disabled. 114 * Only valid when workload is CB or CBGs. 115 */ 116 rsrvd8:1; 117 uint32_t rsrvd9; 118 union { 119 uint32_t input_slice_table_addr_lo; /**<Used when scatter-gather enabled.*/ 120 uint32_t input_start_addr_lo; /**< Used when scatter-gather disabled. */ 121 }; 122 union { 123 uint32_t input_slice_table_addr_hi; /**<Used when scatter-gather enabled.*/ 124 uint32_t input_start_addr_hi; /**< Used when scatter-gather disabled. */ 125 }; 126 union { 127 uint32_t input_slice_num:21, /**< Used when scatter-gather enabled. */ 128 rsrvd10:11; 129 uint32_t input_length:26, /**< Used when scatter-gather disabled. */ 130 rsrvd11:6; 131 }; 132 union { 133 uint32_t output_slice_table_addr_lo; /**< Used when scatter-gather enabled.*/ 134 uint32_t output_start_addr_lo; /**< Used when scatter-gather disabled. */ 135 }; 136 union { 137 uint32_t output_slice_table_addr_hi; /**< Used when scatter-gather enabled.*/ 138 uint32_t output_start_addr_hi; /**< Used when scatter-gather disabled. */ 139 }; 140 union { 141 uint32_t output_slice_num:21, /**< Used when scatter-gather enabled. */ 142 rsrvd12:11; 143 uint32_t output_length:26, /**< Used when scatter-gather disabled. */ 144 rsrvd13:6; 145 }; 146 uint32_t enqueue_timestamp:31, /**< Time when AGX100 receives descriptor. */ 147 rsrvd14:1; 148 uint32_t completion_timestamp:31, /**< Time when AGX100 completes descriptor. */ 149 rsrvd15:1; 150 151 union { 152 struct { 153 /** Virtual addresses used to retrieve SW context info. */ 154 void *op_addr; 155 /** Stores information about total number of Code Blocks 156 * in currently processed Transport Block 157 */ 158 uint64_t cbs_in_op; 159 }; 160 161 uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES * 162 (AGX100_RING_DESC_ENTRY_LENGTH - 1)]; 163 }; 164 } __rte_packed_end; 165 166 /* AGX100 UL DMA Decoding Request Descriptor. */ 167 struct __rte_packed_begin agx100_dma_dec_desc { 168 uint32_t done:1, /**< 0: not completed 1: completed. */ 169 tb_crc_pass:1, /**< 0: doesn't pass 1: pass. */ 170 cb_crc_all_pass:1, /**< 0: doesn't pass 1: pass. */ 171 cb_all_et_pass:1, /**< 0: not all decoded 1: all decoded. */ 172 max_iter_ret:6, /**< Iteration number returned by LDPC decoder. */ 173 cgb_crc_bitmap:8, /**< Field valid only when workload is TB or CBGs. */ 174 error_msg:2, 175 error_code:4, 176 et_dis:1, /**< Disable the early termination feature of LDPC decoder. */ 177 harq_in_en:1, /**< 0: combine disabled 1: combine enable.*/ 178 max_iter:6; /**< Maximum value of iteration for decoding CB. */ 179 uint32_t ncb:16, /**< Limited circular buffer size. */ 180 bg_idx:1, /**< Base Graph 0: BG1 1: BG2.*/ 181 qm_idx:3, /**< 0: BPSK; 1: QPSK; 2: 16QAM; 3: 64QAM; 4: 256QAM. */ 182 zc:9, /**< Lifting size. */ 183 rv:2, /**< Redundancy version number. */ 184 int_en:1; /**< Interrupt enable. */ 185 uint32_t max_cbg:4, /**< Only valid when workload is TB or CBGs. */ 186 rsrvd0:4, 187 cbgti:8, /**< CBG bitmap. */ 188 cbgfi:1, /**< 0: overwrite HARQ buffer 1: enable HARQ for CBGs. */ 189 rsrvd1:3, 190 cbgs:1, /**< 0: TB or CB 1: CBGs. */ 191 desc_idx:11; /**< Sequence number of the descriptor. */ 192 uint32_t ca:10, /**< Code block number with Ea in TB or CBG. */ 193 c:10, /**< Total code block number in TB or CBG. */ 194 llr_pckg:1, /**< 0: 8-bit LLR 1: 6-bit LLR packed together. */ 195 syndrome_check_mode:1, /**<0: full syndrome check 1: 4-layer syndome check.*/ 196 num_null:10; /**< Number of null bits. */ 197 uint32_t ea:21, /**< Value of E when workload is CB. */ 198 rsrvd2:3, 199 eba:8; /**< Only valid when workload is TB or CBGs. */ 200 uint32_t hbstore_offset_out:24, /**< HARQ buffer write address. */ 201 rsrvd3:8; 202 uint32_t hbstore_offset_in:24, /**< HARQ buffer read address. */ 203 en_slice_ts:1, /**< Enable slice descriptor timestamp. */ 204 en_host_ts:1, /**< Enable host descriptor timestamp. */ 205 en_cb_wr_status:1, /**< Enable code block write back status. */ 206 en_output_sg:1, /**< Enable RX scatter-gather. */ 207 en_input_sg:1, /**< Enable TX scatter-gather. */ 208 tb_cb:1, /**< 2'b10: the descriptor is for a TrBlk. 209 * 2'b00: the descriptor is for a CBlk. 210 * 2'b11 or 01: the descriptor is for a CBGs. 211 */ 212 crc24b_ind:1, /**< 1: CB includes CRC, need LDPC-V to check the CB CRC. 213 * 0: There is no CB CRC check. 214 * Only valid when workload is CB or CBGs. 215 */ 216 drop_crc24b:1; /**< 1: CB CRC will be dropped. */ 217 uint32_t harq_input_length_a: 16, /**< HARQ_input_length for CB. */ 218 harq_input_length_b:16; /**< Only valid when workload is TB or CBGs. */ 219 union { 220 uint32_t input_slice_table_addr_lo; /**< Used when scatter-gather enabled.*/ 221 uint32_t input_start_addr_lo; /**< Used when scatter-gather disabled. */ 222 }; 223 union { 224 uint32_t input_slice_table_addr_hi; /**< Used when scatter-gather enabled.*/ 225 uint32_t input_start_addr_hi; /**< Used when scatter-gather disabled. */ 226 }; 227 union { 228 uint32_t input_slice_num:21, /**< Used when scatter-gather enabled. */ 229 rsrvd4:11; 230 uint32_t input_length:26, /**< Used when scatter-gather disabled. */ 231 rsrvd5:6; 232 }; 233 union { 234 uint32_t output_slice_table_addr_lo; /**< Used when scatter-gather enabled.*/ 235 uint32_t output_start_addr_lo; /**< Used when scatter-gather disabled. */ 236 }; 237 union { 238 uint32_t output_slice_table_addr_hi; /**< Used when scatter-gather enabled.*/ 239 uint32_t output_start_addr_hi; /**< Used when scatter-gather disabled. */ 240 }; 241 union { 242 uint32_t output_slice_num:21, /**< Used when scatter-gather enabled. */ 243 rsrvd6:11; 244 uint32_t output_length:26, /**< Used when scatter-gather disabled. */ 245 rsrvd7:6; 246 }; 247 uint32_t enqueue_timestamp:31, /**< Time when AGX100 receives descriptor. */ 248 rsrvd8:1; 249 uint32_t completion_timestamp:31, /**< Time when AGX100 completes descriptor. */ 250 rsrvd9:1; 251 252 union { 253 struct { 254 /** Virtual addresses used to retrieve SW context info. */ 255 void *op_addr; 256 /** Stores information about total number of Code Blocks 257 * in currently processed Transport Block 258 */ 259 uint8_t cbs_in_op; 260 }; 261 262 uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES * 263 (AGX100_RING_DESC_ENTRY_LENGTH - 1)]; 264 }; 265 } __rte_packed_end; 266 267 /* AGX100 DMA Descriptor. */ 268 union agx100_dma_desc { 269 struct agx100_dma_enc_desc enc_req; 270 struct agx100_dma_dec_desc dec_req; 271 }; 272 273 #endif /* _AGX100_H_ */ 274