1*c6fe65f0SNicolas Chautru /* SPDX-License-Identifier: BSD-3-Clause 2*c6fe65f0SNicolas Chautru * Copyright(c) 2023 Intel Corporation 3*c6fe65f0SNicolas Chautru */ 4*c6fe65f0SNicolas Chautru 5*c6fe65f0SNicolas Chautru #ifndef VRB2_PF_ENUM_H 6*c6fe65f0SNicolas Chautru #define VRB2_PF_ENUM_H 7*c6fe65f0SNicolas Chautru 8*c6fe65f0SNicolas Chautru /* 9*c6fe65f0SNicolas Chautru * VRB2 Register mapping on PF BAR0 10*c6fe65f0SNicolas Chautru * This is automatically generated from RDL, format may change with new RDL 11*c6fe65f0SNicolas Chautru * Release. 12*c6fe65f0SNicolas Chautru * Variable names are as is 13*c6fe65f0SNicolas Chautru */ 14*c6fe65f0SNicolas Chautru enum { 15*c6fe65f0SNicolas Chautru VRB2_PfQmgrEgressQueuesTemplate = 0x0007FC00, 16*c6fe65f0SNicolas Chautru VRB2_PfQmgrIngressAq = 0x00100000, 17*c6fe65f0SNicolas Chautru VRB2_PfQmgrSoftReset = 0x00A00034, 18*c6fe65f0SNicolas Chautru VRB2_PfQmgrAramAllocEn = 0x00A000a0, 19*c6fe65f0SNicolas Chautru VRB2_PfQmgrAramAllocSetupN0 = 0x00A000b0, 20*c6fe65f0SNicolas Chautru VRB2_PfQmgrAramAllocSetupN1 = 0x00A000b4, 21*c6fe65f0SNicolas Chautru VRB2_PfQmgrAramAllocSetupN2 = 0x00A000b8, 22*c6fe65f0SNicolas Chautru VRB2_PfQmgrAramAllocSetupN3 = 0x00A000bc, 23*c6fe65f0SNicolas Chautru VRB2_PfQmgrDepthLog2Grp = 0x00A00200, 24*c6fe65f0SNicolas Chautru VRB2_PfQmgrTholdGrp = 0x00A00300, 25*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg0Indx = 0x00A00600, 26*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg1Indx = 0x00A00700, 27*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg2Indx = 0x00A00800, 28*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg3Indx = 0x00A00900, 29*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg4Indx = 0x00A00A00, 30*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg5Indx = 0x00A00B00, 31*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg6Indx = 0x00A00C00, 32*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateReg7Indx = 0x00A00D00, 33*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpTmplateEnRegIndx = 0x00A00E00, 34*c6fe65f0SNicolas Chautru VRB2_PfQmgrArbQDepthGrp = 0x00A02F00, 35*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpFunction0 = 0x00A02F80, 36*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpPriority = 0x00A02FC0, 37*c6fe65f0SNicolas Chautru VRB2_PfQmgrVfBaseAddr = 0x00A08000, 38*c6fe65f0SNicolas Chautru VRB2_PfQmgrAqEnableVf = 0x00A10000, 39*c6fe65f0SNicolas Chautru VRB2_PfQmgrRingSizeVf = 0x00A20010, 40*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpDepthLog20Vf = 0x00A20020, 41*c6fe65f0SNicolas Chautru VRB2_PfQmgrGrpDepthLog21Vf = 0x00A20024, 42*c6fe65f0SNicolas Chautru VRB2_PfFabricM2iBufferReg = 0x00B30000, 43*c6fe65f0SNicolas Chautru VRB2_PfFecUl5gIbDebug0Reg = 0x00B401FC, 44*c6fe65f0SNicolas Chautru VRB2_PfFftConfig0 = 0x00B58004, 45*c6fe65f0SNicolas Chautru VRB2_PfFftParityMask8 = 0x00B5803C, 46*c6fe65f0SNicolas Chautru VRB2_PfDmaConfig0Reg = 0x00B80000, 47*c6fe65f0SNicolas Chautru VRB2_PfDmaConfig1Reg = 0x00B80004, 48*c6fe65f0SNicolas Chautru VRB2_PfDmaQmgrAddrReg = 0x00B80008, 49*c6fe65f0SNicolas Chautru VRB2_PfDmaAxcacheReg = 0x00B80010, 50*c6fe65f0SNicolas Chautru VRB2_PfDmaAxiControl = 0x00B8002C, 51*c6fe65f0SNicolas Chautru VRB2_PfDmaQmanen = 0x00B80040, 52*c6fe65f0SNicolas Chautru VRB2_PfDmaQmanenSelect = 0x00B80044, 53*c6fe65f0SNicolas Chautru VRB2_PfDmaCfgRrespBresp = 0x00B80814, 54*c6fe65f0SNicolas Chautru VRB2_PfDmaDescriptorSignature = 0x00B80868, 55*c6fe65f0SNicolas Chautru VRB2_PfDmaErrorDetectionEn = 0x00B80870, 56*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GulDescBaseLoRegVf = 0x00B88020, 57*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GulDescBaseHiRegVf = 0x00B88024, 58*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GulRespPtrLoRegVf = 0x00B88028, 59*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, 60*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, 61*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, 62*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, 63*c6fe65f0SNicolas Chautru VRB2_PfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, 64*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GulDescBaseLoRegVf = 0x00B88060, 65*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GulDescBaseHiRegVf = 0x00B88064, 66*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GulRespPtrLoRegVf = 0x00B88068, 67*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, 68*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, 69*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, 70*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, 71*c6fe65f0SNicolas Chautru VRB2_PfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, 72*c6fe65f0SNicolas Chautru VRB2_PfDmaFftDescBaseLoRegVf = 0x00B880A0, 73*c6fe65f0SNicolas Chautru VRB2_PfDmaFftDescBaseHiRegVf = 0x00B880A4, 74*c6fe65f0SNicolas Chautru VRB2_PfDmaFftRespPtrLoRegVf = 0x00B880A8, 75*c6fe65f0SNicolas Chautru VRB2_PfDmaFftRespPtrHiRegVf = 0x00B880AC, 76*c6fe65f0SNicolas Chautru VRB2_PfDmaMldDescBaseLoRegVf = 0x00B880C0, 77*c6fe65f0SNicolas Chautru VRB2_PfDmaMldDescBaseHiRegVf = 0x00B880C4, 78*c6fe65f0SNicolas Chautru VRB2_PfQosmonAEvalOverflow0 = 0x00B90008, 79*c6fe65f0SNicolas Chautru VRB2_PfPermonACntrlRegVf = 0x00B98000, 80*c6fe65f0SNicolas Chautru VRB2_PfQosmonBEvalOverflow0 = 0x00BA0008, 81*c6fe65f0SNicolas Chautru VRB2_PfPermonBCntrlRegVf = 0x00BA8000, 82*c6fe65f0SNicolas Chautru VRB2_PfPermonCCntrlRegVf = 0x00BB8000, 83*c6fe65f0SNicolas Chautru VRB2_PfHiInfoRingBaseLoRegPf = 0x00C84014, 84*c6fe65f0SNicolas Chautru VRB2_PfHiInfoRingBaseHiRegPf = 0x00C84018, 85*c6fe65f0SNicolas Chautru VRB2_PfHiInfoRingPointerRegPf = 0x00C8401C, 86*c6fe65f0SNicolas Chautru VRB2_PfHiInfoRingIntWrEnRegPf = 0x00C84020, 87*c6fe65f0SNicolas Chautru VRB2_PfHiBlockTransmitOnErrorEn = 0x00C84038, 88*c6fe65f0SNicolas Chautru VRB2_PfHiCfgMsiIntWrEnRegPf = 0x00C84040, 89*c6fe65f0SNicolas Chautru VRB2_PfHiMsixVectorMapperPf = 0x00C84060, 90*c6fe65f0SNicolas Chautru VRB2_PfHiPfMode = 0x00C84108, 91*c6fe65f0SNicolas Chautru VRB2_PfHiClkGateHystReg = 0x00C8410C, 92*c6fe65f0SNicolas Chautru VRB2_PfHiMsiDropEnableReg = 0x00C84114, 93*c6fe65f0SNicolas Chautru VRB2_PfHiSectionPowerGatingReq = 0x00C84128, 94*c6fe65f0SNicolas Chautru VRB2_PfHiSectionPowerGatingAck = 0x00C8412C, 95*c6fe65f0SNicolas Chautru }; 96*c6fe65f0SNicolas Chautru 97*c6fe65f0SNicolas Chautru /* TIP PF Interrupt numbers */ 98*c6fe65f0SNicolas Chautru enum { 99*c6fe65f0SNicolas Chautru VRB2_PF_INT_QMGR_AQ_OVERFLOW = 0, 100*c6fe65f0SNicolas Chautru VRB2_PF_INT_DOORBELL_VF_2_PF = 1, 101*c6fe65f0SNicolas Chautru VRB2_PF_INT_ILLEGAL_FORMAT = 2, 102*c6fe65f0SNicolas Chautru VRB2_PF_INT_QMGR_DISABLED_ACCESS = 3, 103*c6fe65f0SNicolas Chautru VRB2_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, 104*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_DL_DESC_IRQ = 5, 105*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_UL_DESC_IRQ = 6, 106*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_FFT_DESC_IRQ = 7, 107*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_UL5G_DESC_IRQ = 8, 108*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_DL5G_DESC_IRQ = 9, 109*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_MLD_DESC_IRQ = 10, 110*c6fe65f0SNicolas Chautru VRB2_PF_INT_ARAM_ACCESS_ERR = 11, 111*c6fe65f0SNicolas Chautru VRB2_PF_INT_ARAM_ECC_1BIT_ERR = 12, 112*c6fe65f0SNicolas Chautru VRB2_PF_INT_PARITY_ERR = 13, 113*c6fe65f0SNicolas Chautru VRB2_PF_INT_QMGR_OVERFLOW = 14, 114*c6fe65f0SNicolas Chautru VRB2_PF_INT_QMGR_ERR = 15, 115*c6fe65f0SNicolas Chautru VRB2_PF_INT_ATS_ERR = 22, 116*c6fe65f0SNicolas Chautru VRB2_PF_INT_ARAM_FUUL = 23, 117*c6fe65f0SNicolas Chautru VRB2_PF_INT_EXTRA_READ = 24, 118*c6fe65f0SNicolas Chautru VRB2_PF_INT_COMPLETION_TIMEOUT = 25, 119*c6fe65f0SNicolas Chautru VRB2_PF_INT_CORE_HANG = 26, 120*c6fe65f0SNicolas Chautru VRB2_PF_INT_DMA_HANG = 28, 121*c6fe65f0SNicolas Chautru VRB2_PF_INT_DS_HANG = 27, 122*c6fe65f0SNicolas Chautru }; 123*c6fe65f0SNicolas Chautru 124*c6fe65f0SNicolas Chautru #endif /* VRB2_PF_ENUM_H */ 125