1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2023 Intel Corporation 3 */ 4 5 #ifndef VRB2_PF_ENUM_H 6 #define VRB2_PF_ENUM_H 7 8 /* 9 * VRB2 Register mapping on PF BAR0 10 * This is automatically generated from RDL, format may change with new RDL 11 * Release. 12 * Variable names are as is 13 */ 14 enum { 15 VRB2_PfQmgrEgressQueuesTemplate = 0x0007FC00, 16 VRB2_PfQmgrIngressAq = 0x00100000, 17 VRB2_PfQmgrSoftReset = 0x00A00034, 18 VRB2_PfQmgrAramAllocEn = 0x00A000a0, 19 VRB2_PfQmgrAramAllocSetupN0 = 0x00A000b0, 20 VRB2_PfQmgrAramAllocSetupN1 = 0x00A000b4, 21 VRB2_PfQmgrAramAllocSetupN2 = 0x00A000b8, 22 VRB2_PfQmgrAramAllocSetupN3 = 0x00A000bc, 23 VRB2_PfQmgrDepthLog2Grp = 0x00A00200, 24 VRB2_PfQmgrTholdGrp = 0x00A00300, 25 VRB2_PfQmgrGrpTmplateReg0Indx = 0x00A00600, 26 VRB2_PfQmgrGrpTmplateReg1Indx = 0x00A00700, 27 VRB2_PfQmgrGrpTmplateReg2Indx = 0x00A00800, 28 VRB2_PfQmgrGrpTmplateReg3Indx = 0x00A00900, 29 VRB2_PfQmgrGrpTmplateReg4Indx = 0x00A00A00, 30 VRB2_PfQmgrGrpTmplateReg5Indx = 0x00A00B00, 31 VRB2_PfQmgrGrpTmplateReg6Indx = 0x00A00C00, 32 VRB2_PfQmgrGrpTmplateReg7Indx = 0x00A00D00, 33 VRB2_PfQmgrGrpTmplateEnRegIndx = 0x00A00E00, 34 VRB2_PfQmgrArbQDepthGrp = 0x00A02F00, 35 VRB2_PfQmgrGrpFunction0 = 0x00A02F80, 36 VRB2_PfQmgrGrpPriority = 0x00A02FC0, 37 VRB2_PfQmgrVfBaseAddr = 0x00A08000, 38 VRB2_PfQmgrAqEnableVf = 0x00A10000, 39 VRB2_PfQmgrRingSizeVf = 0x00A20010, 40 VRB2_PfQmgrGrpDepthLog20Vf = 0x00A20020, 41 VRB2_PfQmgrGrpDepthLog21Vf = 0x00A20024, 42 VRB2_PfFabricM2iBufferReg = 0x00B30000, 43 VRB2_PfFecUl5gIbDebug0Reg = 0x00B401FC, 44 VRB2_PfFftConfig0 = 0x00B58004, 45 VRB2_PfFftParityMask8 = 0x00B5803C, 46 VRB2_PfDmaConfig0Reg = 0x00B80000, 47 VRB2_PfDmaConfig1Reg = 0x00B80004, 48 VRB2_PfDmaQmgrAddrReg = 0x00B80008, 49 VRB2_PfDmaAxcacheReg = 0x00B80010, 50 VRB2_PfDmaAxiControl = 0x00B8002C, 51 VRB2_PfDmaQmanen = 0x00B80040, 52 VRB2_PfDmaQmanenSelect = 0x00B80044, 53 VRB2_PfDmaCfgRrespBresp = 0x00B80814, 54 VRB2_PfDmaDescriptorSignature = 0x00B80868, 55 VRB2_PfDmaErrorDetectionEn = 0x00B80870, 56 VRB2_PfDmaFec5GulDescBaseLoRegVf = 0x00B88020, 57 VRB2_PfDmaFec5GulDescBaseHiRegVf = 0x00B88024, 58 VRB2_PfDmaFec5GulRespPtrLoRegVf = 0x00B88028, 59 VRB2_PfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, 60 VRB2_PfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, 61 VRB2_PfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, 62 VRB2_PfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, 63 VRB2_PfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, 64 VRB2_PfDmaFec4GulDescBaseLoRegVf = 0x00B88060, 65 VRB2_PfDmaFec4GulDescBaseHiRegVf = 0x00B88064, 66 VRB2_PfDmaFec4GulRespPtrLoRegVf = 0x00B88068, 67 VRB2_PfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, 68 VRB2_PfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, 69 VRB2_PfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, 70 VRB2_PfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, 71 VRB2_PfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, 72 VRB2_PfDmaFftDescBaseLoRegVf = 0x00B880A0, 73 VRB2_PfDmaFftDescBaseHiRegVf = 0x00B880A4, 74 VRB2_PfDmaFftRespPtrLoRegVf = 0x00B880A8, 75 VRB2_PfDmaFftRespPtrHiRegVf = 0x00B880AC, 76 VRB2_PfDmaMldDescBaseLoRegVf = 0x00B880C0, 77 VRB2_PfDmaMldDescBaseHiRegVf = 0x00B880C4, 78 VRB2_PfQosmonAEvalOverflow0 = 0x00B90008, 79 VRB2_PfPermonACntrlRegVf = 0x00B98000, 80 VRB2_PfQosmonBEvalOverflow0 = 0x00BA0008, 81 VRB2_PfPermonBCntrlRegVf = 0x00BA8000, 82 VRB2_PfPermonCCntrlRegVf = 0x00BB8000, 83 VRB2_PfHiInfoRingBaseLoRegPf = 0x00C84014, 84 VRB2_PfHiInfoRingBaseHiRegPf = 0x00C84018, 85 VRB2_PfHiInfoRingPointerRegPf = 0x00C8401C, 86 VRB2_PfHiInfoRingIntWrEnRegPf = 0x00C84020, 87 VRB2_PfHiBlockTransmitOnErrorEn = 0x00C84038, 88 VRB2_PfHiCfgMsiIntWrEnRegPf = 0x00C84040, 89 VRB2_PfHiMsixVectorMapperPf = 0x00C84060, 90 VRB2_PfHiPfMode = 0x00C84108, 91 VRB2_PfHiClkGateHystReg = 0x00C8410C, 92 VRB2_PfHiMsiDropEnableReg = 0x00C84114, 93 VRB2_PfHiSectionPowerGatingReq = 0x00C84128, 94 VRB2_PfHiSectionPowerGatingAck = 0x00C8412C, 95 }; 96 97 /* TIP PF Interrupt numbers */ 98 enum { 99 VRB2_PF_INT_QMGR_AQ_OVERFLOW = 0, 100 VRB2_PF_INT_DOORBELL_VF_2_PF = 1, 101 VRB2_PF_INT_ILLEGAL_FORMAT = 2, 102 VRB2_PF_INT_QMGR_DISABLED_ACCESS = 3, 103 VRB2_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, 104 VRB2_PF_INT_DMA_DL_DESC_IRQ = 5, 105 VRB2_PF_INT_DMA_UL_DESC_IRQ = 6, 106 VRB2_PF_INT_DMA_FFT_DESC_IRQ = 7, 107 VRB2_PF_INT_DMA_UL5G_DESC_IRQ = 8, 108 VRB2_PF_INT_DMA_DL5G_DESC_IRQ = 9, 109 VRB2_PF_INT_DMA_MLD_DESC_IRQ = 10, 110 VRB2_PF_INT_ARAM_ACCESS_ERR = 11, 111 VRB2_PF_INT_ARAM_ECC_1BIT_ERR = 12, 112 VRB2_PF_INT_PARITY_ERR = 13, 113 VRB2_PF_INT_QMGR_OVERFLOW = 14, 114 VRB2_PF_INT_QMGR_ERR = 15, 115 VRB2_PF_INT_ATS_ERR = 22, 116 VRB2_PF_INT_ARAM_FUUL = 23, 117 VRB2_PF_INT_EXTRA_READ = 24, 118 VRB2_PF_INT_COMPLETION_TIMEOUT = 25, 119 VRB2_PF_INT_CORE_HANG = 26, 120 VRB2_PF_INT_DMA_HANG = 28, 121 VRB2_PF_INT_DS_HANG = 27, 122 }; 123 124 #endif /* VRB2_PF_ENUM_H */ 125