1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2021 Intel Corporation 3 */ 4 5 #ifndef VRB1_PF_ENUM_H 6 #define VRB1_PF_ENUM_H 7 8 /* 9 * VRB1 Register mapping on PF BAR0 10 * This is automatically generated from RDL, format may change with new RDL 11 * Release. 12 * Variable names are as is 13 */ 14 enum { 15 VRB1_PfQmgrEgressQueuesTemplate = 0x0007FC00, 16 VRB1_PfQmgrIngressAq = 0x00080000, 17 VRB1_PfQmgrDepthLog2Grp = 0x00A00200, 18 VRB1_PfQmgrTholdGrp = 0x00A00300, 19 VRB1_PfQmgrGrpTmplateReg0Indx = 0x00A00600, 20 VRB1_PfQmgrGrpTmplateReg1Indx = 0x00A00700, 21 VRB1_PfQmgrGrpTmplateReg2indx = 0x00A00800, 22 VRB1_PfQmgrGrpTmplateReg3Indx = 0x00A00900, 23 VRB1_PfQmgrGrpTmplateReg4Indx = 0x00A00A00, 24 VRB1_PfQmgrVfBaseAddr = 0x00A01000, 25 VRB1_PfQmgrArbQDepthGrp = 0x00A02F00, 26 VRB1_PfQmgrGrpFunction0 = 0x00A02F40, 27 VRB1_PfQmgrGrpFunction1 = 0x00A02F44, 28 VRB1_PfQmgrGrpPriority = 0x00A02F48, 29 VRB1_PfQmgrAqEnableVf = 0x00A10000, 30 VRB1_PfQmgrRingSizeVf = 0x00A20004, 31 VRB1_PfQmgrGrpDepthLog20Vf = 0x00A20008, 32 VRB1_PfQmgrGrpDepthLog21Vf = 0x00A2000C, 33 VRB1_PfFabricM2iBufferReg = 0x00B30000, 34 VRB1_PfFabricI2Mdma_weight = 0x00B31044, 35 VRB1_PfFecUl5gIbDebugReg = 0x00B40200, 36 VRB1_PfFftConfig0 = 0x00B58004, 37 VRB1_PfFftRamPageAccess = 0x00B5800C, 38 VRB1_PfFftRamOff = 0x00B58800, 39 VRB1_PfDmaConfig0Reg = 0x00B80000, 40 VRB1_PfDmaConfig1Reg = 0x00B80004, 41 VRB1_PfDmaQmgrAddrReg = 0x00B80008, 42 VRB1_PfDmaAxcacheReg = 0x00B80010, 43 VRB1_PfDmaAxiControl = 0x00B8002C, 44 VRB1_PfDmaQmanen = 0x00B80040, 45 VRB1_PfDma4gdlIbThld = 0x00B800CC, 46 VRB1_PfDmaCfgRrespBresp = 0x00B80814, 47 VRB1_PfDmaDescriptorSignatuture = 0x00B80868, 48 VRB1_PfDmaErrorDetectionEn = 0x00B80870, 49 VRB1_PfDmaFec5GulDescBaseLoRegVf = 0x00B88020, 50 VRB1_PfDmaFec5GulDescBaseHiRegVf = 0x00B88024, 51 VRB1_PfDmaFec5GulRespPtrLoRegVf = 0x00B88028, 52 VRB1_PfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, 53 VRB1_PfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, 54 VRB1_PfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, 55 VRB1_PfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, 56 VRB1_PfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, 57 VRB1_PfDmaFec4GulDescBaseLoRegVf = 0x00B88060, 58 VRB1_PfDmaFec4GulDescBaseHiRegVf = 0x00B88064, 59 VRB1_PfDmaFec4GulRespPtrLoRegVf = 0x00B88068, 60 VRB1_PfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, 61 VRB1_PfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, 62 VRB1_PfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, 63 VRB1_PfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, 64 VRB1_PfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, 65 VRB1_PfDmaFftDescBaseLoRegVf = 0x00B880A0, 66 VRB1_PfDmaFftDescBaseHiRegVf = 0x00B880A4, 67 VRB1_PfDmaFftRespPtrLoRegVf = 0x00B880A8, 68 VRB1_PfDmaFftRespPtrHiRegVf = 0x00B880AC, 69 VRB1_PfQosmonAEvalOverflow0 = 0x00B90008, 70 VRB1_PfPermonACntrlRegVf = 0x00B98000, 71 VRB1_PfQosmonBEvalOverflow0 = 0x00BA0008, 72 VRB1_PfPermonBCntrlRegVf = 0x00BA8000, 73 VRB1_PfPermonCCntrlRegVf = 0x00BB8000, 74 VRB1_PfHiInfoRingBaseLoRegPf = 0x00C84014, 75 VRB1_PfHiInfoRingBaseHiRegPf = 0x00C84018, 76 VRB1_PfHiInfoRingPointerRegPf = 0x00C8401C, 77 VRB1_PfHiInfoRingIntWrEnRegPf = 0x00C84020, 78 VRB1_PfHiBlockTransmitOnErrorEn = 0x00C84038, 79 VRB1_PfHiCfgMsiIntWrEnRegPf = 0x00C84040, 80 VRB1_PfHiMsixVectorMapperPf = 0x00C84060, 81 VRB1_PfHiPfMode = 0x00C84108, 82 VRB1_PfHiClkGateHystReg = 0x00C8410C, 83 VRB1_PfHiMsiDropEnableReg = 0x00C84114, 84 VRB1_PfHiSectionPowerGatingReq = 0x00C84128, 85 VRB1_PfHiSectionPowerGatingAck = 0x00C8412C, 86 }; 87 88 /* TIP PF Interrupt numbers */ 89 enum { 90 ACC_PF_INT_QMGR_AQ_OVERFLOW = 0, 91 ACC_PF_INT_DOORBELL_VF_2_PF = 1, 92 ACC_PF_INT_ILLEGAL_FORMAT = 2, 93 ACC_PF_INT_QMGR_DISABLED_ACCESS = 3, 94 ACC_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, 95 ACC_PF_INT_DMA_DL_DESC_IRQ = 5, 96 ACC_PF_INT_DMA_UL_DESC_IRQ = 6, 97 ACC_PF_INT_DMA_FFT_DESC_IRQ = 7, 98 ACC_PF_INT_DMA_UL5G_DESC_IRQ = 8, 99 ACC_PF_INT_DMA_DL5G_DESC_IRQ = 9, 100 ACC_PF_INT_DMA_MLD_DESC_IRQ = 10, 101 ACC_PF_INT_ARAM_ACCESS_ERR = 11, 102 ACC_PF_INT_ARAM_ECC_1BIT_ERR = 12, 103 ACC_PF_INT_PARITY_ERR = 13, 104 ACC_PF_INT_QMGR_OVERFLOW = 14, 105 ACC_PF_INT_QMGR_ERR = 15, 106 ACC_PF_INT_ATS_ERR = 22, 107 ACC_PF_INT_ARAM_FUUL = 23, 108 ACC_PF_INT_EXTRA_READ = 24, 109 ACC_PF_INT_COMPLETION_TIMEOUT = 25, 110 ACC_PF_INT_CORE_HANG = 26, 111 ACC_PF_INT_DMA_HANG = 28, 112 ACC_PF_INT_DS_HANG = 27, 113 }; 114 115 #endif /* VRB1_PF_ENUM_H */ 116