1*dcf43d24SNicolas Chautru /* SPDX-License-Identifier: BSD-3-Clause 2*dcf43d24SNicolas Chautru * Copyright(c) 2017 Intel Corporation 3*dcf43d24SNicolas Chautru */ 4*dcf43d24SNicolas Chautru 5*dcf43d24SNicolas Chautru #ifndef ACC100_PF_ENUM_H 6*dcf43d24SNicolas Chautru #define ACC100_PF_ENUM_H 7*dcf43d24SNicolas Chautru 8*dcf43d24SNicolas Chautru /* 9*dcf43d24SNicolas Chautru * ACC100 Register mapping on PF BAR0 10*dcf43d24SNicolas Chautru * This is automatically generated from RDL, format may change with new RDL 11*dcf43d24SNicolas Chautru * Release. 12*dcf43d24SNicolas Chautru * Variable names are as is 13*dcf43d24SNicolas Chautru */ 14*dcf43d24SNicolas Chautru enum { 15*dcf43d24SNicolas Chautru HWPfQmgrEgressQueuesTemplate = 0x0007FE00, 16*dcf43d24SNicolas Chautru HWPfQmgrIngressAq = 0x00080000, 17*dcf43d24SNicolas Chautru HWPfQmgrDepthLog2Grp = 0x00A00200, 18*dcf43d24SNicolas Chautru HWPfQmgrTholdGrp = 0x00A00300, 19*dcf43d24SNicolas Chautru HWPfQmgrGrpTmplateReg0Indx = 0x00A00600, 20*dcf43d24SNicolas Chautru HWPfQmgrGrpTmplateReg1Indx = 0x00A00680, 21*dcf43d24SNicolas Chautru HWPfQmgrGrpTmplateReg2indx = 0x00A00700, 22*dcf43d24SNicolas Chautru HWPfQmgrGrpTmplateReg3Indx = 0x00A00780, 23*dcf43d24SNicolas Chautru HWPfQmgrGrpTmplateReg4Indx = 0x00A00800, 24*dcf43d24SNicolas Chautru HWPfQmgrVfBaseAddr = 0x00A01000, 25*dcf43d24SNicolas Chautru HWPfQmgrArbQDepthGrp = 0x00A02F00, 26*dcf43d24SNicolas Chautru HWPfQmgrGrpFunction0 = 0x00A02F40, 27*dcf43d24SNicolas Chautru HWPfQmgrGrpPriority = 0x00A02F48, 28*dcf43d24SNicolas Chautru HWPfQmgrAqEnableVf = 0x00A10000, 29*dcf43d24SNicolas Chautru HWPfQmgrRingSizeVf = 0x00A20004, 30*dcf43d24SNicolas Chautru HWPfQmgrGrpDepthLog20Vf = 0x00A20008, 31*dcf43d24SNicolas Chautru HWPfQmgrGrpDepthLog21Vf = 0x00A2000C, 32*dcf43d24SNicolas Chautru HWPfDmaConfig0Reg = 0x00B80000, 33*dcf43d24SNicolas Chautru HWPfDmaConfig1Reg = 0x00B80004, 34*dcf43d24SNicolas Chautru HWPfDmaQmgrAddrReg = 0x00B80008, 35*dcf43d24SNicolas Chautru HWPfDmaAxcacheReg = 0x00B80010, 36*dcf43d24SNicolas Chautru HWPfDmaAxiControl = 0x00B8002C, 37*dcf43d24SNicolas Chautru HWPfDmaQmanen = 0x00B80040, 38*dcf43d24SNicolas Chautru HWPfDmaInboundDrainDataSize = 0x00B800C0, 39*dcf43d24SNicolas Chautru HWPfDmaVfDdrBaseRw = 0x00B80400, 40*dcf43d24SNicolas Chautru HWPfDmaDescriptorSignatuture = 0x00B80868, 41*dcf43d24SNicolas Chautru HWPfDmaErrorDetectionEn = 0x00B80870, 42*dcf43d24SNicolas Chautru HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020, 43*dcf43d24SNicolas Chautru HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024, 44*dcf43d24SNicolas Chautru HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028, 45*dcf43d24SNicolas Chautru HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, 46*dcf43d24SNicolas Chautru HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, 47*dcf43d24SNicolas Chautru HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, 48*dcf43d24SNicolas Chautru HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, 49*dcf43d24SNicolas Chautru HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, 50*dcf43d24SNicolas Chautru HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060, 51*dcf43d24SNicolas Chautru HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064, 52*dcf43d24SNicolas Chautru HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068, 53*dcf43d24SNicolas Chautru HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, 54*dcf43d24SNicolas Chautru HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, 55*dcf43d24SNicolas Chautru HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, 56*dcf43d24SNicolas Chautru HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, 57*dcf43d24SNicolas Chautru HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, 58*dcf43d24SNicolas Chautru HWPfQosmonAEvalOverflow0 = 0x00B90008, 59*dcf43d24SNicolas Chautru HWPfPermonACntrlRegVf = 0x00B98000, 60*dcf43d24SNicolas Chautru HWPfQosmonBEvalOverflow0 = 0x00BA0008, 61*dcf43d24SNicolas Chautru HWPfPermonBCntrlRegVf = 0x00BA8000, 62*dcf43d24SNicolas Chautru HWPfFabricMode = 0x00BB1000, 63*dcf43d24SNicolas Chautru HWPfFecUl5gCntrlReg = 0x00BC0000, 64*dcf43d24SNicolas Chautru HwPfFecUl5gIbDebugReg = 0x00BC0200, 65*dcf43d24SNicolas Chautru HWPfChaDl5gPllPhshft0 = 0x00C40098, 66*dcf43d24SNicolas Chautru HWPfChaDdrStDoneStatus = 0x00C40434, 67*dcf43d24SNicolas Chautru HWPfChaDdrWbRstCfg = 0x00C40438, 68*dcf43d24SNicolas Chautru HWPfChaDdrApbRstCfg = 0x00C4043C, 69*dcf43d24SNicolas Chautru HWPfChaDdrPhyRstCfg = 0x00C40440, 70*dcf43d24SNicolas Chautru HWPfChaDdrCpuRstCfg = 0x00C40444, 71*dcf43d24SNicolas Chautru HWPfChaDdrSifRstCfg = 0x00C40448, 72*dcf43d24SNicolas Chautru HWPfHi5GHardResetReg = 0x00C8400C, 73*dcf43d24SNicolas Chautru HWPfHiInfoRingBaseLoRegPf = 0x00C84010, 74*dcf43d24SNicolas Chautru HWPfHiInfoRingBaseHiRegPf = 0x00C84014, 75*dcf43d24SNicolas Chautru HWPfHiInfoRingPointerRegPf = 0x00C84018, 76*dcf43d24SNicolas Chautru HWPfHiInfoRingIntWrEnRegPf = 0x00C84020, 77*dcf43d24SNicolas Chautru HWPfHiInfoRingVf2pfLoWrEnReg = 0x00C84024, 78*dcf43d24SNicolas Chautru HWPfHiBlockTransmitOnErrorEn = 0x00C84038, 79*dcf43d24SNicolas Chautru HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040, 80*dcf43d24SNicolas Chautru HWPfHiCfgMsiVf2pfLoWrEnReg = 0x00C84044, 81*dcf43d24SNicolas Chautru HWPfHiPfMode = 0x00C84108, 82*dcf43d24SNicolas Chautru HWPfHiClkGateHystReg = 0x00C8410C, 83*dcf43d24SNicolas Chautru HWPfHiMsiDropEnableReg = 0x00C84114, 84*dcf43d24SNicolas Chautru HWPfDdrUmmcCtrl = 0x00D00020, 85*dcf43d24SNicolas Chautru HWPfDdrMemInitPhyTrng0 = 0x00D00240, 86*dcf43d24SNicolas Chautru HWPfDdrBcDram = 0x00D003C0, 87*dcf43d24SNicolas Chautru HWPfDdrBcAddrMap = 0x00D003D0, 88*dcf43d24SNicolas Chautru HWPfDdrBcRef = 0x00D003E0, 89*dcf43d24SNicolas Chautru HWPfDdrBcTim0 = 0x00D00400, 90*dcf43d24SNicolas Chautru HWPfDdrBcTim1 = 0x00D00410, 91*dcf43d24SNicolas Chautru HWPfDdrBcTim2 = 0x00D00420, 92*dcf43d24SNicolas Chautru HWPfDdrBcTim3 = 0x00D00430, 93*dcf43d24SNicolas Chautru HWPfDdrBcTim4 = 0x00D00440, 94*dcf43d24SNicolas Chautru HWPfDdrBcTim5 = 0x00D00450, 95*dcf43d24SNicolas Chautru HWPfDdrBcTim6 = 0x00D00460, 96*dcf43d24SNicolas Chautru HWPfDdrBcTim7 = 0x00D00470, 97*dcf43d24SNicolas Chautru HWPfDdrBcTim8 = 0x00D00480, 98*dcf43d24SNicolas Chautru HWPfDdrBcTim9 = 0x00D00490, 99*dcf43d24SNicolas Chautru HWPfDdrBcTim10 = 0x00D004A0, 100*dcf43d24SNicolas Chautru HWPfDdrDfiInit = 0x00D004D0, 101*dcf43d24SNicolas Chautru HWPfDdrDfiTim0 = 0x00D004F0, 102*dcf43d24SNicolas Chautru HWPfDdrDfiTim1 = 0x00D00500, 103*dcf43d24SNicolas Chautru HWPfDdrDfiPhyUpdEn = 0x00D00530, 104*dcf43d24SNicolas Chautru HWPfDdrUmmcIntEn = 0x00D00570, 105*dcf43d24SNicolas Chautru HWPfDdrPhyRdLatency = 0x00D48400, 106*dcf43d24SNicolas Chautru HWPfDdrPhyRdLatencyDbi = 0x00D48410, 107*dcf43d24SNicolas Chautru HWPfDdrPhyWrLatency = 0x00D48420, 108*dcf43d24SNicolas Chautru HWPfDdrPhyTrngType = 0x00D48430, 109*dcf43d24SNicolas Chautru HWPfDdrPhyMr01Dimm = 0x00D484C0, 110*dcf43d24SNicolas Chautru HWPfDdrPhyMr01DimmDbi = 0x00D484D0, 111*dcf43d24SNicolas Chautru HWPfDdrPhyMr23Dimm = 0x00D484E0, 112*dcf43d24SNicolas Chautru HWPfDdrPhyMr45Dimm = 0x00D484F0, 113*dcf43d24SNicolas Chautru HWPfDdrPhyMr67Dimm = 0x00D48500, 114*dcf43d24SNicolas Chautru HWPfDdrPhyWrlvlWwRdlvlRr = 0x00D48510, 115*dcf43d24SNicolas Chautru HWPfDdrPhyIdletimeout = 0x00D48560, 116*dcf43d24SNicolas Chautru HWPfDdrPhyDqsCountMax = 0x00D485D0, 117*dcf43d24SNicolas Chautru HWPfDdrPhyDqsCountNum = 0x00D485E0, 118*dcf43d24SNicolas Chautru HWPfDdrPhyIdtmFwVersion = 0x00D6C410, 119*dcf43d24SNicolas Chautru HWPfDdrPhyDqsCount = 0x00D70020, 120*dcf43d24SNicolas Chautru HwPfPcieLnAdaptctrl = 0x00D80108, 121*dcf43d24SNicolas Chautru HwPfPciePcsEqControl = 0x00D81098, 122*dcf43d24SNicolas Chautru HwPfPcieGpexBridgeControl = 0x00D90808, 123*dcf43d24SNicolas Chautru HwPfPcieGpexAxiPioControl = 0x00D90840, 124*dcf43d24SNicolas Chautru HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh = 0x00D90BAC, 125*dcf43d24SNicolas Chautru }; 126*dcf43d24SNicolas Chautru 127*dcf43d24SNicolas Chautru /* TIP PF Interrupt numbers */ 128*dcf43d24SNicolas Chautru enum { 129*dcf43d24SNicolas Chautru ACC100_PF_INT_QMGR_AQ_OVERFLOW = 0, 130*dcf43d24SNicolas Chautru ACC100_PF_INT_DOORBELL_VF_2_PF = 1, 131*dcf43d24SNicolas Chautru ACC100_PF_INT_DMA_DL_DESC_IRQ = 2, 132*dcf43d24SNicolas Chautru ACC100_PF_INT_DMA_UL_DESC_IRQ = 3, 133*dcf43d24SNicolas Chautru ACC100_PF_INT_DMA_MLD_DESC_IRQ = 4, 134*dcf43d24SNicolas Chautru ACC100_PF_INT_DMA_UL5G_DESC_IRQ = 5, 135*dcf43d24SNicolas Chautru ACC100_PF_INT_DMA_DL5G_DESC_IRQ = 6, 136*dcf43d24SNicolas Chautru ACC100_PF_INT_ILLEGAL_FORMAT = 7, 137*dcf43d24SNicolas Chautru ACC100_PF_INT_QMGR_DISABLED_ACCESS = 8, 138*dcf43d24SNicolas Chautru ACC100_PF_INT_QMGR_AQ_OVERTHRESHOLD = 9, 139*dcf43d24SNicolas Chautru ACC100_PF_INT_ARAM_ACCESS_ERR = 10, 140*dcf43d24SNicolas Chautru ACC100_PF_INT_ARAM_ECC_1BIT_ERR = 11, 141*dcf43d24SNicolas Chautru ACC100_PF_INT_PARITY_ERR = 12, 142*dcf43d24SNicolas Chautru ACC100_PF_INT_QMGR_ERR = 13, 143*dcf43d24SNicolas Chautru ACC100_PF_INT_INT_REQ_OVERFLOW = 14, 144*dcf43d24SNicolas Chautru ACC100_PF_INT_APB_TIMEOUT = 15, 145*dcf43d24SNicolas Chautru }; 146*dcf43d24SNicolas Chautru 147*dcf43d24SNicolas Chautru #endif /* ACC100_PF_ENUM_H */ 148