1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5 #ifndef ACC100_PF_ENUM_H 6 #define ACC100_PF_ENUM_H 7 8 /* 9 * ACC100 Register mapping on PF BAR0 10 * This is automatically generated from RDL, format may change with new RDL 11 * Release. 12 * Variable names are as is 13 */ 14 enum { 15 HWPfQmgrEgressQueuesTemplate = 0x0007FE00, 16 HWPfQmgrIngressAq = 0x00080000, 17 HWPfQmgrDepthLog2Grp = 0x00A00200, 18 HWPfQmgrTholdGrp = 0x00A00300, 19 HWPfQmgrGrpTmplateReg0Indx = 0x00A00600, 20 HWPfQmgrGrpTmplateReg1Indx = 0x00A00680, 21 HWPfQmgrGrpTmplateReg2indx = 0x00A00700, 22 HWPfQmgrGrpTmplateReg3Indx = 0x00A00780, 23 HWPfQmgrGrpTmplateReg4Indx = 0x00A00800, 24 HWPfQmgrVfBaseAddr = 0x00A01000, 25 HWPfQmgrArbQDepthGrp = 0x00A02F00, 26 HWPfQmgrGrpFunction0 = 0x00A02F40, 27 HWPfQmgrGrpPriority = 0x00A02F48, 28 HWPfQmgrAqEnableVf = 0x00A10000, 29 HWPfQmgrRingSizeVf = 0x00A20004, 30 HWPfQmgrGrpDepthLog20Vf = 0x00A20008, 31 HWPfQmgrGrpDepthLog21Vf = 0x00A2000C, 32 HWPfDmaConfig0Reg = 0x00B80000, 33 HWPfDmaConfig1Reg = 0x00B80004, 34 HWPfDmaQmgrAddrReg = 0x00B80008, 35 HWPfDmaAxcacheReg = 0x00B80010, 36 HWPfDmaAxiControl = 0x00B8002C, 37 HWPfDmaQmanen = 0x00B80040, 38 HWPfDmaInboundDrainDataSize = 0x00B800C0, 39 HWPfDmaVfDdrBaseRw = 0x00B80400, 40 HWPfDmaDescriptorSignatuture = 0x00B80868, 41 HWPfDmaErrorDetectionEn = 0x00B80870, 42 HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020, 43 HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024, 44 HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028, 45 HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, 46 HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, 47 HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, 48 HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, 49 HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, 50 HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060, 51 HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064, 52 HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068, 53 HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, 54 HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, 55 HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, 56 HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, 57 HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, 58 HWPfQosmonAEvalOverflow0 = 0x00B90008, 59 HWPfPermonACntrlRegVf = 0x00B98000, 60 HWPfQosmonBEvalOverflow0 = 0x00BA0008, 61 HWPfPermonBCntrlRegVf = 0x00BA8000, 62 HWPfFabricMode = 0x00BB1000, 63 HWPfFecUl5gCntrlReg = 0x00BC0000, 64 HwPfFecUl5gIbDebugReg = 0x00BC0200, 65 HWPfChaDl5gPllPhshft0 = 0x00C40098, 66 HWPfChaDdrStDoneStatus = 0x00C40434, 67 HWPfChaDdrWbRstCfg = 0x00C40438, 68 HWPfChaDdrApbRstCfg = 0x00C4043C, 69 HWPfChaDdrPhyRstCfg = 0x00C40440, 70 HWPfChaDdrCpuRstCfg = 0x00C40444, 71 HWPfChaDdrSifRstCfg = 0x00C40448, 72 HWPfHi5GHardResetReg = 0x00C8400C, 73 HWPfHiInfoRingBaseLoRegPf = 0x00C84010, 74 HWPfHiInfoRingBaseHiRegPf = 0x00C84014, 75 HWPfHiInfoRingPointerRegPf = 0x00C84018, 76 HWPfHiInfoRingIntWrEnRegPf = 0x00C84020, 77 HWPfHiInfoRingVf2pfLoWrEnReg = 0x00C84024, 78 HWPfHiBlockTransmitOnErrorEn = 0x00C84038, 79 HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040, 80 HWPfHiCfgMsiVf2pfLoWrEnReg = 0x00C84044, 81 HWPfHiPfMode = 0x00C84108, 82 HWPfHiClkGateHystReg = 0x00C8410C, 83 HWPfHiMsiDropEnableReg = 0x00C84114, 84 HWPfDdrUmmcCtrl = 0x00D00020, 85 HWPfDdrMemInitPhyTrng0 = 0x00D00240, 86 HWPfDdrBcDram = 0x00D003C0, 87 HWPfDdrBcAddrMap = 0x00D003D0, 88 HWPfDdrBcRef = 0x00D003E0, 89 HWPfDdrBcTim0 = 0x00D00400, 90 HWPfDdrBcTim1 = 0x00D00410, 91 HWPfDdrBcTim2 = 0x00D00420, 92 HWPfDdrBcTim3 = 0x00D00430, 93 HWPfDdrBcTim4 = 0x00D00440, 94 HWPfDdrBcTim5 = 0x00D00450, 95 HWPfDdrBcTim6 = 0x00D00460, 96 HWPfDdrBcTim7 = 0x00D00470, 97 HWPfDdrBcTim8 = 0x00D00480, 98 HWPfDdrBcTim9 = 0x00D00490, 99 HWPfDdrBcTim10 = 0x00D004A0, 100 HWPfDdrDfiInit = 0x00D004D0, 101 HWPfDdrDfiTim0 = 0x00D004F0, 102 HWPfDdrDfiTim1 = 0x00D00500, 103 HWPfDdrDfiPhyUpdEn = 0x00D00530, 104 HWPfDdrUmmcIntEn = 0x00D00570, 105 HWPfDdrPhyRdLatency = 0x00D48400, 106 HWPfDdrPhyRdLatencyDbi = 0x00D48410, 107 HWPfDdrPhyWrLatency = 0x00D48420, 108 HWPfDdrPhyTrngType = 0x00D48430, 109 HWPfDdrPhyMr01Dimm = 0x00D484C0, 110 HWPfDdrPhyMr01DimmDbi = 0x00D484D0, 111 HWPfDdrPhyMr23Dimm = 0x00D484E0, 112 HWPfDdrPhyMr45Dimm = 0x00D484F0, 113 HWPfDdrPhyMr67Dimm = 0x00D48500, 114 HWPfDdrPhyWrlvlWwRdlvlRr = 0x00D48510, 115 HWPfDdrPhyIdletimeout = 0x00D48560, 116 HWPfDdrPhyDqsCountMax = 0x00D485D0, 117 HWPfDdrPhyDqsCountNum = 0x00D485E0, 118 HWPfDdrPhyIdtmFwVersion = 0x00D6C410, 119 HWPfDdrPhyDqsCount = 0x00D70020, 120 HwPfPcieLnAdaptctrl = 0x00D80108, 121 HwPfPciePcsEqControl = 0x00D81098, 122 HwPfPcieGpexBridgeControl = 0x00D90808, 123 HwPfPcieGpexAxiPioControl = 0x00D90840, 124 HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh = 0x00D90BAC, 125 }; 126 127 /* TIP PF Interrupt numbers */ 128 enum { 129 ACC100_PF_INT_QMGR_AQ_OVERFLOW = 0, 130 ACC100_PF_INT_DOORBELL_VF_2_PF = 1, 131 ACC100_PF_INT_DMA_DL_DESC_IRQ = 2, 132 ACC100_PF_INT_DMA_UL_DESC_IRQ = 3, 133 ACC100_PF_INT_DMA_MLD_DESC_IRQ = 4, 134 ACC100_PF_INT_DMA_UL5G_DESC_IRQ = 5, 135 ACC100_PF_INT_DMA_DL5G_DESC_IRQ = 6, 136 ACC100_PF_INT_ILLEGAL_FORMAT = 7, 137 ACC100_PF_INT_QMGR_DISABLED_ACCESS = 8, 138 ACC100_PF_INT_QMGR_AQ_OVERTHRESHOLD = 9, 139 ACC100_PF_INT_ARAM_ACCESS_ERR = 10, 140 ACC100_PF_INT_ARAM_ECC_1BIT_ERR = 11, 141 ACC100_PF_INT_PARITY_ERR = 12, 142 ACC100_PF_INT_QMGR_ERR = 13, 143 ACC100_PF_INT_INT_REQ_OVERFLOW = 14, 144 ACC100_PF_INT_APB_TIMEOUT = 15, 145 }; 146 147 #endif /* ACC100_PF_ENUM_H */ 148