xref: /dpdk/doc/guides/prog_guide/mempool_lib.rst (revision a3f34a98b7217f4ff2a8636096984f566a4e7cab)
1fc1f2750SBernard Iremonger..  BSD LICENSE
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31fc1f2750SBernard Iremonger.. _Mempool_Library:
32fc1f2750SBernard Iremonger
33fc1f2750SBernard IremongerMempool Library
34fc1f2750SBernard Iremonger===============
35fc1f2750SBernard Iremonger
36fc1f2750SBernard IremongerA memory pool is an allocator of a fixed-sized object.
3748624fd9SSiobhan ButlerIn the DPDK, it is identified by name and uses a ring to store free objects.
38fc1f2750SBernard IremongerIt provides some other optional services such as a per-core object cache and
39fc1f2750SBernard Iremongeran alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
40fc1f2750SBernard Iremonger
41*a3f34a98SThomas MonjalonThis library is used by the :ref:`Mbuf Library <Mbuf_Library>`.
42fc1f2750SBernard Iremonger
43fc1f2750SBernard IremongerCookies
44fc1f2750SBernard Iremonger-------
45fc1f2750SBernard Iremonger
46fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.
47fc1f2750SBernard IremongerThe allocated objects then contain overwrite protection fields to help debugging buffer overflows.
48fc1f2750SBernard Iremonger
49fc1f2750SBernard IremongerStats
50fc1f2750SBernard Iremonger-----
51fc1f2750SBernard Iremonger
52fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
53fc1f2750SBernard Iremongerstatistics about get from/put in the pool are stored in the mempool structure.
54fc1f2750SBernard IremongerStatistics are per-lcore to avoid concurrent access to statistics counters.
55fc1f2750SBernard Iremonger
56fc1f2750SBernard IremongerMemory Alignment Constraints
57fc1f2750SBernard Iremonger----------------------------
58fc1f2750SBernard Iremonger
59fc1f2750SBernard IremongerDepending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.
60fc1f2750SBernard IremongerThe objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.
61fc1f2750SBernard Iremonger
62fc1f2750SBernard IremongerThis is particularly true for packet buffers when doing L3 forwarding or flow classification.
63fc1f2750SBernard IremongerOnly the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.
64fc1f2750SBernard Iremonger
65fc1f2750SBernard IremongerThe number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.
66fc1f2750SBernard IremongerThe ranks cannot be accessed simultaneously since they share the same data path.
67fc1f2750SBernard IremongerThe physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.
68fc1f2750SBernard Iremonger
69fc1f2750SBernard IremongerWhen running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.
70fc1f2750SBernard Iremonger
71fc1f2750SBernard Iremonger.. note::
72fc1f2750SBernard Iremonger
73fc1f2750SBernard Iremonger    The command line must always have the number of memory channels specified for the processor.
74fc1f2750SBernard Iremonger
754a22e6eeSJohn McNamaraExamples of alignment for different DIMM architectures are shown in
764a22e6eeSJohn McNamara:numref:`figure_memory-management` and :numref:`figure_memory-management2`.
77fc1f2750SBernard Iremonger
784a22e6eeSJohn McNamara.. _figure_memory-management:
79fc1f2750SBernard Iremonger
804a22e6eeSJohn McNamara.. figure:: img/memory-management.*
81fc1f2750SBernard Iremonger
824a22e6eeSJohn McNamara   Two Channels and Quad-ranked DIMM Example
83fc1f2750SBernard Iremonger
84fc1f2750SBernard Iremonger
85fc1f2750SBernard IremongerIn this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.
86fc1f2750SBernard Iremonger
87fc1f2750SBernard IremongerThe Intel® 5520 chipset has three channels, so in most cases,
88fc1f2750SBernard Iremongerno padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).
89fc1f2750SBernard Iremonger
904a22e6eeSJohn McNamara.. _figure_memory-management2:
91fc1f2750SBernard Iremonger
924a22e6eeSJohn McNamara.. figure:: img/memory-management2.*
93fc1f2750SBernard Iremonger
944a22e6eeSJohn McNamara   Three Channels and Two Dual-ranked DIMM Example
95fc1f2750SBernard Iremonger
96fc1f2750SBernard Iremonger
97fc1f2750SBernard IremongerWhen creating a new pool, the user can specify to use this feature or not.
98fc1f2750SBernard Iremonger
9929e30cbcSThomas Monjalon.. _mempool_local_cache:
10029e30cbcSThomas Monjalon
101fc1f2750SBernard IremongerLocal Cache
102fc1f2750SBernard Iremonger-----------
103fc1f2750SBernard Iremonger
104fc1f2750SBernard IremongerIn terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high
105fc1f2750SBernard Iremongersince each access requires a compare-and-set (CAS) operation.
106fc1f2750SBernard IremongerTo avoid having too many access requests to the memory pool's ring,
107fc1f2750SBernard Iremongerthe memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,
108fc1f2750SBernard Iremongervia the cache with many fewer locks on the actual memory pool structure.
109fc1f2750SBernard IremongerIn this way, each core has full access to its own cache (with locks) of free objects and
110fc1f2750SBernard Iremongeronly when the cache fills does the core need to shuffle some of the free objects back to the pools ring or
111fc1f2750SBernard Iremongerobtain more objects when the cache is empty.
112fc1f2750SBernard Iremonger
113fc1f2750SBernard IremongerWhile this may mean a number of buffers may sit idle on some core's cache,
114fc1f2750SBernard Iremongerthe speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.
115fc1f2750SBernard Iremonger
116fc1f2750SBernard IremongerThe cache is composed of a small, per-core table of pointers and its length (used as a stack).
117fc1f2750SBernard IremongerThis cache can be enabled or disabled at creation of the pool.
118fc1f2750SBernard Iremonger
119fc1f2750SBernard IremongerThe maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).
120fc1f2750SBernard Iremonger
1214a22e6eeSJohn McNamara:numref:`figure_mempool` shows a cache in operation.
122fc1f2750SBernard Iremonger
1234a22e6eeSJohn McNamara.. _figure_mempool:
124fc1f2750SBernard Iremonger
1254a22e6eeSJohn McNamara.. figure:: img/mempool.*
126fc1f2750SBernard Iremonger
1274a22e6eeSJohn McNamara   A mempool in Memory with its Associated Ring
128fc1f2750SBernard Iremonger
129fc1f2750SBernard Iremonger
130fc1f2750SBernard IremongerUse Cases
131fc1f2750SBernard Iremonger---------
132fc1f2750SBernard Iremonger
133fc1f2750SBernard IremongerAll allocations that require a high level of performance should use a pool-based memory allocator.
134fc1f2750SBernard IremongerBelow are some examples:
135fc1f2750SBernard Iremonger
136fc1f2750SBernard Iremonger*   :ref:`Mbuf Library <Mbuf_Library>`
137fc1f2750SBernard Iremonger
138fc1f2750SBernard Iremonger*   :ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` , for logging service
139fc1f2750SBernard Iremonger
140fc1f2750SBernard Iremonger*   Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.
141