xref: /dpdk/doc/guides/prog_guide/mempool_lib.rst (revision 4b5062755aa74517ed1d7bd6829b7e9f28b801d8)
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30fc1f2750SBernard Iremonger
31fc1f2750SBernard Iremonger.. _Mempool_Library:
32fc1f2750SBernard Iremonger
33fc1f2750SBernard IremongerMempool Library
34fc1f2750SBernard Iremonger===============
35fc1f2750SBernard Iremonger
36fc1f2750SBernard IremongerA memory pool is an allocator of a fixed-sized object.
37449c49b9SDavid HuntIn the DPDK, it is identified by name and uses a mempool handler to store free objects.
38449c49b9SDavid HuntThe default mempool handler is ring based.
39fc1f2750SBernard IremongerIt provides some other optional services such as a per-core object cache and
40fc1f2750SBernard Iremongeran alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
41fc1f2750SBernard Iremonger
42a3f34a98SThomas MonjalonThis library is used by the :ref:`Mbuf Library <Mbuf_Library>`.
43fc1f2750SBernard Iremonger
44fc1f2750SBernard IremongerCookies
45fc1f2750SBernard Iremonger-------
46fc1f2750SBernard Iremonger
47fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.
48fc1f2750SBernard IremongerThe allocated objects then contain overwrite protection fields to help debugging buffer overflows.
49fc1f2750SBernard Iremonger
50fc1f2750SBernard IremongerStats
51fc1f2750SBernard Iremonger-----
52fc1f2750SBernard Iremonger
53fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
54fc1f2750SBernard Iremongerstatistics about get from/put in the pool are stored in the mempool structure.
55fc1f2750SBernard IremongerStatistics are per-lcore to avoid concurrent access to statistics counters.
56fc1f2750SBernard Iremonger
57fc1f2750SBernard IremongerMemory Alignment Constraints
58fc1f2750SBernard Iremonger----------------------------
59fc1f2750SBernard Iremonger
60fc1f2750SBernard IremongerDepending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.
61fc1f2750SBernard IremongerThe objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.
62fc1f2750SBernard Iremonger
63fc1f2750SBernard IremongerThis is particularly true for packet buffers when doing L3 forwarding or flow classification.
64fc1f2750SBernard IremongerOnly the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.
65fc1f2750SBernard Iremonger
66fc1f2750SBernard IremongerThe number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.
67fc1f2750SBernard IremongerThe ranks cannot be accessed simultaneously since they share the same data path.
68fc1f2750SBernard IremongerThe physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.
69fc1f2750SBernard Iremonger
70fc1f2750SBernard IremongerWhen running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.
71fc1f2750SBernard Iremonger
72fc1f2750SBernard Iremonger.. note::
73fc1f2750SBernard Iremonger
74fc1f2750SBernard Iremonger    The command line must always have the number of memory channels specified for the processor.
75fc1f2750SBernard Iremonger
764a22e6eeSJohn McNamaraExamples of alignment for different DIMM architectures are shown in
774a22e6eeSJohn McNamara:numref:`figure_memory-management` and :numref:`figure_memory-management2`.
78fc1f2750SBernard Iremonger
794a22e6eeSJohn McNamara.. _figure_memory-management:
80fc1f2750SBernard Iremonger
814a22e6eeSJohn McNamara.. figure:: img/memory-management.*
82fc1f2750SBernard Iremonger
834a22e6eeSJohn McNamara   Two Channels and Quad-ranked DIMM Example
84fc1f2750SBernard Iremonger
85fc1f2750SBernard Iremonger
86fc1f2750SBernard IremongerIn this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.
87fc1f2750SBernard Iremonger
88fc1f2750SBernard IremongerThe Intel® 5520 chipset has three channels, so in most cases,
89fc1f2750SBernard Iremongerno padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).
90fc1f2750SBernard Iremonger
914a22e6eeSJohn McNamara.. _figure_memory-management2:
92fc1f2750SBernard Iremonger
934a22e6eeSJohn McNamara.. figure:: img/memory-management2.*
94fc1f2750SBernard Iremonger
954a22e6eeSJohn McNamara   Three Channels and Two Dual-ranked DIMM Example
96fc1f2750SBernard Iremonger
97fc1f2750SBernard Iremonger
98fc1f2750SBernard IremongerWhen creating a new pool, the user can specify to use this feature or not.
99fc1f2750SBernard Iremonger
10029e30cbcSThomas Monjalon.. _mempool_local_cache:
10129e30cbcSThomas Monjalon
102fc1f2750SBernard IremongerLocal Cache
103fc1f2750SBernard Iremonger-----------
104fc1f2750SBernard Iremonger
105fc1f2750SBernard IremongerIn terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high
106fc1f2750SBernard Iremongersince each access requires a compare-and-set (CAS) operation.
107fc1f2750SBernard IremongerTo avoid having too many access requests to the memory pool's ring,
108fc1f2750SBernard Iremongerthe memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,
109fc1f2750SBernard Iremongervia the cache with many fewer locks on the actual memory pool structure.
110fc1f2750SBernard IremongerIn this way, each core has full access to its own cache (with locks) of free objects and
111fc1f2750SBernard Iremongeronly when the cache fills does the core need to shuffle some of the free objects back to the pools ring or
112fc1f2750SBernard Iremongerobtain more objects when the cache is empty.
113fc1f2750SBernard Iremonger
114fc1f2750SBernard IremongerWhile this may mean a number of buffers may sit idle on some core's cache,
115fc1f2750SBernard Iremongerthe speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.
116fc1f2750SBernard Iremonger
117fc1f2750SBernard IremongerThe cache is composed of a small, per-core table of pointers and its length (used as a stack).
118*4b506275SLazaros KoromilasThis internal cache can be enabled or disabled at creation of the pool.
119fc1f2750SBernard Iremonger
120fc1f2750SBernard IremongerThe maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).
121fc1f2750SBernard Iremonger
1224a22e6eeSJohn McNamara:numref:`figure_mempool` shows a cache in operation.
123fc1f2750SBernard Iremonger
1244a22e6eeSJohn McNamara.. _figure_mempool:
125fc1f2750SBernard Iremonger
1264a22e6eeSJohn McNamara.. figure:: img/mempool.*
127fc1f2750SBernard Iremonger
1284a22e6eeSJohn McNamara   A mempool in Memory with its Associated Ring
129fc1f2750SBernard Iremonger
130*4b506275SLazaros KoromilasAlternatively to the internal default per-lcore local cache, an application can create and manage external caches through the ``rte_mempool_cache_create()``, ``rte_mempool_cache_free()`` and ``rte_mempool_cache_flush()`` calls.
131*4b506275SLazaros KoromilasThese user-owned caches can be explicitly passed to ``rte_mempool_generic_put()`` and ``rte_mempool_generic_get()``.
132*4b506275SLazaros KoromilasThe ``rte_mempool_default_cache()`` call returns the default internal cache if any.
133*4b506275SLazaros KoromilasIn contrast to the default caches, user-owned caches can be used by non-EAL threads too.
134fc1f2750SBernard Iremonger
135449c49b9SDavid HuntMempool Handlers
136449c49b9SDavid Hunt------------------------
137449c49b9SDavid Hunt
138449c49b9SDavid HuntThis allows external memory subsystems, such as external hardware memory
139449c49b9SDavid Huntmanagement systems and software based memory allocators, to be used with DPDK.
140449c49b9SDavid Hunt
141449c49b9SDavid HuntThere are two aspects to a mempool handler.
142449c49b9SDavid Hunt
143449c49b9SDavid Hunt* Adding the code for your new mempool operations (ops). This is achieved by
144449c49b9SDavid Hunt  adding a new mempool ops code, and using the ``REGISTER_MEMPOOL_OPS`` macro.
145449c49b9SDavid Hunt
146449c49b9SDavid Hunt* Using the new API to call ``rte_mempool_create_empty()`` and
147449c49b9SDavid Hunt  ``rte_mempool_set_ops_byname()`` to create a new mempool and specifying which
148449c49b9SDavid Hunt  ops to use.
149449c49b9SDavid Hunt
150449c49b9SDavid HuntSeveral different mempool handlers may be used in the same application. A new
151449c49b9SDavid Huntmempool can be created by using the ``rte_mempool_create_empty()`` function,
152449c49b9SDavid Huntthen using ``rte_mempool_set_ops_byname()`` to point the mempool to the
153449c49b9SDavid Huntrelevant mempool handler callback (ops) structure.
154449c49b9SDavid Hunt
155449c49b9SDavid HuntLegacy applications may continue to use the old ``rte_mempool_create()`` API
156449c49b9SDavid Huntcall, which uses a ring based mempool handler by default. These applications
157449c49b9SDavid Huntwill need to be modified to use a new mempool handler.
158449c49b9SDavid Hunt
159449c49b9SDavid HuntFor applications that use ``rte_pktmbuf_create()``, there is a config setting
160449c49b9SDavid Hunt(``RTE_MBUF_DEFAULT_MEMPOOL_OPS``) that allows the application to make use of
161449c49b9SDavid Huntan alternative mempool handler.
162449c49b9SDavid Hunt
163449c49b9SDavid Hunt
164fc1f2750SBernard IremongerUse Cases
165fc1f2750SBernard Iremonger---------
166fc1f2750SBernard Iremonger
167fc1f2750SBernard IremongerAll allocations that require a high level of performance should use a pool-based memory allocator.
168fc1f2750SBernard IremongerBelow are some examples:
169fc1f2750SBernard Iremonger
170fc1f2750SBernard Iremonger*   :ref:`Mbuf Library <Mbuf_Library>`
171fc1f2750SBernard Iremonger
172fc1f2750SBernard Iremonger*   :ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` , for logging service
173fc1f2750SBernard Iremonger
174fc1f2750SBernard Iremonger*   Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.
175