xref: /dpdk/doc/guides/prog_guide/mempool_lib.rst (revision 48624fd96e7c4a9603e383baa193909fea392232)
1fc1f2750SBernard Iremonger..  BSD LICENSE
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31fc1f2750SBernard Iremonger.. _Mempool_Library:
32fc1f2750SBernard Iremonger
33fc1f2750SBernard IremongerMempool Library
34fc1f2750SBernard Iremonger===============
35fc1f2750SBernard Iremonger
36fc1f2750SBernard IremongerA memory pool is an allocator of a fixed-sized object.
37*48624fd9SSiobhan ButlerIn the DPDK, it is identified by name and uses a ring to store free objects.
38fc1f2750SBernard IremongerIt provides some other optional services such as a per-core object cache and
39fc1f2750SBernard Iremongeran alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.
40fc1f2750SBernard Iremonger
41fc1f2750SBernard IremongerThis library is used by the
42fc1f2750SBernard Iremonger:ref:`Mbuf Library <Mbuf_Library>` and the
43fc1f2750SBernard Iremonger:ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` (for logging history).
44fc1f2750SBernard Iremonger
45fc1f2750SBernard IremongerCookies
46fc1f2750SBernard Iremonger-------
47fc1f2750SBernard Iremonger
48fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.
49fc1f2750SBernard IremongerThe allocated objects then contain overwrite protection fields to help debugging buffer overflows.
50fc1f2750SBernard Iremonger
51fc1f2750SBernard IremongerStats
52fc1f2750SBernard Iremonger-----
53fc1f2750SBernard Iremonger
54fc1f2750SBernard IremongerIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
55fc1f2750SBernard Iremongerstatistics about get from/put in the pool are stored in the mempool structure.
56fc1f2750SBernard IremongerStatistics are per-lcore to avoid concurrent access to statistics counters.
57fc1f2750SBernard Iremonger
58fc1f2750SBernard IremongerMemory Alignment Constraints
59fc1f2750SBernard Iremonger----------------------------
60fc1f2750SBernard Iremonger
61fc1f2750SBernard IremongerDepending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.
62fc1f2750SBernard IremongerThe objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.
63fc1f2750SBernard Iremonger
64fc1f2750SBernard IremongerThis is particularly true for packet buffers when doing L3 forwarding or flow classification.
65fc1f2750SBernard IremongerOnly the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.
66fc1f2750SBernard Iremonger
67fc1f2750SBernard IremongerThe number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.
68fc1f2750SBernard IremongerThe ranks cannot be accessed simultaneously since they share the same data path.
69fc1f2750SBernard IremongerThe physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.
70fc1f2750SBernard Iremonger
71fc1f2750SBernard IremongerWhen running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.
72fc1f2750SBernard Iremonger
73fc1f2750SBernard Iremonger.. note::
74fc1f2750SBernard Iremonger
75fc1f2750SBernard Iremonger    The command line must always have the number of memory channels specified for the processor.
76fc1f2750SBernard Iremonger
77fc1f2750SBernard IremongerExamples of alignment for different DIMM architectures are shown in Figure 5 and Figure 6.
78fc1f2750SBernard Iremonger
79fc1f2750SBernard Iremonger.. _pg_figure_5:
80fc1f2750SBernard Iremonger
81fc1f2750SBernard Iremonger**Figure 5. Two Channels and Quad-ranked DIMM Example**
82fc1f2750SBernard Iremonger
83fc1f2750SBernard Iremonger.. image19_png has been replaced
84fc1f2750SBernard Iremonger
85fc1f2750SBernard Iremonger|memory-management|
86fc1f2750SBernard Iremonger
87fc1f2750SBernard IremongerIn this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.
88fc1f2750SBernard Iremonger
89fc1f2750SBernard IremongerThe Intel® 5520 chipset has three channels, so in most cases,
90fc1f2750SBernard Iremongerno padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).
91fc1f2750SBernard Iremonger
92fc1f2750SBernard Iremonger.. _pg_figure_6:
93fc1f2750SBernard Iremonger
94fc1f2750SBernard Iremonger**Figure 6. Three Channels and Two Dual-ranked DIMM Example**
95fc1f2750SBernard Iremonger
96fc1f2750SBernard Iremonger.. image20_png has been replaced
97fc1f2750SBernard Iremonger
98fc1f2750SBernard Iremonger|memory-management2|
99fc1f2750SBernard Iremonger
100fc1f2750SBernard IremongerWhen creating a new pool, the user can specify to use this feature or not.
101fc1f2750SBernard Iremonger
102fc1f2750SBernard IremongerLocal Cache
103fc1f2750SBernard Iremonger-----------
104fc1f2750SBernard Iremonger
105fc1f2750SBernard IremongerIn terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high
106fc1f2750SBernard Iremongersince each access requires a compare-and-set (CAS) operation.
107fc1f2750SBernard IremongerTo avoid having too many access requests to the memory pool's ring,
108fc1f2750SBernard Iremongerthe memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,
109fc1f2750SBernard Iremongervia the cache with many fewer locks on the actual memory pool structure.
110fc1f2750SBernard IremongerIn this way, each core has full access to its own cache (with locks) of free objects and
111fc1f2750SBernard Iremongeronly when the cache fills does the core need to shuffle some of the free objects back to the pools ring or
112fc1f2750SBernard Iremongerobtain more objects when the cache is empty.
113fc1f2750SBernard Iremonger
114fc1f2750SBernard IremongerWhile this may mean a number of buffers may sit idle on some core's cache,
115fc1f2750SBernard Iremongerthe speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.
116fc1f2750SBernard Iremonger
117fc1f2750SBernard IremongerThe cache is composed of a small, per-core table of pointers and its length (used as a stack).
118fc1f2750SBernard IremongerThis cache can be enabled or disabled at creation of the pool.
119fc1f2750SBernard Iremonger
120fc1f2750SBernard IremongerThe maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).
121fc1f2750SBernard Iremonger
122fc1f2750SBernard IremongerFigure 7 shows a cache in operation.
123fc1f2750SBernard Iremonger
124fc1f2750SBernard Iremonger.. _pg_figure_7:
125fc1f2750SBernard Iremonger
126fc1f2750SBernard Iremonger**Figure 7. A mempool in Memory with its Associated Ring**
127fc1f2750SBernard Iremonger
128fc1f2750SBernard Iremonger.. image21_png has been replaced
129fc1f2750SBernard Iremonger
130fc1f2750SBernard Iremonger|mempool|
131fc1f2750SBernard Iremonger
132fc1f2750SBernard IremongerUse Cases
133fc1f2750SBernard Iremonger---------
134fc1f2750SBernard Iremonger
135fc1f2750SBernard IremongerAll allocations that require a high level of performance should use a pool-based memory allocator.
136fc1f2750SBernard IremongerBelow are some examples:
137fc1f2750SBernard Iremonger
138fc1f2750SBernard Iremonger*   :ref:`Mbuf Library <Mbuf_Library>`
139fc1f2750SBernard Iremonger
140fc1f2750SBernard Iremonger*   :ref:`Environment Abstraction Layer <Environment_Abstraction_Layer>` , for logging service
141fc1f2750SBernard Iremonger
142fc1f2750SBernard Iremonger*   Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.
143fc1f2750SBernard Iremonger
144fc1f2750SBernard Iremonger.. |memory-management| image:: img/memory-management.svg
145fc1f2750SBernard Iremonger
146fc1f2750SBernard Iremonger.. |memory-management2| image:: img/memory-management2.svg
147fc1f2750SBernard Iremonger
148fc1f2750SBernard Iremonger.. |mempool| image:: img/mempool.svg
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