1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <math.h> 6 7 #include "test_perf_common.h" 8 9 #define NB_CRYPTODEV_DESCRIPTORS 1024 10 #define DATA_SIZE 512 11 #define IV_OFFSET (sizeof(struct rte_crypto_op) + \ 12 sizeof(struct rte_crypto_sym_op) + \ 13 sizeof(union rte_event_crypto_metadata)) 14 15 struct modex_test_data { 16 enum rte_crypto_asym_xform_type xform_type; 17 struct { 18 uint8_t data[DATA_SIZE]; 19 uint16_t len; 20 } base; 21 struct { 22 uint8_t data[DATA_SIZE]; 23 uint16_t len; 24 } exponent; 25 struct { 26 uint8_t data[DATA_SIZE]; 27 uint16_t len; 28 } modulus; 29 struct { 30 uint8_t data[DATA_SIZE]; 31 uint16_t len; 32 } reminder; 33 uint16_t result_len; 34 }; 35 36 static struct 37 modex_test_data modex_test_case = { 38 .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, 39 .base = { 40 .data = { 41 0xF8, 0xBA, 0x1A, 0x55, 0xD0, 0x2F, 0x85, 42 0xAE, 0x96, 0x7B, 0xB6, 0x2F, 0xB6, 0xCD, 43 0xA8, 0xEB, 0x7E, 0x78, 0xA0, 0x50 44 }, 45 .len = 20, 46 }, 47 .exponent = { 48 .data = { 49 0x01, 0x00, 0x01 50 }, 51 .len = 3, 52 }, 53 .reminder = { 54 .data = { 55 0x2C, 0x60, 0x75, 0x45, 0x98, 0x9D, 0xE0, 0x72, 56 0xA0, 0x9D, 0x3A, 0x9E, 0x03, 0x38, 0x73, 0x3C, 57 0x31, 0x83, 0x04, 0xFE, 0x75, 0x43, 0xE6, 0x17, 58 0x5C, 0x01, 0x29, 0x51, 0x69, 0x33, 0x62, 0x2D, 59 0x78, 0xBE, 0xAE, 0xC4, 0xBC, 0xDE, 0x7E, 0x2C, 60 0x77, 0x84, 0xF2, 0xC5, 0x14, 0xB5, 0x2F, 0xF7, 61 0xC5, 0x94, 0xEF, 0x86, 0x75, 0x75, 0xB5, 0x11, 62 0xE5, 0x0E, 0x0A, 0x29, 0x76, 0xE2, 0xEA, 0x32, 63 0x0E, 0x43, 0x77, 0x7E, 0x2C, 0x27, 0xAC, 0x3B, 64 0x86, 0xA5, 0xDB, 0xC9, 0x48, 0x40, 0xE8, 0x99, 65 0x9A, 0x0A, 0x3D, 0xD6, 0x74, 0xFA, 0x2E, 0x2E, 66 0x5B, 0xAF, 0x8C, 0x99, 0x44, 0x2A, 0x67, 0x38, 67 0x27, 0x41, 0x59, 0x9D, 0xB8, 0x51, 0xC9, 0xF7, 68 0x43, 0x61, 0x31, 0x6E, 0xF1, 0x25, 0x38, 0x7F, 69 0xAE, 0xC6, 0xD0, 0xBB, 0x29, 0x76, 0x3F, 0x46, 70 0x2E, 0x1B, 0xE4, 0x67, 0x71, 0xE3, 0x87, 0x5A 71 }, 72 .len = 128, 73 }, 74 .modulus = { 75 .data = { 76 0xb3, 0xa1, 0xaf, 0xb7, 0x13, 0x08, 0x00, 0x0a, 77 0x35, 0xdc, 0x2b, 0x20, 0x8d, 0xa1, 0xb5, 0xce, 78 0x47, 0x8a, 0xc3, 0x80, 0xf4, 0x7d, 0x4a, 0xa2, 79 0x62, 0xfd, 0x61, 0x7f, 0xb5, 0xa8, 0xde, 0x0a, 80 0x17, 0x97, 0xa0, 0xbf, 0xdf, 0x56, 0x5a, 0x3d, 81 0x51, 0x56, 0x4f, 0x70, 0x70, 0x3f, 0x63, 0x6a, 82 0x44, 0x5b, 0xad, 0x84, 0x0d, 0x3f, 0x27, 0x6e, 83 0x3b, 0x34, 0x91, 0x60, 0x14, 0xb9, 0xaa, 0x72, 84 0xfd, 0xa3, 0x64, 0xd2, 0x03, 0xa7, 0x53, 0x87, 85 0x9e, 0x88, 0x0b, 0xc1, 0x14, 0x93, 0x1a, 0x62, 86 0xff, 0xb1, 0x5d, 0x74, 0xcd, 0x59, 0x63, 0x18, 87 0x11, 0x3d, 0x4f, 0xba, 0x75, 0xd4, 0x33, 0x4e, 88 0x23, 0x6b, 0x7b, 0x57, 0x44, 0xe1, 0xd3, 0x03, 89 0x13, 0xa6, 0xf0, 0x8b, 0x60, 0xb0, 0x9e, 0xee, 90 0x75, 0x08, 0x9d, 0x71, 0x63, 0x13, 0xcb, 0xa6, 91 0x81, 0x92, 0x14, 0x03, 0x22, 0x2d, 0xde, 0x55 92 }, 93 .len = 128, 94 }, 95 .result_len = 128, 96 }; 97 98 int 99 perf_test_result(struct evt_test *test, struct evt_options *opt) 100 { 101 RTE_SET_USED(opt); 102 int i; 103 uint64_t total = 0; 104 struct test_perf *t = evt_test_priv(test); 105 106 printf("Packet distribution across worker cores :\n"); 107 for (i = 0; i < t->nb_workers; i++) 108 total += t->worker[i].processed_pkts; 109 for (i = 0; i < t->nb_workers; i++) 110 printf("Worker %d packets: "CLGRN"%"PRIx64" "CLNRM"percentage:" 111 CLGRN" %3.2f"CLNRM"\n", i, 112 t->worker[i].processed_pkts, 113 (((double)t->worker[i].processed_pkts)/total) 114 * 100); 115 116 return t->result; 117 } 118 119 static inline int 120 perf_producer(void *arg) 121 { 122 int i; 123 struct prod_data *p = arg; 124 struct test_perf *t = p->t; 125 struct evt_options *opt = t->opt; 126 const uint8_t dev_id = p->dev_id; 127 const uint8_t port = p->port_id; 128 struct rte_mempool *pool = t->pool; 129 const uint64_t nb_pkts = t->nb_pkts; 130 const uint32_t nb_flows = t->nb_flows; 131 uint32_t flow_counter = 0; 132 uint64_t count = 0; 133 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 134 uint8_t enable_fwd_latency; 135 struct rte_event ev; 136 137 enable_fwd_latency = opt->fwd_latency; 138 if (opt->verbose_level > 1) 139 printf("%s(): lcore %d dev_id %d port=%d queue %d\n", __func__, 140 rte_lcore_id(), dev_id, port, p->queue_id); 141 142 ev.event = 0; 143 ev.op = RTE_EVENT_OP_NEW; 144 ev.queue_id = p->queue_id; 145 ev.sched_type = t->opt->sched_type_list[0]; 146 ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 147 ev.event_type = RTE_EVENT_TYPE_CPU; 148 ev.sub_event_type = 0; /* stage 0 */ 149 150 while (count < nb_pkts && t->done == false) { 151 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 152 continue; 153 for (i = 0; i < BURST_SIZE; i++) { 154 ev.flow_id = flow_counter++ % nb_flows; 155 ev.event_ptr = m[i]; 156 if (enable_fwd_latency) 157 m[i]->timestamp = rte_get_timer_cycles(); 158 while (rte_event_enqueue_new_burst(dev_id, port, &ev, 159 1) != 1) { 160 if (t->done) 161 break; 162 rte_pause(); 163 if (enable_fwd_latency) 164 m[i]->timestamp = 165 rte_get_timer_cycles(); 166 } 167 } 168 count += BURST_SIZE; 169 } 170 171 return 0; 172 } 173 174 static inline int 175 perf_producer_burst(void *arg) 176 { 177 uint32_t i; 178 uint64_t timestamp; 179 struct prod_data *p = arg; 180 struct test_perf *t = p->t; 181 struct evt_options *opt = t->opt; 182 const uint8_t dev_id = p->dev_id; 183 const uint8_t port = p->port_id; 184 struct rte_mempool *pool = t->pool; 185 const uint64_t nb_pkts = t->nb_pkts; 186 const uint32_t nb_flows = t->nb_flows; 187 uint32_t flow_counter = 0; 188 uint16_t enq = 0; 189 uint64_t count = 0; 190 struct perf_elt *m[opt->prod_enq_burst_sz + 1]; 191 struct rte_event ev[opt->prod_enq_burst_sz + 1]; 192 uint32_t burst_size = opt->prod_enq_burst_sz; 193 uint8_t enable_fwd_latency; 194 195 enable_fwd_latency = opt->fwd_latency; 196 memset(m, 0, sizeof(*m) * (opt->prod_enq_burst_sz + 1)); 197 if (opt->verbose_level > 1) 198 printf("%s(): lcore %d dev_id %d port=%d queue %d\n", __func__, 199 rte_lcore_id(), dev_id, port, p->queue_id); 200 201 for (i = 0; i < burst_size; i++) { 202 ev[i].op = RTE_EVENT_OP_NEW; 203 ev[i].queue_id = p->queue_id; 204 ev[i].sched_type = t->opt->sched_type_list[0]; 205 ev[i].priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 206 ev[i].event_type = RTE_EVENT_TYPE_CPU; 207 ev[i].sub_event_type = 0; /* stage 0 */ 208 } 209 210 while (count < nb_pkts && t->done == false) { 211 if (rte_mempool_get_bulk(pool, (void **)m, burst_size) < 0) 212 continue; 213 timestamp = rte_get_timer_cycles(); 214 for (i = 0; i < burst_size; i++) { 215 ev[i].flow_id = flow_counter++ % nb_flows; 216 ev[i].event_ptr = m[i]; 217 if (enable_fwd_latency) 218 m[i]->timestamp = timestamp; 219 } 220 enq = rte_event_enqueue_new_burst(dev_id, port, ev, burst_size); 221 while (enq < burst_size) { 222 enq += rte_event_enqueue_new_burst( 223 dev_id, port, ev + enq, burst_size - enq); 224 if (t->done) 225 break; 226 rte_pause(); 227 if (enable_fwd_latency) { 228 timestamp = rte_get_timer_cycles(); 229 for (i = enq; i < burst_size; i++) 230 m[i]->timestamp = timestamp; 231 } 232 } 233 count += burst_size; 234 } 235 return 0; 236 } 237 238 static inline int 239 perf_event_timer_producer(void *arg) 240 { 241 int i; 242 struct prod_data *p = arg; 243 struct test_perf *t = p->t; 244 struct evt_options *opt = t->opt; 245 uint32_t flow_counter = 0; 246 uint64_t count = 0; 247 uint64_t arm_latency = 0; 248 const uint8_t nb_timer_adptrs = opt->nb_timer_adptrs; 249 const uint32_t nb_flows = t->nb_flows; 250 const uint64_t nb_timers = opt->nb_timers; 251 struct rte_mempool *pool = t->pool; 252 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 253 struct rte_event_timer_adapter **adptr = t->timer_adptr; 254 struct rte_event_timer tim; 255 uint64_t timeout_ticks = opt->expiry_nsec / opt->timer_tick_nsec; 256 257 memset(&tim, 0, sizeof(struct rte_event_timer)); 258 timeout_ticks = 259 opt->optm_timer_tick_nsec 260 ? ceil((double)(timeout_ticks * opt->timer_tick_nsec) / 261 opt->optm_timer_tick_nsec) 262 : timeout_ticks; 263 timeout_ticks += timeout_ticks ? 0 : 1; 264 tim.ev.event_type = RTE_EVENT_TYPE_TIMER; 265 tim.ev.op = RTE_EVENT_OP_NEW; 266 tim.ev.sched_type = t->opt->sched_type_list[0]; 267 tim.ev.queue_id = p->queue_id; 268 tim.ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 269 tim.state = RTE_EVENT_TIMER_NOT_ARMED; 270 tim.timeout_ticks = timeout_ticks; 271 272 if (opt->verbose_level > 1) 273 printf("%s(): lcore %d\n", __func__, rte_lcore_id()); 274 275 while (count < nb_timers && t->done == false) { 276 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 277 continue; 278 for (i = 0; i < BURST_SIZE; i++) { 279 rte_prefetch0(m[i + 1]); 280 m[i]->tim = tim; 281 m[i]->tim.ev.flow_id = flow_counter++ % nb_flows; 282 m[i]->tim.ev.event_ptr = m[i]; 283 m[i]->timestamp = rte_get_timer_cycles(); 284 while (rte_event_timer_arm_burst( 285 adptr[flow_counter % nb_timer_adptrs], 286 (struct rte_event_timer **)&m[i], 1) != 1) { 287 if (t->done) 288 break; 289 m[i]->timestamp = rte_get_timer_cycles(); 290 } 291 arm_latency += rte_get_timer_cycles() - m[i]->timestamp; 292 } 293 count += BURST_SIZE; 294 } 295 fflush(stdout); 296 rte_delay_ms(1000); 297 printf("%s(): lcore %d Average event timer arm latency = %.3f us\n", 298 __func__, rte_lcore_id(), 299 count ? (float)(arm_latency / count) / 300 (rte_get_timer_hz() / 1000000) : 0); 301 return 0; 302 } 303 304 static inline int 305 perf_event_timer_producer_burst(void *arg) 306 { 307 int i; 308 struct prod_data *p = arg; 309 struct test_perf *t = p->t; 310 struct evt_options *opt = t->opt; 311 uint32_t flow_counter = 0; 312 uint64_t count = 0; 313 uint64_t arm_latency = 0; 314 const uint8_t nb_timer_adptrs = opt->nb_timer_adptrs; 315 const uint32_t nb_flows = t->nb_flows; 316 const uint64_t nb_timers = opt->nb_timers; 317 struct rte_mempool *pool = t->pool; 318 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 319 struct rte_event_timer_adapter **adptr = t->timer_adptr; 320 struct rte_event_timer tim; 321 uint64_t timeout_ticks = opt->expiry_nsec / opt->timer_tick_nsec; 322 323 memset(&tim, 0, sizeof(struct rte_event_timer)); 324 timeout_ticks = 325 opt->optm_timer_tick_nsec 326 ? ceil((double)(timeout_ticks * opt->timer_tick_nsec) / 327 opt->optm_timer_tick_nsec) 328 : timeout_ticks; 329 timeout_ticks += timeout_ticks ? 0 : 1; 330 tim.ev.event_type = RTE_EVENT_TYPE_TIMER; 331 tim.ev.op = RTE_EVENT_OP_NEW; 332 tim.ev.sched_type = t->opt->sched_type_list[0]; 333 tim.ev.queue_id = p->queue_id; 334 tim.ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 335 tim.state = RTE_EVENT_TIMER_NOT_ARMED; 336 tim.timeout_ticks = timeout_ticks; 337 338 if (opt->verbose_level > 1) 339 printf("%s(): lcore %d\n", __func__, rte_lcore_id()); 340 341 while (count < nb_timers && t->done == false) { 342 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 343 continue; 344 for (i = 0; i < BURST_SIZE; i++) { 345 rte_prefetch0(m[i + 1]); 346 m[i]->tim = tim; 347 m[i]->tim.ev.flow_id = flow_counter++ % nb_flows; 348 m[i]->tim.ev.event_ptr = m[i]; 349 m[i]->timestamp = rte_get_timer_cycles(); 350 } 351 rte_event_timer_arm_tmo_tick_burst( 352 adptr[flow_counter % nb_timer_adptrs], 353 (struct rte_event_timer **)m, 354 tim.timeout_ticks, 355 BURST_SIZE); 356 arm_latency += rte_get_timer_cycles() - m[i - 1]->timestamp; 357 count += BURST_SIZE; 358 } 359 fflush(stdout); 360 rte_delay_ms(1000); 361 printf("%s(): lcore %d Average event timer arm latency = %.3f us\n", 362 __func__, rte_lcore_id(), 363 count ? (float)(arm_latency / count) / 364 (rte_get_timer_hz() / 1000000) : 0); 365 return 0; 366 } 367 368 static inline void 369 crypto_adapter_enq_op_new(struct prod_data *p) 370 { 371 struct test_perf *t = p->t; 372 const uint32_t nb_flows = t->nb_flows; 373 const uint64_t nb_pkts = t->nb_pkts; 374 struct rte_mempool *pool = t->pool; 375 uint16_t data_length, data_offset; 376 struct evt_options *opt = t->opt; 377 uint16_t qp_id = p->ca.cdev_qp_id; 378 uint8_t cdev_id = p->ca.cdev_id; 379 uint64_t alloc_failures = 0; 380 uint32_t flow_counter = 0; 381 struct rte_crypto_op *op; 382 uint16_t len, offset; 383 struct rte_mbuf *m; 384 uint64_t count = 0; 385 386 if (opt->verbose_level > 1) 387 printf("%s(): lcore %d queue %d cdev_id %u cdev_qp_id %u\n", 388 __func__, rte_lcore_id(), p->queue_id, p->ca.cdev_id, 389 p->ca.cdev_qp_id); 390 391 offset = sizeof(struct perf_elt); 392 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 393 394 if (opt->crypto_cipher_bit_mode) { 395 data_offset = offset << 3; 396 data_length = (len - offset) << 3; 397 } else { 398 data_offset = offset; 399 data_length = len - offset; 400 } 401 402 while (count < nb_pkts && t->done == false) { 403 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 404 struct rte_crypto_sym_op *sym_op; 405 406 op = rte_crypto_op_alloc(t->ca_op_pool, 407 RTE_CRYPTO_OP_TYPE_SYMMETRIC); 408 if (unlikely(op == NULL)) { 409 alloc_failures++; 410 continue; 411 } 412 413 m = rte_pktmbuf_alloc(pool); 414 if (unlikely(m == NULL)) { 415 alloc_failures++; 416 rte_crypto_op_free(op); 417 continue; 418 } 419 420 rte_pktmbuf_append(m, len); 421 sym_op = op->sym; 422 sym_op->m_src = m; 423 424 sym_op->cipher.data.offset = data_offset; 425 sym_op->cipher.data.length = data_length; 426 427 rte_crypto_op_attach_sym_session( 428 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 429 } else { 430 struct rte_crypto_asym_op *asym_op; 431 uint8_t *result; 432 433 if (rte_mempool_get(pool, (void **)&result)) { 434 alloc_failures++; 435 continue; 436 } 437 438 op = rte_crypto_op_alloc(t->ca_op_pool, 439 RTE_CRYPTO_OP_TYPE_ASYMMETRIC); 440 if (unlikely(op == NULL)) { 441 alloc_failures++; 442 rte_mempool_put(pool, result); 443 continue; 444 } 445 446 asym_op = op->asym; 447 asym_op->modex.base.data = modex_test_case.base.data; 448 asym_op->modex.base.length = modex_test_case.base.len; 449 asym_op->modex.result.data = result; 450 asym_op->modex.result.length = modex_test_case.result_len; 451 rte_crypto_op_attach_asym_session( 452 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 453 } 454 while (rte_cryptodev_enqueue_burst(cdev_id, qp_id, &op, 1) != 1 && 455 t->done == false) 456 rte_pause(); 457 458 count++; 459 } 460 461 if (opt->verbose_level > 1 && alloc_failures) 462 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 463 __func__, rte_lcore_id(), alloc_failures); 464 } 465 466 static inline void 467 crypto_adapter_enq_op_fwd(struct prod_data *p) 468 { 469 const uint8_t dev_id = p->dev_id; 470 const uint8_t port = p->port_id; 471 struct test_perf *t = p->t; 472 const uint32_t nb_flows = t->nb_flows; 473 const uint64_t nb_pkts = t->nb_pkts; 474 struct rte_mempool *pool = t->pool; 475 struct evt_options *opt = t->opt; 476 uint64_t alloc_failures = 0; 477 uint32_t flow_counter = 0; 478 struct rte_crypto_op *op; 479 uint16_t len, offset; 480 struct rte_event ev; 481 struct rte_mbuf *m; 482 uint64_t count = 0; 483 484 if (opt->verbose_level > 1) 485 printf("%s(): lcore %d port %d queue %d cdev_id %u cdev_qp_id %u\n", 486 __func__, rte_lcore_id(), port, p->queue_id, 487 p->ca.cdev_id, p->ca.cdev_qp_id); 488 489 ev.event = 0; 490 ev.op = RTE_EVENT_OP_NEW; 491 ev.queue_id = p->queue_id; 492 ev.sched_type = RTE_SCHED_TYPE_ATOMIC; 493 ev.event_type = RTE_EVENT_TYPE_CPU; 494 495 offset = sizeof(struct perf_elt); 496 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 497 498 while (count < nb_pkts && t->done == false) { 499 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 500 struct rte_crypto_sym_op *sym_op; 501 502 op = rte_crypto_op_alloc(t->ca_op_pool, 503 RTE_CRYPTO_OP_TYPE_SYMMETRIC); 504 if (unlikely(op == NULL)) { 505 alloc_failures++; 506 continue; 507 } 508 509 m = rte_pktmbuf_alloc(pool); 510 if (unlikely(m == NULL)) { 511 alloc_failures++; 512 rte_crypto_op_free(op); 513 continue; 514 } 515 516 rte_pktmbuf_append(m, len); 517 sym_op = op->sym; 518 sym_op->m_src = m; 519 sym_op->cipher.data.offset = offset; 520 sym_op->cipher.data.length = len - offset; 521 rte_crypto_op_attach_sym_session( 522 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 523 } else { 524 struct rte_crypto_asym_op *asym_op; 525 uint8_t *result; 526 527 if (rte_mempool_get(pool, (void **)&result)) { 528 alloc_failures++; 529 continue; 530 } 531 532 op = rte_crypto_op_alloc(t->ca_op_pool, 533 RTE_CRYPTO_OP_TYPE_ASYMMETRIC); 534 if (unlikely(op == NULL)) { 535 alloc_failures++; 536 rte_mempool_put(pool, result); 537 continue; 538 } 539 540 asym_op = op->asym; 541 asym_op->modex.base.data = modex_test_case.base.data; 542 asym_op->modex.base.length = modex_test_case.base.len; 543 asym_op->modex.result.data = result; 544 asym_op->modex.result.length = modex_test_case.result_len; 545 rte_crypto_op_attach_asym_session( 546 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 547 } 548 ev.event_ptr = op; 549 550 while (rte_event_crypto_adapter_enqueue(dev_id, port, &ev, 1) != 1 && 551 t->done == false) 552 rte_pause(); 553 554 count++; 555 } 556 557 if (opt->verbose_level > 1 && alloc_failures) 558 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 559 __func__, rte_lcore_id(), alloc_failures); 560 } 561 562 static inline int 563 perf_event_crypto_producer(void *arg) 564 { 565 struct prod_data *p = arg; 566 struct evt_options *opt = p->t->opt; 567 568 if (opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) 569 crypto_adapter_enq_op_new(p); 570 else 571 crypto_adapter_enq_op_fwd(p); 572 573 return 0; 574 } 575 576 static void 577 crypto_adapter_enq_op_new_burst(struct prod_data *p) 578 { 579 const struct test_perf *t = p->t; 580 const struct evt_options *opt = t->opt; 581 582 struct rte_mbuf *m, *pkts_burst[MAX_PROD_ENQ_BURST_SIZE]; 583 struct rte_crypto_op *ops_burst[MAX_PROD_ENQ_BURST_SIZE]; 584 const uint32_t burst_size = opt->prod_enq_burst_sz; 585 uint8_t *result[MAX_PROD_ENQ_BURST_SIZE]; 586 const uint32_t nb_flows = t->nb_flows; 587 const uint64_t nb_pkts = t->nb_pkts; 588 uint16_t len, enq, nb_alloc, offset; 589 struct rte_mempool *pool = t->pool; 590 uint16_t qp_id = p->ca.cdev_qp_id; 591 uint8_t cdev_id = p->ca.cdev_id; 592 uint64_t alloc_failures = 0; 593 uint32_t flow_counter = 0; 594 uint64_t count = 0; 595 uint32_t i; 596 597 if (opt->verbose_level > 1) 598 printf("%s(): lcore %d queue %d cdev_id %u cdev_qp_id %u\n", 599 __func__, rte_lcore_id(), p->queue_id, p->ca.cdev_id, 600 p->ca.cdev_qp_id); 601 602 offset = sizeof(struct perf_elt); 603 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 604 605 while (count < nb_pkts && t->done == false) { 606 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 607 struct rte_crypto_sym_op *sym_op; 608 int ret; 609 610 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 611 RTE_CRYPTO_OP_TYPE_SYMMETRIC, ops_burst, burst_size); 612 if (unlikely(nb_alloc != burst_size)) { 613 alloc_failures++; 614 continue; 615 } 616 617 ret = rte_pktmbuf_alloc_bulk(pool, pkts_burst, burst_size); 618 if (unlikely(ret != 0)) { 619 alloc_failures++; 620 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 621 continue; 622 } 623 624 for (i = 0; i < burst_size; i++) { 625 m = pkts_burst[i]; 626 rte_pktmbuf_append(m, len); 627 sym_op = ops_burst[i]->sym; 628 sym_op->m_src = m; 629 sym_op->cipher.data.offset = offset; 630 sym_op->cipher.data.length = len - offset; 631 rte_crypto_op_attach_sym_session(ops_burst[i], 632 p->ca.crypto_sess[flow_counter++ % nb_flows]); 633 } 634 } else { 635 struct rte_crypto_asym_op *asym_op; 636 637 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 638 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, ops_burst, burst_size); 639 if (unlikely(nb_alloc != burst_size)) { 640 alloc_failures++; 641 continue; 642 } 643 644 if (rte_mempool_get_bulk(pool, (void **)result, burst_size)) { 645 alloc_failures++; 646 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 647 continue; 648 } 649 650 for (i = 0; i < burst_size; i++) { 651 asym_op = ops_burst[i]->asym; 652 asym_op->modex.base.data = modex_test_case.base.data; 653 asym_op->modex.base.length = modex_test_case.base.len; 654 asym_op->modex.result.data = result[i]; 655 asym_op->modex.result.length = modex_test_case.result_len; 656 rte_crypto_op_attach_asym_session(ops_burst[i], 657 p->ca.crypto_sess[flow_counter++ % nb_flows]); 658 } 659 } 660 661 enq = 0; 662 while (!t->done) { 663 enq += rte_cryptodev_enqueue_burst(cdev_id, qp_id, ops_burst + enq, 664 burst_size - enq); 665 if (enq == burst_size) 666 break; 667 } 668 669 count += burst_size; 670 } 671 672 if (opt->verbose_level > 1 && alloc_failures) 673 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 674 __func__, rte_lcore_id(), alloc_failures); 675 } 676 677 static void 678 crypto_adapter_enq_op_fwd_burst(struct prod_data *p) 679 { 680 const struct test_perf *t = p->t; 681 const struct evt_options *opt = t->opt; 682 683 struct rte_mbuf *m, *pkts_burst[MAX_PROD_ENQ_BURST_SIZE]; 684 struct rte_crypto_op *ops_burst[MAX_PROD_ENQ_BURST_SIZE]; 685 const uint32_t burst_size = opt->prod_enq_burst_sz; 686 struct rte_event ev[MAX_PROD_ENQ_BURST_SIZE]; 687 uint8_t *result[MAX_PROD_ENQ_BURST_SIZE]; 688 const uint32_t nb_flows = t->nb_flows; 689 const uint64_t nb_pkts = t->nb_pkts; 690 uint16_t len, enq, nb_alloc, offset; 691 struct rte_mempool *pool = t->pool; 692 const uint8_t dev_id = p->dev_id; 693 const uint8_t port = p->port_id; 694 uint64_t alloc_failures = 0; 695 uint32_t flow_counter = 0; 696 uint64_t count = 0; 697 uint32_t i; 698 699 if (opt->verbose_level > 1) 700 printf("%s(): lcore %d port %d queue %d cdev_id %u cdev_qp_id %u\n", 701 __func__, rte_lcore_id(), port, p->queue_id, 702 p->ca.cdev_id, p->ca.cdev_qp_id); 703 704 offset = sizeof(struct perf_elt); 705 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 706 707 for (i = 0; i < burst_size; i++) { 708 ev[i].event = 0; 709 ev[i].op = RTE_EVENT_OP_NEW; 710 ev[i].queue_id = p->queue_id; 711 ev[i].sched_type = RTE_SCHED_TYPE_ATOMIC; 712 ev[i].event_type = RTE_EVENT_TYPE_CPU; 713 } 714 715 while (count < nb_pkts && t->done == false) { 716 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 717 struct rte_crypto_sym_op *sym_op; 718 int ret; 719 720 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 721 RTE_CRYPTO_OP_TYPE_SYMMETRIC, ops_burst, burst_size); 722 if (unlikely(nb_alloc != burst_size)) { 723 alloc_failures++; 724 continue; 725 } 726 727 ret = rte_pktmbuf_alloc_bulk(pool, pkts_burst, burst_size); 728 if (unlikely(ret != 0)) { 729 alloc_failures++; 730 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 731 continue; 732 } 733 734 for (i = 0; i < burst_size; i++) { 735 m = pkts_burst[i]; 736 rte_pktmbuf_append(m, len); 737 sym_op = ops_burst[i]->sym; 738 sym_op->m_src = m; 739 sym_op->cipher.data.offset = offset; 740 sym_op->cipher.data.length = len - offset; 741 rte_crypto_op_attach_sym_session(ops_burst[i], 742 p->ca.crypto_sess[flow_counter++ % nb_flows]); 743 ev[i].event_ptr = ops_burst[i]; 744 } 745 } else { 746 struct rte_crypto_asym_op *asym_op; 747 748 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 749 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, ops_burst, burst_size); 750 if (unlikely(nb_alloc != burst_size)) { 751 alloc_failures++; 752 continue; 753 } 754 755 if (rte_mempool_get_bulk(pool, (void **)result, burst_size)) { 756 alloc_failures++; 757 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 758 continue; 759 } 760 761 for (i = 0; i < burst_size; i++) { 762 asym_op = ops_burst[i]->asym; 763 asym_op->modex.base.data = modex_test_case.base.data; 764 asym_op->modex.base.length = modex_test_case.base.len; 765 asym_op->modex.result.data = result[i]; 766 asym_op->modex.result.length = modex_test_case.result_len; 767 rte_crypto_op_attach_asym_session(ops_burst[i], 768 p->ca.crypto_sess[flow_counter++ % nb_flows]); 769 ev[i].event_ptr = ops_burst[i]; 770 } 771 } 772 773 enq = 0; 774 while (!t->done) { 775 enq += rte_event_crypto_adapter_enqueue(dev_id, port, ev + enq, 776 burst_size - enq); 777 if (enq == burst_size) 778 break; 779 } 780 781 count += burst_size; 782 } 783 784 if (opt->verbose_level > 1 && alloc_failures) 785 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 786 __func__, rte_lcore_id(), alloc_failures); 787 } 788 789 static inline int 790 perf_event_crypto_producer_burst(void *arg) 791 { 792 struct prod_data *p = arg; 793 struct evt_options *opt = p->t->opt; 794 795 if (opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) 796 crypto_adapter_enq_op_new_burst(p); 797 else 798 crypto_adapter_enq_op_fwd_burst(p); 799 800 return 0; 801 } 802 803 static int 804 perf_producer_wrapper(void *arg) 805 { 806 struct rte_event_dev_info dev_info; 807 struct prod_data *p = arg; 808 struct test_perf *t = p->t; 809 810 rte_event_dev_info_get(p->dev_id, &dev_info); 811 if (!t->opt->prod_enq_burst_sz) { 812 t->opt->prod_enq_burst_sz = MAX_PROD_ENQ_BURST_SIZE; 813 if (dev_info.max_event_port_enqueue_depth > 0 && 814 (uint32_t)dev_info.max_event_port_enqueue_depth < 815 t->opt->prod_enq_burst_sz) 816 t->opt->prod_enq_burst_sz = 817 dev_info.max_event_port_enqueue_depth; 818 } 819 820 /* In case of synthetic producer, launch perf_producer or 821 * perf_producer_burst depending on producer enqueue burst size 822 */ 823 if (t->opt->prod_type == EVT_PROD_TYPE_SYNT && 824 t->opt->prod_enq_burst_sz == 1) 825 return perf_producer(arg); 826 else if (t->opt->prod_type == EVT_PROD_TYPE_SYNT && 827 t->opt->prod_enq_burst_sz > 1) { 828 if (dev_info.max_event_port_enqueue_depth == 1) 829 evt_err("This event device does not support burst mode"); 830 else 831 return perf_producer_burst(arg); 832 } 833 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR && 834 !t->opt->timdev_use_burst) 835 return perf_event_timer_producer(arg); 836 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR && 837 t->opt->timdev_use_burst) 838 return perf_event_timer_producer_burst(arg); 839 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 840 if (t->opt->prod_enq_burst_sz > 1) 841 return perf_event_crypto_producer_burst(arg); 842 else 843 return perf_event_crypto_producer(arg); 844 } 845 return 0; 846 } 847 848 static inline uint64_t 849 processed_pkts(struct test_perf *t) 850 { 851 uint8_t i; 852 uint64_t total = 0; 853 854 for (i = 0; i < t->nb_workers; i++) 855 total += t->worker[i].processed_pkts; 856 857 return total; 858 } 859 860 static inline uint64_t 861 total_latency(struct test_perf *t) 862 { 863 uint8_t i; 864 uint64_t total = 0; 865 866 for (i = 0; i < t->nb_workers; i++) 867 total += t->worker[i].latency; 868 869 return total; 870 } 871 872 873 int 874 perf_launch_lcores(struct evt_test *test, struct evt_options *opt, 875 int (*worker)(void *)) 876 { 877 int ret, lcore_id; 878 struct test_perf *t = evt_test_priv(test); 879 880 int port_idx = 0; 881 /* launch workers */ 882 RTE_LCORE_FOREACH_WORKER(lcore_id) { 883 if (!(opt->wlcores[lcore_id])) 884 continue; 885 886 ret = rte_eal_remote_launch(worker, 887 &t->worker[port_idx], lcore_id); 888 if (ret) { 889 evt_err("failed to launch worker %d", lcore_id); 890 return ret; 891 } 892 port_idx++; 893 } 894 895 /* launch producers */ 896 RTE_LCORE_FOREACH_WORKER(lcore_id) { 897 if (!(opt->plcores[lcore_id])) 898 continue; 899 900 ret = rte_eal_remote_launch(perf_producer_wrapper, 901 &t->prod[port_idx], lcore_id); 902 if (ret) { 903 evt_err("failed to launch perf_producer %d", lcore_id); 904 return ret; 905 } 906 port_idx++; 907 } 908 909 const uint64_t total_pkts = t->outstand_pkts; 910 911 uint64_t dead_lock_cycles = rte_get_timer_cycles(); 912 int64_t dead_lock_remaining = total_pkts; 913 const uint64_t dead_lock_sample = rte_get_timer_hz() * 5; 914 915 uint64_t perf_cycles = rte_get_timer_cycles(); 916 int64_t perf_remaining = total_pkts; 917 const uint64_t perf_sample = rte_get_timer_hz(); 918 919 static float total_mpps; 920 static uint64_t samples; 921 922 const uint64_t freq_mhz = rte_get_timer_hz() / 1000000; 923 int64_t remaining = t->outstand_pkts - processed_pkts(t); 924 925 while (t->done == false) { 926 const uint64_t new_cycles = rte_get_timer_cycles(); 927 928 if ((new_cycles - perf_cycles) > perf_sample) { 929 const uint64_t latency = total_latency(t); 930 const uint64_t pkts = processed_pkts(t); 931 932 remaining = t->outstand_pkts - pkts; 933 float mpps = (float)(perf_remaining-remaining)/1000000; 934 935 perf_remaining = remaining; 936 perf_cycles = new_cycles; 937 total_mpps += mpps; 938 ++samples; 939 if (opt->fwd_latency && pkts > 0) { 940 printf(CLGRN"\r%.3f mpps avg %.3f mpps [avg fwd latency %.3f us] "CLNRM, 941 mpps, total_mpps/samples, 942 (float)(latency/pkts)/freq_mhz); 943 } else { 944 printf(CLGRN"\r%.3f mpps avg %.3f mpps"CLNRM, 945 mpps, total_mpps/samples); 946 } 947 fflush(stdout); 948 949 if (remaining <= 0) { 950 t->result = EVT_TEST_SUCCESS; 951 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 952 opt->prod_type == 953 EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 954 opt->prod_type == 955 EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 956 t->done = true; 957 break; 958 } 959 } 960 } 961 962 if (new_cycles - dead_lock_cycles > dead_lock_sample && 963 (opt->prod_type == EVT_PROD_TYPE_SYNT || 964 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 965 opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR)) { 966 remaining = t->outstand_pkts - processed_pkts(t); 967 if (dead_lock_remaining == remaining) { 968 rte_event_dev_dump(opt->dev_id, stdout); 969 evt_err("No schedules for seconds, deadlock"); 970 t->done = true; 971 break; 972 } 973 dead_lock_remaining = remaining; 974 dead_lock_cycles = new_cycles; 975 } 976 } 977 printf("\n"); 978 return 0; 979 } 980 981 static int 982 perf_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride, 983 struct rte_event_port_conf prod_conf) 984 { 985 int ret = 0; 986 uint16_t prod; 987 struct rte_event_eth_rx_adapter_queue_conf queue_conf; 988 989 memset(&queue_conf, 0, 990 sizeof(struct rte_event_eth_rx_adapter_queue_conf)); 991 queue_conf.ev.sched_type = opt->sched_type_list[0]; 992 RTE_ETH_FOREACH_DEV(prod) { 993 uint32_t cap; 994 995 ret = rte_event_eth_rx_adapter_caps_get(opt->dev_id, 996 prod, &cap); 997 if (ret) { 998 evt_err("failed to get event rx adapter[%d]" 999 " capabilities", 1000 opt->dev_id); 1001 return ret; 1002 } 1003 queue_conf.ev.queue_id = prod * stride; 1004 ret = rte_event_eth_rx_adapter_create(prod, opt->dev_id, 1005 &prod_conf); 1006 if (ret) { 1007 evt_err("failed to create rx adapter[%d]", prod); 1008 return ret; 1009 } 1010 ret = rte_event_eth_rx_adapter_queue_add(prod, prod, -1, 1011 &queue_conf); 1012 if (ret) { 1013 evt_err("failed to add rx queues to adapter[%d]", prod); 1014 return ret; 1015 } 1016 1017 if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) { 1018 uint32_t service_id; 1019 1020 rte_event_eth_rx_adapter_service_id_get(prod, 1021 &service_id); 1022 ret = evt_service_setup(service_id); 1023 if (ret) { 1024 evt_err("Failed to setup service core" 1025 " for Rx adapter\n"); 1026 return ret; 1027 } 1028 } 1029 } 1030 1031 return ret; 1032 } 1033 1034 static int 1035 perf_event_timer_adapter_setup(struct test_perf *t) 1036 { 1037 int i; 1038 int ret; 1039 struct rte_event_timer_adapter_info adapter_info; 1040 struct rte_event_timer_adapter *wl; 1041 uint8_t nb_producers = evt_nr_active_lcores(t->opt->plcores); 1042 uint8_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; 1043 1044 if (nb_producers == 1) 1045 flags |= RTE_EVENT_TIMER_ADAPTER_F_SP_PUT; 1046 1047 for (i = 0; i < t->opt->nb_timer_adptrs; i++) { 1048 struct rte_event_timer_adapter_conf config = { 1049 .event_dev_id = t->opt->dev_id, 1050 .timer_adapter_id = i, 1051 .timer_tick_ns = t->opt->timer_tick_nsec, 1052 .max_tmo_ns = t->opt->max_tmo_nsec, 1053 .nb_timers = t->opt->pool_sz, 1054 .flags = flags, 1055 }; 1056 1057 wl = rte_event_timer_adapter_create(&config); 1058 if (wl == NULL) { 1059 evt_err("failed to create event timer ring %d", i); 1060 return rte_errno; 1061 } 1062 1063 memset(&adapter_info, 0, 1064 sizeof(struct rte_event_timer_adapter_info)); 1065 rte_event_timer_adapter_get_info(wl, &adapter_info); 1066 t->opt->optm_timer_tick_nsec = adapter_info.min_resolution_ns; 1067 1068 if (!(adapter_info.caps & 1069 RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT)) { 1070 uint32_t service_id = -1U; 1071 1072 rte_event_timer_adapter_service_id_get(wl, 1073 &service_id); 1074 ret = evt_service_setup(service_id); 1075 if (ret) { 1076 evt_err("Failed to setup service core" 1077 " for timer adapter\n"); 1078 return ret; 1079 } 1080 rte_service_runstate_set(service_id, 1); 1081 } 1082 t->timer_adptr[i] = wl; 1083 } 1084 return 0; 1085 } 1086 1087 static int 1088 perf_event_crypto_adapter_setup(struct test_perf *t, struct prod_data *p) 1089 { 1090 struct rte_event_crypto_adapter_queue_conf conf; 1091 struct evt_options *opt = t->opt; 1092 uint32_t cap; 1093 int ret; 1094 1095 memset(&conf, 0, sizeof(conf)); 1096 1097 ret = rte_event_crypto_adapter_caps_get(p->dev_id, p->ca.cdev_id, &cap); 1098 if (ret) { 1099 evt_err("Failed to get crypto adapter capabilities"); 1100 return ret; 1101 } 1102 1103 if (((opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) && 1104 !(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW)) || 1105 ((opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_FORWARD) && 1106 !(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD))) { 1107 evt_err("crypto adapter %s mode unsupported\n", 1108 opt->crypto_adptr_mode ? "OP_FORWARD" : "OP_NEW"); 1109 return -ENOTSUP; 1110 } else if (!(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)) { 1111 evt_err("Storing crypto session not supported"); 1112 return -ENOTSUP; 1113 } 1114 1115 if (opt->ena_vector) { 1116 struct rte_event_crypto_adapter_vector_limits limits; 1117 1118 if (!(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR)) { 1119 evt_err("Crypto adapter doesn't support event vector"); 1120 return -EINVAL; 1121 } 1122 1123 ret = rte_event_crypto_adapter_vector_limits_get(p->dev_id, p->ca.cdev_id, &limits); 1124 if (ret) { 1125 evt_err("Failed to get crypto adapter's vector limits"); 1126 return ret; 1127 } 1128 1129 if (opt->vector_size < limits.min_sz || opt->vector_size > limits.max_sz) { 1130 evt_err("Vector size [%d] not within limits max[%d] min[%d]", 1131 opt->vector_size, limits.max_sz, limits.min_sz); 1132 return -EINVAL; 1133 } 1134 1135 if (limits.log2_sz && !rte_is_power_of_2(opt->vector_size)) { 1136 evt_err("Vector size [%d] not power of 2", opt->vector_size); 1137 return -EINVAL; 1138 } 1139 1140 if (opt->vector_tmo_nsec > limits.max_timeout_ns || 1141 opt->vector_tmo_nsec < limits.min_timeout_ns) { 1142 evt_err("Vector timeout [%" PRIu64 "] not within limits " 1143 "max[%" PRIu64 "] min[%" PRIu64 "]", 1144 opt->vector_tmo_nsec, limits.max_timeout_ns, limits.min_timeout_ns); 1145 return -EINVAL; 1146 } 1147 1148 conf.vector_mp = t->ca_vector_pool; 1149 conf.vector_sz = opt->vector_size; 1150 conf.vector_timeout_ns = opt->vector_tmo_nsec; 1151 conf.flags |= RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR; 1152 } 1153 1154 if (cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { 1155 conf.ev.sched_type = RTE_SCHED_TYPE_ATOMIC; 1156 conf.ev.queue_id = p->queue_id; 1157 } 1158 1159 ret = rte_event_crypto_adapter_queue_pair_add( 1160 TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id, &conf); 1161 1162 return ret; 1163 } 1164 1165 static void * 1166 cryptodev_sym_sess_create(struct prod_data *p, struct test_perf *t) 1167 { 1168 const struct rte_cryptodev_symmetric_capability *cap; 1169 struct rte_cryptodev_sym_capability_idx cap_idx; 1170 enum rte_crypto_cipher_algorithm cipher_algo; 1171 struct rte_crypto_sym_xform cipher_xform; 1172 struct evt_options *opt = t->opt; 1173 uint16_t key_size; 1174 uint16_t iv_size; 1175 void *sess; 1176 1177 cipher_algo = opt->crypto_cipher_alg; 1178 key_size = opt->crypto_cipher_key_sz; 1179 iv_size = opt->crypto_cipher_iv_sz; 1180 1181 /* Check if device supports the algorithm */ 1182 cap_idx.type = RTE_CRYPTO_SYM_XFORM_CIPHER; 1183 cap_idx.algo.cipher = cipher_algo; 1184 1185 cap = rte_cryptodev_sym_capability_get(p->ca.cdev_id, &cap_idx); 1186 if (cap == NULL) { 1187 evt_err("Device doesn't support cipher algorithm [%s]. Test Skipped\n", 1188 rte_cryptodev_get_cipher_algo_string(cipher_algo)); 1189 return NULL; 1190 } 1191 1192 /* Check if device supports key size and IV size */ 1193 if (rte_cryptodev_sym_capability_check_cipher(cap, key_size, 1194 iv_size) < 0) { 1195 evt_err("Device doesn't support cipher configuration:\n" 1196 "cipher algo [%s], key sz [%d], iv sz [%d]. Test Skipped\n", 1197 rte_cryptodev_get_cipher_algo_string(cipher_algo), key_size, iv_size); 1198 return NULL; 1199 } 1200 1201 cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER; 1202 cipher_xform.cipher.algo = cipher_algo; 1203 cipher_xform.cipher.key.data = opt->crypto_cipher_key; 1204 cipher_xform.cipher.key.length = key_size; 1205 cipher_xform.cipher.iv.length = iv_size; 1206 cipher_xform.cipher.iv.offset = IV_OFFSET; 1207 cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT; 1208 cipher_xform.next = NULL; 1209 1210 sess = rte_cryptodev_sym_session_create(p->ca.cdev_id, &cipher_xform, 1211 t->ca_sess_pool); 1212 if (sess == NULL) { 1213 evt_err("Failed to create sym session"); 1214 return NULL; 1215 } 1216 1217 return sess; 1218 } 1219 1220 static void * 1221 cryptodev_asym_sess_create(struct prod_data *p, struct test_perf *t) 1222 { 1223 const struct rte_cryptodev_asymmetric_xform_capability *capability; 1224 struct rte_cryptodev_asym_capability_idx cap_idx; 1225 struct rte_crypto_asym_xform xform; 1226 void *sess; 1227 1228 xform.next = NULL; 1229 xform.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX; 1230 cap_idx.type = xform.xform_type; 1231 capability = rte_cryptodev_asym_capability_get(p->ca.cdev_id, &cap_idx); 1232 if (capability == NULL) { 1233 evt_err("Device doesn't support MODEX. Test Skipped\n"); 1234 return NULL; 1235 } 1236 1237 xform.modex.modulus.data = modex_test_case.modulus.data; 1238 xform.modex.modulus.length = modex_test_case.modulus.len; 1239 xform.modex.exponent.data = modex_test_case.exponent.data; 1240 xform.modex.exponent.length = modex_test_case.exponent.len; 1241 1242 if (rte_cryptodev_asym_session_create(p->ca.cdev_id, &xform, 1243 t->ca_asym_sess_pool, &sess)) { 1244 evt_err("Failed to create asym session"); 1245 return NULL; 1246 } 1247 1248 return sess; 1249 } 1250 1251 int 1252 perf_event_dev_port_setup(struct evt_test *test, struct evt_options *opt, 1253 uint8_t stride, uint8_t nb_queues, 1254 const struct rte_event_port_conf *port_conf) 1255 { 1256 struct test_perf *t = evt_test_priv(test); 1257 uint16_t port, prod; 1258 int ret = -1; 1259 1260 /* setup one port per worker, linking to all queues */ 1261 for (port = 0; port < evt_nr_active_lcores(opt->wlcores); 1262 port++) { 1263 struct worker_data *w = &t->worker[port]; 1264 1265 w->dev_id = opt->dev_id; 1266 w->port_id = port; 1267 w->t = t; 1268 w->processed_pkts = 0; 1269 w->latency = 0; 1270 1271 struct rte_event_port_conf conf = *port_conf; 1272 conf.event_port_cfg |= RTE_EVENT_PORT_CFG_HINT_WORKER; 1273 1274 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1275 if (ret) { 1276 evt_err("failed to setup port %d", port); 1277 return ret; 1278 } 1279 1280 ret = rte_event_port_link(opt->dev_id, port, NULL, NULL, 0); 1281 if (ret != nb_queues) { 1282 evt_err("failed to link all queues to port %d", port); 1283 return -EINVAL; 1284 } 1285 } 1286 1287 /* port for producers, no links */ 1288 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1289 for ( ; port < perf_nb_event_ports(opt); port++) { 1290 struct prod_data *p = &t->prod[port]; 1291 p->t = t; 1292 } 1293 1294 struct rte_event_port_conf conf = *port_conf; 1295 conf.event_port_cfg |= RTE_EVENT_PORT_CFG_HINT_PRODUCER; 1296 1297 ret = perf_event_rx_adapter_setup(opt, stride, conf); 1298 if (ret) 1299 return ret; 1300 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1301 prod = 0; 1302 for ( ; port < perf_nb_event_ports(opt); port++) { 1303 struct prod_data *p = &t->prod[port]; 1304 p->queue_id = prod * stride; 1305 p->t = t; 1306 prod++; 1307 } 1308 1309 ret = perf_event_timer_adapter_setup(t); 1310 if (ret) 1311 return ret; 1312 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 1313 struct rte_event_port_conf conf = *port_conf; 1314 uint8_t cdev_id = 0; 1315 uint16_t qp_id = 0; 1316 1317 ret = rte_event_crypto_adapter_create(TEST_PERF_CA_ID, 1318 opt->dev_id, &conf, 0); 1319 if (ret) { 1320 evt_err("Failed to create crypto adapter"); 1321 return ret; 1322 } 1323 1324 prod = 0; 1325 for (; port < perf_nb_event_ports(opt); port++) { 1326 union rte_event_crypto_metadata m_data; 1327 struct prod_data *p = &t->prod[port]; 1328 uint32_t flow_id; 1329 1330 if (qp_id == rte_cryptodev_queue_pair_count(cdev_id)) { 1331 cdev_id++; 1332 qp_id = 0; 1333 } 1334 1335 p->dev_id = opt->dev_id; 1336 p->port_id = port; 1337 p->queue_id = prod * stride; 1338 p->ca.cdev_id = cdev_id; 1339 p->ca.cdev_qp_id = qp_id; 1340 p->ca.crypto_sess = rte_zmalloc_socket( 1341 NULL, sizeof(void *) * t->nb_flows, 1342 RTE_CACHE_LINE_SIZE, opt->socket_id); 1343 p->t = t; 1344 1345 ret = perf_event_crypto_adapter_setup(t, p); 1346 if (ret) 1347 return ret; 1348 1349 m_data.request_info.cdev_id = p->ca.cdev_id; 1350 m_data.request_info.queue_pair_id = p->ca.cdev_qp_id; 1351 m_data.response_info.sched_type = RTE_SCHED_TYPE_ATOMIC; 1352 m_data.response_info.queue_id = p->queue_id; 1353 1354 for (flow_id = 0; flow_id < t->nb_flows; flow_id++) { 1355 m_data.response_info.flow_id = flow_id; 1356 if (opt->crypto_op_type == 1357 RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 1358 void *sess; 1359 1360 sess = cryptodev_sym_sess_create(p, t); 1361 if (sess == NULL) 1362 return -ENOMEM; 1363 1364 ret = rte_cryptodev_session_event_mdata_set( 1365 cdev_id, 1366 sess, 1367 RTE_CRYPTO_OP_TYPE_SYMMETRIC, 1368 RTE_CRYPTO_OP_WITH_SESSION, 1369 &m_data, sizeof(m_data)); 1370 if (ret) 1371 return ret; 1372 p->ca.crypto_sess[flow_id] = sess; 1373 } else { 1374 void *sess; 1375 1376 sess = cryptodev_asym_sess_create(p, t); 1377 if (sess == NULL) 1378 return -ENOMEM; 1379 ret = rte_cryptodev_session_event_mdata_set( 1380 cdev_id, 1381 sess, 1382 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, 1383 RTE_CRYPTO_OP_WITH_SESSION, 1384 &m_data, sizeof(m_data)); 1385 if (ret) 1386 return ret; 1387 p->ca.crypto_sess[flow_id] = sess; 1388 } 1389 } 1390 1391 conf.event_port_cfg |= 1392 RTE_EVENT_PORT_CFG_HINT_PRODUCER | 1393 RTE_EVENT_PORT_CFG_HINT_CONSUMER; 1394 1395 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1396 if (ret) { 1397 evt_err("failed to setup port %d", port); 1398 return ret; 1399 } 1400 1401 qp_id++; 1402 prod++; 1403 } 1404 } else { 1405 prod = 0; 1406 for ( ; port < perf_nb_event_ports(opt); port++) { 1407 struct prod_data *p = &t->prod[port]; 1408 1409 p->dev_id = opt->dev_id; 1410 p->port_id = port; 1411 p->queue_id = prod * stride; 1412 p->t = t; 1413 1414 struct rte_event_port_conf conf = *port_conf; 1415 conf.event_port_cfg |= 1416 RTE_EVENT_PORT_CFG_HINT_PRODUCER | 1417 RTE_EVENT_PORT_CFG_HINT_CONSUMER; 1418 1419 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1420 if (ret) { 1421 evt_err("failed to setup port %d", port); 1422 return ret; 1423 } 1424 prod++; 1425 } 1426 } 1427 1428 return ret; 1429 } 1430 1431 int 1432 perf_opt_check(struct evt_options *opt, uint64_t nb_queues) 1433 { 1434 unsigned int lcores; 1435 1436 /* N producer + N worker + main when producer cores are used 1437 * Else N worker + main when Rx adapter is used 1438 */ 1439 lcores = opt->prod_type == EVT_PROD_TYPE_SYNT ? 3 : 2; 1440 1441 if (rte_lcore_count() < lcores) { 1442 evt_err("test need minimum %d lcores", lcores); 1443 return -1; 1444 } 1445 1446 /* Validate worker lcores */ 1447 if (evt_lcores_has_overlap(opt->wlcores, rte_get_main_lcore())) { 1448 evt_err("worker lcores overlaps with main lcore"); 1449 return -1; 1450 } 1451 if (evt_lcores_has_overlap_multi(opt->wlcores, opt->plcores)) { 1452 evt_err("worker lcores overlaps producer lcores"); 1453 return -1; 1454 } 1455 if (evt_has_disabled_lcore(opt->wlcores)) { 1456 evt_err("one or more workers lcores are not enabled"); 1457 return -1; 1458 } 1459 if (!evt_has_active_lcore(opt->wlcores)) { 1460 evt_err("minimum one worker is required"); 1461 return -1; 1462 } 1463 1464 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 1465 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 1466 opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 1467 /* Validate producer lcores */ 1468 if (evt_lcores_has_overlap(opt->plcores, 1469 rte_get_main_lcore())) { 1470 evt_err("producer lcores overlaps with main lcore"); 1471 return -1; 1472 } 1473 if (evt_has_disabled_lcore(opt->plcores)) { 1474 evt_err("one or more producer lcores are not enabled"); 1475 return -1; 1476 } 1477 if (!evt_has_active_lcore(opt->plcores)) { 1478 evt_err("minimum one producer is required"); 1479 return -1; 1480 } 1481 } 1482 1483 if (evt_has_invalid_stage(opt)) 1484 return -1; 1485 1486 if (evt_has_invalid_sched_type(opt)) 1487 return -1; 1488 1489 if (nb_queues > EVT_MAX_QUEUES) { 1490 evt_err("number of queues exceeds %d", EVT_MAX_QUEUES); 1491 return -1; 1492 } 1493 if (perf_nb_event_ports(opt) > EVT_MAX_PORTS) { 1494 evt_err("number of ports exceeds %d", EVT_MAX_PORTS); 1495 return -1; 1496 } 1497 1498 /* Fixups */ 1499 if ((opt->nb_stages == 1 && 1500 opt->prod_type != EVT_PROD_TYPE_EVENT_TIMER_ADPTR) && 1501 opt->fwd_latency) { 1502 evt_info("fwd_latency is valid when nb_stages > 1, disabling"); 1503 opt->fwd_latency = 0; 1504 } 1505 1506 if (opt->fwd_latency && !opt->q_priority) { 1507 evt_info("enabled queue priority for latency measurement"); 1508 opt->q_priority = 1; 1509 } 1510 if (opt->nb_pkts == 0) 1511 opt->nb_pkts = INT64_MAX/evt_nr_active_lcores(opt->plcores); 1512 1513 return 0; 1514 } 1515 1516 void 1517 perf_opt_dump(struct evt_options *opt, uint8_t nb_queues) 1518 { 1519 evt_dump("nb_prod_lcores", "%d", evt_nr_active_lcores(opt->plcores)); 1520 evt_dump_producer_lcores(opt); 1521 evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores)); 1522 evt_dump_worker_lcores(opt); 1523 evt_dump_nb_stages(opt); 1524 evt_dump("nb_evdev_ports", "%d", perf_nb_event_ports(opt)); 1525 evt_dump("nb_evdev_queues", "%d", nb_queues); 1526 evt_dump_queue_priority(opt); 1527 evt_dump_sched_type_list(opt); 1528 evt_dump_producer_type(opt); 1529 evt_dump("prod_enq_burst_sz", "%d", opt->prod_enq_burst_sz); 1530 } 1531 1532 static void 1533 perf_event_port_flush(uint8_t dev_id __rte_unused, struct rte_event ev, 1534 void *args) 1535 { 1536 rte_mempool_put(args, ev.event_ptr); 1537 } 1538 1539 void 1540 perf_worker_cleanup(struct rte_mempool *const pool, uint8_t dev_id, 1541 uint8_t port_id, struct rte_event events[], uint16_t nb_enq, 1542 uint16_t nb_deq) 1543 { 1544 int i; 1545 1546 if (nb_deq) { 1547 for (i = nb_enq; i < nb_deq; i++) 1548 rte_mempool_put(pool, events[i].event_ptr); 1549 1550 for (i = 0; i < nb_deq; i++) 1551 events[i].op = RTE_EVENT_OP_RELEASE; 1552 rte_event_enqueue_burst(dev_id, port_id, events, nb_deq); 1553 } 1554 rte_event_port_quiesce(dev_id, port_id, perf_event_port_flush, pool); 1555 } 1556 1557 void 1558 perf_eventdev_destroy(struct evt_test *test, struct evt_options *opt) 1559 { 1560 int i; 1561 struct test_perf *t = evt_test_priv(test); 1562 1563 if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1564 for (i = 0; i < opt->nb_timer_adptrs; i++) 1565 rte_event_timer_adapter_stop(t->timer_adptr[i]); 1566 } 1567 rte_event_dev_stop(opt->dev_id); 1568 rte_event_dev_close(opt->dev_id); 1569 } 1570 1571 static inline void 1572 perf_elt_init(struct rte_mempool *mp, void *arg __rte_unused, 1573 void *obj, unsigned i __rte_unused) 1574 { 1575 memset(obj, 0, mp->elt_size); 1576 } 1577 1578 #define NB_RX_DESC 128 1579 #define NB_TX_DESC 512 1580 int 1581 perf_ethdev_setup(struct evt_test *test, struct evt_options *opt) 1582 { 1583 uint16_t i; 1584 int ret; 1585 struct test_perf *t = evt_test_priv(test); 1586 struct rte_eth_conf port_conf = { 1587 .rxmode = { 1588 .mq_mode = RTE_ETH_MQ_RX_RSS, 1589 }, 1590 .rx_adv_conf = { 1591 .rss_conf = { 1592 .rss_key = NULL, 1593 .rss_hf = RTE_ETH_RSS_IP, 1594 }, 1595 }, 1596 }; 1597 1598 if (opt->prod_type != EVT_PROD_TYPE_ETH_RX_ADPTR) 1599 return 0; 1600 1601 if (!rte_eth_dev_count_avail()) { 1602 evt_err("No ethernet ports found."); 1603 return -ENODEV; 1604 } 1605 1606 RTE_ETH_FOREACH_DEV(i) { 1607 struct rte_eth_dev_info dev_info; 1608 struct rte_eth_conf local_port_conf = port_conf; 1609 1610 ret = rte_eth_dev_info_get(i, &dev_info); 1611 if (ret != 0) { 1612 evt_err("Error during getting device (port %u) info: %s\n", 1613 i, strerror(-ret)); 1614 return ret; 1615 } 1616 1617 local_port_conf.rx_adv_conf.rss_conf.rss_hf &= 1618 dev_info.flow_type_rss_offloads; 1619 if (local_port_conf.rx_adv_conf.rss_conf.rss_hf != 1620 port_conf.rx_adv_conf.rss_conf.rss_hf) { 1621 evt_info("Port %u modified RSS hash function based on hardware support," 1622 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 1623 i, 1624 port_conf.rx_adv_conf.rss_conf.rss_hf, 1625 local_port_conf.rx_adv_conf.rss_conf.rss_hf); 1626 } 1627 1628 if (rte_eth_dev_configure(i, 1, 1, &local_port_conf) < 0) { 1629 evt_err("Failed to configure eth port [%d]", i); 1630 return -EINVAL; 1631 } 1632 1633 if (rte_eth_rx_queue_setup(i, 0, NB_RX_DESC, 1634 rte_socket_id(), NULL, t->pool) < 0) { 1635 evt_err("Failed to setup eth port [%d] rx_queue: %d.", 1636 i, 0); 1637 return -EINVAL; 1638 } 1639 1640 if (rte_eth_tx_queue_setup(i, 0, NB_TX_DESC, 1641 rte_socket_id(), NULL) < 0) { 1642 evt_err("Failed to setup eth port [%d] tx_queue: %d.", 1643 i, 0); 1644 return -EINVAL; 1645 } 1646 1647 ret = rte_eth_promiscuous_enable(i); 1648 if (ret != 0) { 1649 evt_err("Failed to enable promiscuous mode for eth port [%d]: %s", 1650 i, rte_strerror(-ret)); 1651 return ret; 1652 } 1653 } 1654 1655 return 0; 1656 } 1657 1658 void 1659 perf_ethdev_rx_stop(struct evt_test *test, struct evt_options *opt) 1660 { 1661 uint16_t i; 1662 RTE_SET_USED(test); 1663 1664 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1665 RTE_ETH_FOREACH_DEV(i) { 1666 rte_event_eth_rx_adapter_stop(i); 1667 rte_event_eth_rx_adapter_queue_del(i, i, -1); 1668 rte_eth_dev_rx_queue_stop(i, 0); 1669 } 1670 } 1671 } 1672 1673 void 1674 perf_ethdev_destroy(struct evt_test *test, struct evt_options *opt) 1675 { 1676 uint16_t i; 1677 RTE_SET_USED(test); 1678 1679 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1680 RTE_ETH_FOREACH_DEV(i) { 1681 rte_event_eth_tx_adapter_stop(i); 1682 rte_event_eth_tx_adapter_queue_del(i, i, -1); 1683 rte_eth_dev_tx_queue_stop(i, 0); 1684 rte_eth_dev_stop(i); 1685 } 1686 } 1687 } 1688 1689 int 1690 perf_cryptodev_setup(struct evt_test *test, struct evt_options *opt) 1691 { 1692 uint8_t cdev_count, cdev_id, nb_plcores, nb_qps; 1693 struct test_perf *t = evt_test_priv(test); 1694 unsigned int max_session_size; 1695 uint32_t nb_sessions; 1696 int ret; 1697 1698 if (opt->prod_type != EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 1699 return 0; 1700 1701 cdev_count = rte_cryptodev_count(); 1702 if (cdev_count == 0) { 1703 evt_err("No crypto devices available\n"); 1704 return -ENODEV; 1705 } 1706 1707 t->ca_op_pool = rte_crypto_op_pool_create( 1708 "crypto_op_pool", opt->crypto_op_type, opt->pool_sz, 1709 128, sizeof(union rte_event_crypto_metadata) + EVT_CRYPTO_MAX_IV_SIZE, 1710 rte_socket_id()); 1711 if (t->ca_op_pool == NULL) { 1712 evt_err("Failed to create crypto op pool"); 1713 return -ENOMEM; 1714 } 1715 1716 nb_sessions = evt_nr_active_lcores(opt->plcores) * t->nb_flows; 1717 t->ca_asym_sess_pool = rte_cryptodev_asym_session_pool_create( 1718 "ca_asym_sess_pool", nb_sessions, 0, 1719 sizeof(union rte_event_crypto_metadata), SOCKET_ID_ANY); 1720 if (t->ca_asym_sess_pool == NULL) { 1721 evt_err("Failed to create sym session pool"); 1722 ret = -ENOMEM; 1723 goto err; 1724 } 1725 1726 max_session_size = 0; 1727 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 1728 unsigned int session_size; 1729 1730 session_size = 1731 rte_cryptodev_sym_get_private_session_size(cdev_id); 1732 if (session_size > max_session_size) 1733 max_session_size = session_size; 1734 } 1735 1736 t->ca_sess_pool = rte_cryptodev_sym_session_pool_create( 1737 "ca_sess_pool", nb_sessions, max_session_size, 0, 1738 sizeof(union rte_event_crypto_metadata), SOCKET_ID_ANY); 1739 if (t->ca_sess_pool == NULL) { 1740 evt_err("Failed to create sym session pool"); 1741 ret = -ENOMEM; 1742 goto err; 1743 } 1744 1745 if (opt->ena_vector) { 1746 unsigned int nb_elem = (opt->pool_sz / opt->vector_size) * 2; 1747 nb_elem = RTE_MAX(512U, nb_elem); 1748 nb_elem += evt_nr_active_lcores(opt->wlcores) * 32; 1749 t->ca_vector_pool = rte_event_vector_pool_create("vector_pool", nb_elem, 32, 1750 opt->vector_size, opt->socket_id); 1751 if (t->ca_vector_pool == NULL) { 1752 evt_err("Failed to create event vector pool"); 1753 ret = -ENOMEM; 1754 goto err; 1755 } 1756 } 1757 1758 /* 1759 * Calculate number of needed queue pairs, based on the amount of 1760 * available number of logical cores and crypto devices. For instance, 1761 * if there are 4 cores and 2 crypto devices, 2 queue pairs will be set 1762 * up per device. 1763 */ 1764 nb_plcores = evt_nr_active_lcores(opt->plcores); 1765 nb_qps = (nb_plcores % cdev_count) ? (nb_plcores / cdev_count) + 1 : 1766 nb_plcores / cdev_count; 1767 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 1768 struct rte_cryptodev_qp_conf qp_conf; 1769 struct rte_cryptodev_config conf; 1770 struct rte_cryptodev_info info; 1771 int qp_id; 1772 1773 rte_cryptodev_info_get(cdev_id, &info); 1774 if (nb_qps > info.max_nb_queue_pairs) { 1775 evt_err("Not enough queue pairs per cryptodev (%u)", 1776 nb_qps); 1777 ret = -EINVAL; 1778 goto err; 1779 } 1780 1781 conf.nb_queue_pairs = nb_qps; 1782 conf.socket_id = SOCKET_ID_ANY; 1783 conf.ff_disable = RTE_CRYPTODEV_FF_SECURITY; 1784 1785 ret = rte_cryptodev_configure(cdev_id, &conf); 1786 if (ret) { 1787 evt_err("Failed to configure cryptodev (%u)", cdev_id); 1788 goto err; 1789 } 1790 1791 qp_conf.nb_descriptors = NB_CRYPTODEV_DESCRIPTORS; 1792 qp_conf.mp_session = t->ca_sess_pool; 1793 1794 for (qp_id = 0; qp_id < conf.nb_queue_pairs; qp_id++) { 1795 ret = rte_cryptodev_queue_pair_setup( 1796 cdev_id, qp_id, &qp_conf, 1797 rte_cryptodev_socket_id(cdev_id)); 1798 if (ret) { 1799 evt_err("Failed to setup queue pairs on cryptodev %u\n", 1800 cdev_id); 1801 goto err; 1802 } 1803 } 1804 } 1805 1806 return 0; 1807 err: 1808 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) 1809 rte_cryptodev_close(cdev_id); 1810 1811 rte_mempool_free(t->ca_op_pool); 1812 rte_mempool_free(t->ca_sess_pool); 1813 rte_mempool_free(t->ca_asym_sess_pool); 1814 rte_mempool_free(t->ca_vector_pool); 1815 1816 return ret; 1817 } 1818 1819 void 1820 perf_cryptodev_destroy(struct evt_test *test, struct evt_options *opt) 1821 { 1822 uint8_t cdev_id, cdev_count = rte_cryptodev_count(); 1823 struct test_perf *t = evt_test_priv(test); 1824 uint16_t port; 1825 1826 if (opt->prod_type != EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 1827 return; 1828 1829 for (port = t->nb_workers; port < perf_nb_event_ports(opt); port++) { 1830 void *sess; 1831 struct prod_data *p = &t->prod[port]; 1832 uint32_t flow_id; 1833 uint8_t cdev_id; 1834 1835 for (flow_id = 0; flow_id < t->nb_flows; flow_id++) { 1836 sess = p->ca.crypto_sess[flow_id]; 1837 cdev_id = p->ca.cdev_id; 1838 rte_cryptodev_sym_session_free(cdev_id, sess); 1839 } 1840 1841 rte_event_crypto_adapter_queue_pair_del( 1842 TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id); 1843 } 1844 1845 rte_event_crypto_adapter_free(TEST_PERF_CA_ID); 1846 1847 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 1848 rte_cryptodev_stop(cdev_id); 1849 rte_cryptodev_close(cdev_id); 1850 } 1851 1852 rte_mempool_free(t->ca_op_pool); 1853 rte_mempool_free(t->ca_sess_pool); 1854 rte_mempool_free(t->ca_asym_sess_pool); 1855 rte_mempool_free(t->ca_vector_pool); 1856 } 1857 1858 int 1859 perf_mempool_setup(struct evt_test *test, struct evt_options *opt) 1860 { 1861 struct test_perf *t = evt_test_priv(test); 1862 unsigned int cache_sz; 1863 1864 cache_sz = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, (opt->pool_sz / 1.5) / t->nb_workers); 1865 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 1866 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1867 t->pool = rte_mempool_create(test->name, /* mempool name */ 1868 opt->pool_sz, /* number of elements*/ 1869 sizeof(struct perf_elt), /* element size*/ 1870 cache_sz, /* cache size*/ 1871 0, NULL, NULL, 1872 perf_elt_init, /* obj constructor */ 1873 NULL, opt->socket_id, 0); /* flags */ 1874 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR && 1875 opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { 1876 t->pool = rte_mempool_create(test->name, /* mempool name */ 1877 opt->pool_sz, /* number of elements*/ 1878 sizeof(struct perf_elt) + modex_test_case.result_len, 1879 /* element size*/ 1880 cache_sz, /* cache size*/ 1881 0, NULL, NULL, 1882 NULL, /* obj constructor */ 1883 NULL, opt->socket_id, 0); /* flags */ 1884 } else { 1885 t->pool = rte_pktmbuf_pool_create(test->name, /* mempool name */ 1886 opt->pool_sz, /* number of elements*/ 1887 cache_sz, /* cache size*/ 1888 0, 1889 RTE_MBUF_DEFAULT_BUF_SIZE, 1890 opt->socket_id); /* flags */ 1891 } 1892 1893 if (t->pool == NULL) { 1894 evt_err("failed to create mempool"); 1895 return -ENOMEM; 1896 } 1897 1898 return 0; 1899 } 1900 1901 void 1902 perf_mempool_destroy(struct evt_test *test, struct evt_options *opt) 1903 { 1904 RTE_SET_USED(opt); 1905 struct test_perf *t = evt_test_priv(test); 1906 1907 rte_mempool_free(t->pool); 1908 } 1909 1910 int 1911 perf_test_setup(struct evt_test *test, struct evt_options *opt) 1912 { 1913 void *test_perf; 1914 1915 test_perf = rte_zmalloc_socket(test->name, sizeof(struct test_perf), 1916 RTE_CACHE_LINE_SIZE, opt->socket_id); 1917 if (test_perf == NULL) { 1918 evt_err("failed to allocate test_perf memory"); 1919 goto nomem; 1920 } 1921 test->test_priv = test_perf; 1922 1923 struct test_perf *t = evt_test_priv(test); 1924 1925 if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1926 t->outstand_pkts = opt->nb_timers * 1927 evt_nr_active_lcores(opt->plcores); 1928 t->nb_pkts = opt->nb_timers; 1929 } else { 1930 t->outstand_pkts = opt->nb_pkts * 1931 evt_nr_active_lcores(opt->plcores); 1932 t->nb_pkts = opt->nb_pkts; 1933 } 1934 1935 t->nb_workers = evt_nr_active_lcores(opt->wlcores); 1936 t->done = false; 1937 t->nb_flows = opt->nb_flows; 1938 t->result = EVT_TEST_FAILED; 1939 t->opt = opt; 1940 memcpy(t->sched_type_list, opt->sched_type_list, 1941 sizeof(opt->sched_type_list)); 1942 return 0; 1943 nomem: 1944 return -ENOMEM; 1945 } 1946 1947 void 1948 perf_test_destroy(struct evt_test *test, struct evt_options *opt) 1949 { 1950 RTE_SET_USED(opt); 1951 1952 rte_free(test->test_priv); 1953 } 1954