1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <math.h> 6 7 #include "test_perf_common.h" 8 9 #define NB_CRYPTODEV_DESCRIPTORS 4096 10 #define DATA_SIZE 512 11 #define IV_OFFSET (sizeof(struct rte_crypto_op) + \ 12 sizeof(struct rte_crypto_sym_op) + \ 13 sizeof(union rte_event_crypto_metadata)) 14 15 struct modex_test_data { 16 enum rte_crypto_asym_xform_type xform_type; 17 struct { 18 uint8_t data[DATA_SIZE]; 19 uint16_t len; 20 } base; 21 struct { 22 uint8_t data[DATA_SIZE]; 23 uint16_t len; 24 } exponent; 25 struct { 26 uint8_t data[DATA_SIZE]; 27 uint16_t len; 28 } modulus; 29 struct { 30 uint8_t data[DATA_SIZE]; 31 uint16_t len; 32 } reminder; 33 uint16_t result_len; 34 }; 35 36 static struct 37 modex_test_data modex_test_case = { 38 .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, 39 .base = { 40 .data = { 41 0xF8, 0xBA, 0x1A, 0x55, 0xD0, 0x2F, 0x85, 42 0xAE, 0x96, 0x7B, 0xB6, 0x2F, 0xB6, 0xCD, 43 0xA8, 0xEB, 0x7E, 0x78, 0xA0, 0x50 44 }, 45 .len = 20, 46 }, 47 .exponent = { 48 .data = { 49 0x01, 0x00, 0x01 50 }, 51 .len = 3, 52 }, 53 .reminder = { 54 .data = { 55 0x2C, 0x60, 0x75, 0x45, 0x98, 0x9D, 0xE0, 0x72, 56 0xA0, 0x9D, 0x3A, 0x9E, 0x03, 0x38, 0x73, 0x3C, 57 0x31, 0x83, 0x04, 0xFE, 0x75, 0x43, 0xE6, 0x17, 58 0x5C, 0x01, 0x29, 0x51, 0x69, 0x33, 0x62, 0x2D, 59 0x78, 0xBE, 0xAE, 0xC4, 0xBC, 0xDE, 0x7E, 0x2C, 60 0x77, 0x84, 0xF2, 0xC5, 0x14, 0xB5, 0x2F, 0xF7, 61 0xC5, 0x94, 0xEF, 0x86, 0x75, 0x75, 0xB5, 0x11, 62 0xE5, 0x0E, 0x0A, 0x29, 0x76, 0xE2, 0xEA, 0x32, 63 0x0E, 0x43, 0x77, 0x7E, 0x2C, 0x27, 0xAC, 0x3B, 64 0x86, 0xA5, 0xDB, 0xC9, 0x48, 0x40, 0xE8, 0x99, 65 0x9A, 0x0A, 0x3D, 0xD6, 0x74, 0xFA, 0x2E, 0x2E, 66 0x5B, 0xAF, 0x8C, 0x99, 0x44, 0x2A, 0x67, 0x38, 67 0x27, 0x41, 0x59, 0x9D, 0xB8, 0x51, 0xC9, 0xF7, 68 0x43, 0x61, 0x31, 0x6E, 0xF1, 0x25, 0x38, 0x7F, 69 0xAE, 0xC6, 0xD0, 0xBB, 0x29, 0x76, 0x3F, 0x46, 70 0x2E, 0x1B, 0xE4, 0x67, 0x71, 0xE3, 0x87, 0x5A 71 }, 72 .len = 128, 73 }, 74 .modulus = { 75 .data = { 76 0xb3, 0xa1, 0xaf, 0xb7, 0x13, 0x08, 0x00, 0x0a, 77 0x35, 0xdc, 0x2b, 0x20, 0x8d, 0xa1, 0xb5, 0xce, 78 0x47, 0x8a, 0xc3, 0x80, 0xf4, 0x7d, 0x4a, 0xa2, 79 0x62, 0xfd, 0x61, 0x7f, 0xb5, 0xa8, 0xde, 0x0a, 80 0x17, 0x97, 0xa0, 0xbf, 0xdf, 0x56, 0x5a, 0x3d, 81 0x51, 0x56, 0x4f, 0x70, 0x70, 0x3f, 0x63, 0x6a, 82 0x44, 0x5b, 0xad, 0x84, 0x0d, 0x3f, 0x27, 0x6e, 83 0x3b, 0x34, 0x91, 0x60, 0x14, 0xb9, 0xaa, 0x72, 84 0xfd, 0xa3, 0x64, 0xd2, 0x03, 0xa7, 0x53, 0x87, 85 0x9e, 0x88, 0x0b, 0xc1, 0x14, 0x93, 0x1a, 0x62, 86 0xff, 0xb1, 0x5d, 0x74, 0xcd, 0x59, 0x63, 0x18, 87 0x11, 0x3d, 0x4f, 0xba, 0x75, 0xd4, 0x33, 0x4e, 88 0x23, 0x6b, 0x7b, 0x57, 0x44, 0xe1, 0xd3, 0x03, 89 0x13, 0xa6, 0xf0, 0x8b, 0x60, 0xb0, 0x9e, 0xee, 90 0x75, 0x08, 0x9d, 0x71, 0x63, 0x13, 0xcb, 0xa6, 91 0x81, 0x92, 0x14, 0x03, 0x22, 0x2d, 0xde, 0x55 92 }, 93 .len = 128, 94 }, 95 .result_len = 128, 96 }; 97 98 int 99 perf_test_result(struct evt_test *test, struct evt_options *opt) 100 { 101 RTE_SET_USED(opt); 102 int i; 103 uint64_t total = 0; 104 struct test_perf *t = evt_test_priv(test); 105 106 printf("Packet distribution across worker cores :\n"); 107 for (i = 0; i < t->nb_workers; i++) 108 total += t->worker[i].processed_pkts; 109 for (i = 0; i < t->nb_workers; i++) 110 printf("Worker %d packets: "CLGRN"%"PRIx64" "CLNRM"percentage:" 111 CLGRN" %3.2f"CLNRM"\n", i, 112 t->worker[i].processed_pkts, 113 (((double)t->worker[i].processed_pkts)/total) 114 * 100); 115 116 return t->result; 117 } 118 119 static inline int 120 perf_producer(void *arg) 121 { 122 int i; 123 struct prod_data *p = arg; 124 struct test_perf *t = p->t; 125 struct evt_options *opt = t->opt; 126 const uint8_t dev_id = p->dev_id; 127 const uint8_t port = p->port_id; 128 struct rte_mempool *pool = t->pool; 129 const uint64_t nb_pkts = t->nb_pkts; 130 const uint32_t nb_flows = t->nb_flows; 131 uint32_t flow_counter = 0; 132 uint64_t count = 0; 133 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 134 uint8_t enable_fwd_latency; 135 struct rte_event ev; 136 137 enable_fwd_latency = opt->fwd_latency; 138 if (opt->verbose_level > 1) 139 printf("%s(): lcore %d dev_id %d port=%d queue %d\n", __func__, 140 rte_lcore_id(), dev_id, port, p->queue_id); 141 142 ev.event = 0; 143 ev.op = RTE_EVENT_OP_NEW; 144 ev.queue_id = p->queue_id; 145 ev.sched_type = t->opt->sched_type_list[0]; 146 ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 147 ev.event_type = RTE_EVENT_TYPE_CPU; 148 ev.sub_event_type = 0; /* stage 0 */ 149 150 while (count < nb_pkts && t->done == false) { 151 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 152 continue; 153 for (i = 0; i < BURST_SIZE; i++) { 154 ev.flow_id = flow_counter++ % nb_flows; 155 ev.event_ptr = m[i]; 156 if (enable_fwd_latency) 157 m[i]->timestamp = rte_get_timer_cycles(); 158 while (rte_event_enqueue_new_burst(dev_id, port, &ev, 159 1) != 1) { 160 if (t->done) 161 break; 162 rte_pause(); 163 if (enable_fwd_latency) 164 m[i]->timestamp = 165 rte_get_timer_cycles(); 166 } 167 } 168 count += BURST_SIZE; 169 } 170 171 return 0; 172 } 173 174 static inline int 175 perf_producer_burst(void *arg) 176 { 177 uint32_t i; 178 uint64_t timestamp; 179 struct prod_data *p = arg; 180 struct test_perf *t = p->t; 181 struct evt_options *opt = t->opt; 182 const uint8_t dev_id = p->dev_id; 183 const uint8_t port = p->port_id; 184 struct rte_mempool *pool = t->pool; 185 const uint64_t nb_pkts = t->nb_pkts; 186 const uint32_t nb_flows = t->nb_flows; 187 uint32_t flow_counter = 0; 188 uint16_t enq = 0; 189 uint64_t count = 0; 190 struct perf_elt *m[opt->prod_enq_burst_sz + 1]; 191 struct rte_event ev[opt->prod_enq_burst_sz + 1]; 192 uint32_t burst_size = opt->prod_enq_burst_sz; 193 uint8_t enable_fwd_latency; 194 195 enable_fwd_latency = opt->fwd_latency; 196 memset(m, 0, sizeof(*m) * (opt->prod_enq_burst_sz + 1)); 197 if (opt->verbose_level > 1) 198 printf("%s(): lcore %d dev_id %d port=%d queue %d\n", __func__, 199 rte_lcore_id(), dev_id, port, p->queue_id); 200 201 for (i = 0; i < burst_size; i++) { 202 ev[i].op = RTE_EVENT_OP_NEW; 203 ev[i].queue_id = p->queue_id; 204 ev[i].sched_type = t->opt->sched_type_list[0]; 205 ev[i].priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 206 ev[i].event_type = RTE_EVENT_TYPE_CPU; 207 ev[i].sub_event_type = 0; /* stage 0 */ 208 } 209 210 while (count < nb_pkts && t->done == false) { 211 if (rte_mempool_get_bulk(pool, (void **)m, burst_size) < 0) 212 continue; 213 timestamp = rte_get_timer_cycles(); 214 for (i = 0; i < burst_size; i++) { 215 ev[i].flow_id = flow_counter++ % nb_flows; 216 ev[i].event_ptr = m[i]; 217 if (enable_fwd_latency) 218 m[i]->timestamp = timestamp; 219 } 220 enq = rte_event_enqueue_new_burst(dev_id, port, ev, burst_size); 221 while (enq < burst_size) { 222 enq += rte_event_enqueue_new_burst( 223 dev_id, port, ev + enq, burst_size - enq); 224 if (t->done) 225 break; 226 rte_pause(); 227 if (enable_fwd_latency) { 228 timestamp = rte_get_timer_cycles(); 229 for (i = enq; i < burst_size; i++) 230 m[i]->timestamp = timestamp; 231 } 232 } 233 count += burst_size; 234 } 235 return 0; 236 } 237 238 static inline int 239 perf_event_timer_producer(void *arg) 240 { 241 int i; 242 struct prod_data *p = arg; 243 struct test_perf *t = p->t; 244 struct evt_options *opt = t->opt; 245 uint32_t flow_counter = 0; 246 uint64_t count = 0; 247 uint64_t arm_latency = 0; 248 const uint8_t nb_timer_adptrs = opt->nb_timer_adptrs; 249 const uint32_t nb_flows = t->nb_flows; 250 const uint64_t nb_timers = opt->nb_timers; 251 struct rte_mempool *pool = t->pool; 252 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 253 struct rte_event_timer_adapter **adptr = t->timer_adptr; 254 struct rte_event_timer tim; 255 uint64_t timeout_ticks = opt->expiry_nsec / opt->timer_tick_nsec; 256 257 memset(&tim, 0, sizeof(struct rte_event_timer)); 258 timeout_ticks = 259 opt->optm_timer_tick_nsec 260 ? ceil((double)(timeout_ticks * opt->timer_tick_nsec) / 261 opt->optm_timer_tick_nsec) 262 : timeout_ticks; 263 timeout_ticks += timeout_ticks ? 0 : 1; 264 tim.ev.event_type = RTE_EVENT_TYPE_TIMER; 265 tim.ev.op = RTE_EVENT_OP_NEW; 266 tim.ev.sched_type = t->opt->sched_type_list[0]; 267 tim.ev.queue_id = p->queue_id; 268 tim.ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 269 tim.state = RTE_EVENT_TIMER_NOT_ARMED; 270 tim.timeout_ticks = timeout_ticks; 271 272 if (opt->verbose_level > 1) 273 printf("%s(): lcore %d\n", __func__, rte_lcore_id()); 274 275 while (count < nb_timers && t->done == false) { 276 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 277 continue; 278 for (i = 0; i < BURST_SIZE; i++) { 279 rte_prefetch0(m[i + 1]); 280 m[i]->tim = tim; 281 m[i]->tim.ev.flow_id = flow_counter++ % nb_flows; 282 m[i]->tim.ev.event_ptr = m[i]; 283 m[i]->timestamp = rte_get_timer_cycles(); 284 while (rte_event_timer_arm_burst( 285 adptr[flow_counter % nb_timer_adptrs], 286 (struct rte_event_timer **)&m[i], 1) != 1) { 287 if (t->done) 288 break; 289 m[i]->timestamp = rte_get_timer_cycles(); 290 } 291 arm_latency += rte_get_timer_cycles() - m[i]->timestamp; 292 } 293 count += BURST_SIZE; 294 } 295 fflush(stdout); 296 rte_delay_ms(1000); 297 printf("%s(): lcore %d Average event timer arm latency = %.3f us\n", 298 __func__, rte_lcore_id(), 299 count ? (float)(arm_latency / count) / 300 (rte_get_timer_hz() / 1000000) : 0); 301 return 0; 302 } 303 304 static inline int 305 perf_event_timer_producer_burst(void *arg) 306 { 307 int i; 308 struct prod_data *p = arg; 309 struct test_perf *t = p->t; 310 struct evt_options *opt = t->opt; 311 uint32_t flow_counter = 0; 312 uint64_t count = 0; 313 uint64_t arm_latency = 0; 314 const uint8_t nb_timer_adptrs = opt->nb_timer_adptrs; 315 const uint32_t nb_flows = t->nb_flows; 316 const uint64_t nb_timers = opt->nb_timers; 317 struct rte_mempool *pool = t->pool; 318 struct perf_elt *m[BURST_SIZE + 1] = {NULL}; 319 struct rte_event_timer_adapter **adptr = t->timer_adptr; 320 struct rte_event_timer tim; 321 uint64_t timeout_ticks = opt->expiry_nsec / opt->timer_tick_nsec; 322 323 memset(&tim, 0, sizeof(struct rte_event_timer)); 324 timeout_ticks = 325 opt->optm_timer_tick_nsec 326 ? ceil((double)(timeout_ticks * opt->timer_tick_nsec) / 327 opt->optm_timer_tick_nsec) 328 : timeout_ticks; 329 timeout_ticks += timeout_ticks ? 0 : 1; 330 tim.ev.event_type = RTE_EVENT_TYPE_TIMER; 331 tim.ev.op = RTE_EVENT_OP_NEW; 332 tim.ev.sched_type = t->opt->sched_type_list[0]; 333 tim.ev.queue_id = p->queue_id; 334 tim.ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL; 335 tim.state = RTE_EVENT_TIMER_NOT_ARMED; 336 tim.timeout_ticks = timeout_ticks; 337 338 if (opt->verbose_level > 1) 339 printf("%s(): lcore %d\n", __func__, rte_lcore_id()); 340 341 while (count < nb_timers && t->done == false) { 342 if (rte_mempool_get_bulk(pool, (void **)m, BURST_SIZE) < 0) 343 continue; 344 for (i = 0; i < BURST_SIZE; i++) { 345 rte_prefetch0(m[i + 1]); 346 m[i]->tim = tim; 347 m[i]->tim.ev.flow_id = flow_counter++ % nb_flows; 348 m[i]->tim.ev.event_ptr = m[i]; 349 m[i]->timestamp = rte_get_timer_cycles(); 350 } 351 rte_event_timer_arm_tmo_tick_burst( 352 adptr[flow_counter % nb_timer_adptrs], 353 (struct rte_event_timer **)m, 354 tim.timeout_ticks, 355 BURST_SIZE); 356 arm_latency += rte_get_timer_cycles() - m[i - 1]->timestamp; 357 count += BURST_SIZE; 358 } 359 fflush(stdout); 360 rte_delay_ms(1000); 361 printf("%s(): lcore %d Average event timer arm latency = %.3f us\n", 362 __func__, rte_lcore_id(), 363 count ? (float)(arm_latency / count) / 364 (rte_get_timer_hz() / 1000000) : 0); 365 return 0; 366 } 367 368 static inline void 369 crypto_adapter_enq_op_new(struct prod_data *p) 370 { 371 struct test_perf *t = p->t; 372 const uint32_t nb_flows = t->nb_flows; 373 const uint64_t nb_pkts = t->nb_pkts; 374 struct rte_mempool *pool = t->pool; 375 uint16_t data_length, data_offset; 376 struct evt_options *opt = t->opt; 377 uint16_t qp_id = p->ca.cdev_qp_id; 378 uint8_t cdev_id = p->ca.cdev_id; 379 uint64_t alloc_failures = 0; 380 uint32_t flow_counter = 0; 381 struct rte_crypto_op *op; 382 uint16_t len, offset; 383 struct rte_mbuf *m; 384 uint64_t count = 0; 385 386 if (opt->verbose_level > 1) 387 printf("%s(): lcore %d queue %d cdev_id %u cdev_qp_id %u\n", 388 __func__, rte_lcore_id(), p->queue_id, p->ca.cdev_id, 389 p->ca.cdev_qp_id); 390 391 offset = sizeof(struct perf_elt); 392 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 393 394 if (opt->crypto_cipher_bit_mode) { 395 data_offset = offset << 3; 396 data_length = (len - offset) << 3; 397 } else { 398 data_offset = offset; 399 data_length = len - offset; 400 } 401 402 while (count < nb_pkts && t->done == false) { 403 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 404 struct rte_crypto_sym_op *sym_op; 405 406 op = rte_crypto_op_alloc(t->ca_op_pool, 407 RTE_CRYPTO_OP_TYPE_SYMMETRIC); 408 if (unlikely(op == NULL)) { 409 alloc_failures++; 410 continue; 411 } 412 413 m = rte_pktmbuf_alloc(pool); 414 if (unlikely(m == NULL)) { 415 alloc_failures++; 416 rte_crypto_op_free(op); 417 continue; 418 } 419 420 rte_pktmbuf_append(m, len); 421 sym_op = op->sym; 422 sym_op->m_src = m; 423 424 sym_op->cipher.data.offset = data_offset; 425 sym_op->cipher.data.length = data_length; 426 427 rte_crypto_op_attach_sym_session( 428 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 429 } else { 430 struct rte_crypto_asym_op *asym_op; 431 uint8_t *result; 432 433 if (rte_mempool_get(pool, (void **)&result)) { 434 alloc_failures++; 435 continue; 436 } 437 438 op = rte_crypto_op_alloc(t->ca_op_pool, 439 RTE_CRYPTO_OP_TYPE_ASYMMETRIC); 440 if (unlikely(op == NULL)) { 441 alloc_failures++; 442 rte_mempool_put(pool, result); 443 continue; 444 } 445 446 asym_op = op->asym; 447 asym_op->modex.base.data = modex_test_case.base.data; 448 asym_op->modex.base.length = modex_test_case.base.len; 449 asym_op->modex.result.data = result; 450 asym_op->modex.result.length = modex_test_case.result_len; 451 rte_crypto_op_attach_asym_session( 452 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 453 } 454 while (rte_cryptodev_enqueue_burst(cdev_id, qp_id, &op, 1) != 1 && 455 t->done == false) 456 rte_pause(); 457 458 count++; 459 } 460 461 if (opt->verbose_level > 1 && alloc_failures) 462 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 463 __func__, rte_lcore_id(), alloc_failures); 464 } 465 466 static inline void 467 crypto_adapter_enq_op_fwd(struct prod_data *p) 468 { 469 const uint8_t dev_id = p->dev_id; 470 const uint8_t port = p->port_id; 471 struct test_perf *t = p->t; 472 const uint32_t nb_flows = t->nb_flows; 473 const uint64_t nb_pkts = t->nb_pkts; 474 struct rte_mempool *pool = t->pool; 475 struct evt_options *opt = t->opt; 476 uint64_t alloc_failures = 0; 477 uint32_t flow_counter = 0; 478 struct rte_crypto_op *op; 479 uint16_t len, offset; 480 struct rte_event ev; 481 struct rte_mbuf *m; 482 uint64_t count = 0; 483 484 if (opt->verbose_level > 1) 485 printf("%s(): lcore %d port %d queue %d cdev_id %u cdev_qp_id %u\n", 486 __func__, rte_lcore_id(), port, p->queue_id, 487 p->ca.cdev_id, p->ca.cdev_qp_id); 488 489 ev.event = 0; 490 ev.op = RTE_EVENT_OP_NEW; 491 ev.queue_id = p->queue_id; 492 ev.sched_type = RTE_SCHED_TYPE_ATOMIC; 493 ev.event_type = RTE_EVENT_TYPE_CPU; 494 495 offset = sizeof(struct perf_elt); 496 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 497 498 while (count < nb_pkts && t->done == false) { 499 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 500 struct rte_crypto_sym_op *sym_op; 501 502 op = rte_crypto_op_alloc(t->ca_op_pool, 503 RTE_CRYPTO_OP_TYPE_SYMMETRIC); 504 if (unlikely(op == NULL)) { 505 alloc_failures++; 506 continue; 507 } 508 509 m = rte_pktmbuf_alloc(pool); 510 if (unlikely(m == NULL)) { 511 alloc_failures++; 512 rte_crypto_op_free(op); 513 continue; 514 } 515 516 rte_pktmbuf_append(m, len); 517 sym_op = op->sym; 518 sym_op->m_src = m; 519 sym_op->cipher.data.offset = offset; 520 sym_op->cipher.data.length = len - offset; 521 rte_crypto_op_attach_sym_session( 522 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 523 } else { 524 struct rte_crypto_asym_op *asym_op; 525 uint8_t *result; 526 527 if (rte_mempool_get(pool, (void **)&result)) { 528 alloc_failures++; 529 continue; 530 } 531 532 op = rte_crypto_op_alloc(t->ca_op_pool, 533 RTE_CRYPTO_OP_TYPE_ASYMMETRIC); 534 if (unlikely(op == NULL)) { 535 alloc_failures++; 536 rte_mempool_put(pool, result); 537 continue; 538 } 539 540 asym_op = op->asym; 541 asym_op->modex.base.data = modex_test_case.base.data; 542 asym_op->modex.base.length = modex_test_case.base.len; 543 asym_op->modex.result.data = result; 544 asym_op->modex.result.length = modex_test_case.result_len; 545 rte_crypto_op_attach_asym_session( 546 op, p->ca.crypto_sess[flow_counter++ % nb_flows]); 547 } 548 ev.event_ptr = op; 549 550 while (rte_event_crypto_adapter_enqueue(dev_id, port, &ev, 1) != 1 && 551 t->done == false) 552 rte_pause(); 553 554 count++; 555 } 556 557 if (opt->verbose_level > 1 && alloc_failures) 558 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 559 __func__, rte_lcore_id(), alloc_failures); 560 } 561 562 static inline void 563 dma_adapter_enq_op_fwd(struct prod_data *p) 564 { 565 struct rte_event_dma_adapter_op *ops[BURST_SIZE] = {NULL}; 566 struct test_perf *t = p->t; 567 const uint32_t nb_flows = t->nb_flows; 568 const uint64_t nb_pkts = t->nb_pkts; 569 struct rte_event_dma_adapter_op op; 570 struct rte_event evts[BURST_SIZE]; 571 const uint8_t dev_id = p->dev_id; 572 struct evt_options *opt = t->opt; 573 const uint8_t port = p->port_id; 574 uint32_t flow_counter = 0; 575 struct rte_mempool *pool; 576 struct rte_event ev; 577 uint8_t *src, *dst; 578 uint64_t count = 0; 579 uint32_t flow; 580 int i; 581 582 pool = t->pool; 583 if (opt->verbose_level > 1) 584 printf("%s(): lcore %d port %d queue %d dma_dev_id %u dma_dev_vchan_id %u\n", 585 __func__, rte_lcore_id(), port, p->queue_id, 586 p->da.dma_dev_id, p->da.vchan_id); 587 588 src = rte_zmalloc(NULL, nb_flows * RTE_CACHE_LINE_SIZE, RTE_CACHE_LINE_SIZE); 589 dst = rte_zmalloc(NULL, nb_flows * RTE_CACHE_LINE_SIZE, RTE_CACHE_LINE_SIZE); 590 if (!src || !dst) { 591 rte_free(src); 592 rte_free(dst); 593 evt_err("Failed to alloc memory for src/dst"); 594 return; 595 } 596 597 ev.event = 0; 598 ev.op = RTE_EVENT_OP_NEW; 599 ev.queue_id = p->queue_id; 600 ev.sched_type = RTE_SCHED_TYPE_ATOMIC; 601 ev.event_type = RTE_EVENT_TYPE_CPU; 602 603 op.dma_dev_id = p->da.dma_dev_id; 604 op.vchan = p->da.vchan_id; 605 op.op_mp = pool; 606 op.flags = RTE_DMA_OP_FLAG_SUBMIT; 607 op.nb_src = 1; 608 op.nb_dst = 1; 609 610 while (count < nb_pkts && t->done == false) { 611 if (rte_mempool_get_bulk(pool, (void **)ops, BURST_SIZE) < 0) 612 continue; 613 for (i = 0; i < BURST_SIZE; i++) { 614 flow = flow_counter++ % nb_flows; 615 *ops[i] = op; 616 ops[i]->src_dst_seg[0].addr = (rte_iova_t)&src[flow * RTE_CACHE_LINE_SIZE]; 617 ops[i]->src_dst_seg[1].addr = (rte_iova_t)&dst[flow * RTE_CACHE_LINE_SIZE]; 618 ops[i]->src_dst_seg[0].length = RTE_CACHE_LINE_SIZE; 619 ops[i]->src_dst_seg[1].length = RTE_CACHE_LINE_SIZE; 620 621 evts[i].event = ev.event; 622 evts[i].flow_id = flow; 623 evts[i].event_ptr = ops[i]; 624 } 625 626 i = rte_event_dma_adapter_enqueue(dev_id, port, evts, BURST_SIZE); 627 while (i < BURST_SIZE) { 628 i += rte_event_dma_adapter_enqueue(dev_id, port, evts + i, BURST_SIZE - i); 629 if (t->done) 630 break; 631 rte_pause(); 632 } 633 634 count += BURST_SIZE; 635 } 636 } 637 638 static inline int 639 perf_event_dma_producer(void *arg) 640 { 641 struct prod_data *p = arg; 642 643 /* Only fwd mode is supported. */ 644 dma_adapter_enq_op_fwd(p); 645 646 return 0; 647 } 648 649 static inline int 650 perf_event_crypto_producer(void *arg) 651 { 652 struct prod_data *p = arg; 653 struct evt_options *opt = p->t->opt; 654 655 if (opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) 656 crypto_adapter_enq_op_new(p); 657 else 658 crypto_adapter_enq_op_fwd(p); 659 660 return 0; 661 } 662 663 static void 664 crypto_adapter_enq_op_new_burst(struct prod_data *p) 665 { 666 const struct test_perf *t = p->t; 667 const struct evt_options *opt = t->opt; 668 669 struct rte_mbuf *m, *pkts_burst[MAX_PROD_ENQ_BURST_SIZE]; 670 struct rte_crypto_op *ops_burst[MAX_PROD_ENQ_BURST_SIZE]; 671 const uint32_t burst_size = opt->prod_enq_burst_sz; 672 uint8_t *result[MAX_PROD_ENQ_BURST_SIZE]; 673 const uint32_t nb_flows = t->nb_flows; 674 const uint64_t nb_pkts = t->nb_pkts; 675 uint16_t len, enq, nb_alloc, offset; 676 struct rte_mempool *pool = t->pool; 677 uint16_t qp_id = p->ca.cdev_qp_id; 678 uint8_t cdev_id = p->ca.cdev_id; 679 uint64_t alloc_failures = 0; 680 uint32_t flow_counter = 0; 681 uint64_t count = 0; 682 uint32_t i; 683 684 if (opt->verbose_level > 1) 685 printf("%s(): lcore %d queue %d cdev_id %u cdev_qp_id %u\n", 686 __func__, rte_lcore_id(), p->queue_id, p->ca.cdev_id, 687 p->ca.cdev_qp_id); 688 689 offset = sizeof(struct perf_elt); 690 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 691 692 while (count < nb_pkts && t->done == false) { 693 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 694 struct rte_crypto_sym_op *sym_op; 695 int ret; 696 697 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 698 RTE_CRYPTO_OP_TYPE_SYMMETRIC, ops_burst, burst_size); 699 if (unlikely(nb_alloc != burst_size)) { 700 alloc_failures++; 701 continue; 702 } 703 704 ret = rte_pktmbuf_alloc_bulk(pool, pkts_burst, burst_size); 705 if (unlikely(ret != 0)) { 706 alloc_failures++; 707 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 708 continue; 709 } 710 711 for (i = 0; i < burst_size; i++) { 712 m = pkts_burst[i]; 713 rte_pktmbuf_append(m, len); 714 sym_op = ops_burst[i]->sym; 715 sym_op->m_src = m; 716 sym_op->cipher.data.offset = offset; 717 sym_op->cipher.data.length = len - offset; 718 rte_crypto_op_attach_sym_session(ops_burst[i], 719 p->ca.crypto_sess[flow_counter++ % nb_flows]); 720 } 721 } else { 722 struct rte_crypto_asym_op *asym_op; 723 724 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 725 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, ops_burst, burst_size); 726 if (unlikely(nb_alloc != burst_size)) { 727 alloc_failures++; 728 continue; 729 } 730 731 if (rte_mempool_get_bulk(pool, (void **)result, burst_size)) { 732 alloc_failures++; 733 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 734 continue; 735 } 736 737 for (i = 0; i < burst_size; i++) { 738 asym_op = ops_burst[i]->asym; 739 asym_op->modex.base.data = modex_test_case.base.data; 740 asym_op->modex.base.length = modex_test_case.base.len; 741 asym_op->modex.result.data = result[i]; 742 asym_op->modex.result.length = modex_test_case.result_len; 743 rte_crypto_op_attach_asym_session(ops_burst[i], 744 p->ca.crypto_sess[flow_counter++ % nb_flows]); 745 } 746 } 747 748 enq = 0; 749 while (!t->done) { 750 enq += rte_cryptodev_enqueue_burst(cdev_id, qp_id, ops_burst + enq, 751 burst_size - enq); 752 if (enq == burst_size) 753 break; 754 } 755 756 count += burst_size; 757 } 758 759 if (opt->verbose_level > 1 && alloc_failures) 760 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 761 __func__, rte_lcore_id(), alloc_failures); 762 } 763 764 static void 765 crypto_adapter_enq_op_fwd_burst(struct prod_data *p) 766 { 767 const struct test_perf *t = p->t; 768 const struct evt_options *opt = t->opt; 769 770 struct rte_mbuf *m, *pkts_burst[MAX_PROD_ENQ_BURST_SIZE]; 771 struct rte_crypto_op *ops_burst[MAX_PROD_ENQ_BURST_SIZE]; 772 const uint32_t burst_size = opt->prod_enq_burst_sz; 773 struct rte_event ev[MAX_PROD_ENQ_BURST_SIZE]; 774 uint8_t *result[MAX_PROD_ENQ_BURST_SIZE]; 775 const uint32_t nb_flows = t->nb_flows; 776 const uint64_t nb_pkts = t->nb_pkts; 777 uint16_t len, enq, nb_alloc, offset; 778 struct rte_mempool *pool = t->pool; 779 const uint8_t dev_id = p->dev_id; 780 const uint8_t port = p->port_id; 781 uint64_t alloc_failures = 0; 782 uint32_t flow_counter = 0; 783 uint64_t count = 0; 784 uint32_t i; 785 786 if (opt->verbose_level > 1) 787 printf("%s(): lcore %d port %d queue %d cdev_id %u cdev_qp_id %u\n", 788 __func__, rte_lcore_id(), port, p->queue_id, 789 p->ca.cdev_id, p->ca.cdev_qp_id); 790 791 offset = sizeof(struct perf_elt); 792 len = RTE_MAX(RTE_ETHER_MIN_LEN + offset, opt->mbuf_sz); 793 794 for (i = 0; i < burst_size; i++) { 795 ev[i].event = 0; 796 ev[i].op = RTE_EVENT_OP_NEW; 797 ev[i].queue_id = p->queue_id; 798 ev[i].sched_type = RTE_SCHED_TYPE_ATOMIC; 799 ev[i].event_type = RTE_EVENT_TYPE_CPU; 800 } 801 802 while (count < nb_pkts && t->done == false) { 803 if (opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 804 struct rte_crypto_sym_op *sym_op; 805 int ret; 806 807 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 808 RTE_CRYPTO_OP_TYPE_SYMMETRIC, ops_burst, burst_size); 809 if (unlikely(nb_alloc != burst_size)) { 810 alloc_failures++; 811 continue; 812 } 813 814 ret = rte_pktmbuf_alloc_bulk(pool, pkts_burst, burst_size); 815 if (unlikely(ret != 0)) { 816 alloc_failures++; 817 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 818 continue; 819 } 820 821 for (i = 0; i < burst_size; i++) { 822 m = pkts_burst[i]; 823 rte_pktmbuf_append(m, len); 824 sym_op = ops_burst[i]->sym; 825 sym_op->m_src = m; 826 sym_op->cipher.data.offset = offset; 827 sym_op->cipher.data.length = len - offset; 828 rte_crypto_op_attach_sym_session(ops_burst[i], 829 p->ca.crypto_sess[flow_counter++ % nb_flows]); 830 ev[i].event_ptr = ops_burst[i]; 831 } 832 } else { 833 struct rte_crypto_asym_op *asym_op; 834 835 nb_alloc = rte_crypto_op_bulk_alloc(t->ca_op_pool, 836 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, ops_burst, burst_size); 837 if (unlikely(nb_alloc != burst_size)) { 838 alloc_failures++; 839 continue; 840 } 841 842 if (rte_mempool_get_bulk(pool, (void **)result, burst_size)) { 843 alloc_failures++; 844 rte_mempool_put_bulk(t->ca_op_pool, (void **)ops_burst, burst_size); 845 continue; 846 } 847 848 for (i = 0; i < burst_size; i++) { 849 asym_op = ops_burst[i]->asym; 850 asym_op->modex.base.data = modex_test_case.base.data; 851 asym_op->modex.base.length = modex_test_case.base.len; 852 asym_op->modex.result.data = result[i]; 853 asym_op->modex.result.length = modex_test_case.result_len; 854 rte_crypto_op_attach_asym_session(ops_burst[i], 855 p->ca.crypto_sess[flow_counter++ % nb_flows]); 856 ev[i].event_ptr = ops_burst[i]; 857 } 858 } 859 860 enq = 0; 861 while (!t->done) { 862 enq += rte_event_crypto_adapter_enqueue(dev_id, port, ev + enq, 863 burst_size - enq); 864 if (enq == burst_size) 865 break; 866 } 867 868 count += burst_size; 869 } 870 871 if (opt->verbose_level > 1 && alloc_failures) 872 printf("%s(): lcore %d allocation failures: %"PRIu64"\n", 873 __func__, rte_lcore_id(), alloc_failures); 874 } 875 876 static inline int 877 perf_event_crypto_producer_burst(void *arg) 878 { 879 struct prod_data *p = arg; 880 struct evt_options *opt = p->t->opt; 881 882 if (opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) 883 crypto_adapter_enq_op_new_burst(p); 884 else 885 crypto_adapter_enq_op_fwd_burst(p); 886 887 return 0; 888 } 889 890 static int 891 perf_producer_wrapper(void *arg) 892 { 893 struct rte_event_dev_info dev_info; 894 struct prod_data *p = arg; 895 struct test_perf *t = p->t; 896 897 rte_event_dev_info_get(p->dev_id, &dev_info); 898 if (!t->opt->prod_enq_burst_sz) { 899 t->opt->prod_enq_burst_sz = MAX_PROD_ENQ_BURST_SIZE; 900 if (dev_info.max_event_port_enqueue_depth > 0 && 901 (uint32_t)dev_info.max_event_port_enqueue_depth < 902 t->opt->prod_enq_burst_sz) 903 t->opt->prod_enq_burst_sz = 904 dev_info.max_event_port_enqueue_depth; 905 } 906 907 /* In case of synthetic producer, launch perf_producer or 908 * perf_producer_burst depending on producer enqueue burst size 909 */ 910 if (t->opt->prod_type == EVT_PROD_TYPE_SYNT && 911 t->opt->prod_enq_burst_sz == 1) 912 return perf_producer(arg); 913 else if (t->opt->prod_type == EVT_PROD_TYPE_SYNT && 914 t->opt->prod_enq_burst_sz > 1) { 915 if (dev_info.max_event_port_enqueue_depth == 1) 916 evt_err("This event device does not support burst mode"); 917 else 918 return perf_producer_burst(arg); 919 } 920 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR && 921 !t->opt->timdev_use_burst) 922 return perf_event_timer_producer(arg); 923 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR && 924 t->opt->timdev_use_burst) 925 return perf_event_timer_producer_burst(arg); 926 else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 927 if (t->opt->prod_enq_burst_sz > 1) 928 return perf_event_crypto_producer_burst(arg); 929 else 930 return perf_event_crypto_producer(arg); 931 } else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) 932 return perf_event_dma_producer(arg); 933 934 return 0; 935 } 936 937 static inline uint64_t 938 processed_pkts(struct test_perf *t) 939 { 940 uint8_t i; 941 uint64_t total = 0; 942 943 for (i = 0; i < t->nb_workers; i++) 944 total += t->worker[i].processed_pkts; 945 946 return total; 947 } 948 949 static inline uint64_t 950 total_latency(struct test_perf *t) 951 { 952 uint8_t i; 953 uint64_t total = 0; 954 955 for (i = 0; i < t->nb_workers; i++) 956 total += t->worker[i].latency; 957 958 return total; 959 } 960 961 962 int 963 perf_launch_lcores(struct evt_test *test, struct evt_options *opt, 964 int (*worker)(void *)) 965 { 966 int ret, lcore_id; 967 struct test_perf *t = evt_test_priv(test); 968 969 int port_idx = 0; 970 /* launch workers */ 971 RTE_LCORE_FOREACH_WORKER(lcore_id) { 972 if (!(opt->wlcores[lcore_id])) 973 continue; 974 975 ret = rte_eal_remote_launch(worker, 976 &t->worker[port_idx], lcore_id); 977 if (ret) { 978 evt_err("failed to launch worker %d", lcore_id); 979 return ret; 980 } 981 port_idx++; 982 } 983 984 /* launch producers */ 985 RTE_LCORE_FOREACH_WORKER(lcore_id) { 986 if (!(opt->plcores[lcore_id])) 987 continue; 988 989 ret = rte_eal_remote_launch(perf_producer_wrapper, 990 &t->prod[port_idx], lcore_id); 991 if (ret) { 992 evt_err("failed to launch perf_producer %d", lcore_id); 993 return ret; 994 } 995 port_idx++; 996 } 997 998 const uint64_t total_pkts = t->outstand_pkts; 999 1000 uint64_t dead_lock_cycles = rte_get_timer_cycles(); 1001 int64_t dead_lock_remaining = total_pkts; 1002 const uint64_t dead_lock_sample = rte_get_timer_hz() * 5; 1003 1004 uint64_t perf_cycles = rte_get_timer_cycles(); 1005 int64_t perf_remaining = total_pkts; 1006 const uint64_t perf_sample = rte_get_timer_hz(); 1007 1008 static float total_mpps; 1009 static uint64_t samples; 1010 1011 const uint64_t freq_mhz = rte_get_timer_hz() / 1000000; 1012 int64_t remaining = t->outstand_pkts - processed_pkts(t); 1013 1014 while (t->done == false) { 1015 const uint64_t new_cycles = rte_get_timer_cycles(); 1016 1017 if ((new_cycles - perf_cycles) > perf_sample) { 1018 const uint64_t latency = total_latency(t); 1019 const uint64_t pkts = processed_pkts(t); 1020 1021 remaining = t->outstand_pkts - pkts; 1022 float mpps = (float)(perf_remaining-remaining)/1000000; 1023 1024 perf_remaining = remaining; 1025 perf_cycles = new_cycles; 1026 total_mpps += mpps; 1027 ++samples; 1028 if (opt->fwd_latency && pkts > 0) { 1029 printf(CLGRN"\r%.3f mpps avg %.3f mpps [avg fwd latency %.3f us] "CLNRM, 1030 mpps, total_mpps/samples, 1031 (float)(latency/pkts)/freq_mhz); 1032 } else { 1033 printf(CLGRN"\r%.3f mpps avg %.3f mpps"CLNRM, 1034 mpps, total_mpps/samples); 1035 } 1036 fflush(stdout); 1037 1038 if (remaining <= 0) { 1039 t->result = EVT_TEST_SUCCESS; 1040 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 1041 opt->prod_type == 1042 EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 1043 opt->prod_type == 1044 EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR || 1045 opt->prod_type == 1046 EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 1047 t->done = true; 1048 break; 1049 } 1050 } 1051 } 1052 1053 if (new_cycles - dead_lock_cycles > dead_lock_sample && 1054 (opt->prod_type == EVT_PROD_TYPE_SYNT || 1055 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 1056 opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR || 1057 opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR)) { 1058 remaining = t->outstand_pkts - processed_pkts(t); 1059 if (dead_lock_remaining == remaining) { 1060 rte_event_dev_dump(opt->dev_id, stdout); 1061 evt_err("No schedules for seconds, deadlock"); 1062 t->done = true; 1063 break; 1064 } 1065 dead_lock_remaining = remaining; 1066 dead_lock_cycles = new_cycles; 1067 } 1068 } 1069 printf("\n"); 1070 return 0; 1071 } 1072 1073 static int 1074 perf_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride, 1075 struct rte_event_port_conf prod_conf) 1076 { 1077 int ret = 0; 1078 uint16_t prod; 1079 struct rte_event_eth_rx_adapter_queue_conf queue_conf; 1080 1081 memset(&queue_conf, 0, 1082 sizeof(struct rte_event_eth_rx_adapter_queue_conf)); 1083 queue_conf.ev.sched_type = opt->sched_type_list[0]; 1084 RTE_ETH_FOREACH_DEV(prod) { 1085 uint32_t cap; 1086 1087 ret = rte_event_eth_rx_adapter_caps_get(opt->dev_id, 1088 prod, &cap); 1089 if (ret) { 1090 evt_err("failed to get event rx adapter[%d]" 1091 " capabilities", 1092 opt->dev_id); 1093 return ret; 1094 } 1095 queue_conf.ev.queue_id = prod * stride; 1096 ret = rte_event_eth_rx_adapter_create(prod, opt->dev_id, 1097 &prod_conf); 1098 if (ret) { 1099 evt_err("failed to create rx adapter[%d]", prod); 1100 return ret; 1101 } 1102 ret = rte_event_eth_rx_adapter_queue_add(prod, prod, -1, 1103 &queue_conf); 1104 if (ret) { 1105 evt_err("failed to add rx queues to adapter[%d]", prod); 1106 return ret; 1107 } 1108 1109 if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) { 1110 uint32_t service_id; 1111 1112 rte_event_eth_rx_adapter_service_id_get(prod, 1113 &service_id); 1114 ret = evt_service_setup(service_id); 1115 if (ret) { 1116 evt_err("Failed to setup service core" 1117 " for Rx adapter\n"); 1118 return ret; 1119 } 1120 } 1121 } 1122 1123 return ret; 1124 } 1125 1126 static int 1127 perf_event_timer_adapter_setup(struct test_perf *t) 1128 { 1129 int i; 1130 int ret; 1131 struct rte_event_timer_adapter_info adapter_info; 1132 struct rte_event_timer_adapter *wl; 1133 uint8_t nb_producers = evt_nr_active_lcores(t->opt->plcores); 1134 uint8_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; 1135 1136 if (nb_producers == 1) 1137 flags |= RTE_EVENT_TIMER_ADAPTER_F_SP_PUT; 1138 1139 for (i = 0; i < t->opt->nb_timer_adptrs; i++) { 1140 struct rte_event_timer_adapter_conf config = { 1141 .event_dev_id = t->opt->dev_id, 1142 .timer_adapter_id = i, 1143 .timer_tick_ns = t->opt->timer_tick_nsec, 1144 .max_tmo_ns = t->opt->max_tmo_nsec, 1145 .nb_timers = t->opt->pool_sz, 1146 .flags = flags, 1147 }; 1148 1149 wl = rte_event_timer_adapter_create(&config); 1150 if (wl == NULL) { 1151 evt_err("failed to create event timer ring %d", i); 1152 return rte_errno; 1153 } 1154 1155 memset(&adapter_info, 0, 1156 sizeof(struct rte_event_timer_adapter_info)); 1157 rte_event_timer_adapter_get_info(wl, &adapter_info); 1158 t->opt->optm_timer_tick_nsec = adapter_info.min_resolution_ns; 1159 1160 if (!(adapter_info.caps & 1161 RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT)) { 1162 uint32_t service_id = -1U; 1163 1164 rte_event_timer_adapter_service_id_get(wl, 1165 &service_id); 1166 ret = evt_service_setup(service_id); 1167 if (ret) { 1168 evt_err("Failed to setup service core" 1169 " for timer adapter\n"); 1170 return ret; 1171 } 1172 rte_service_runstate_set(service_id, 1); 1173 } 1174 t->timer_adptr[i] = wl; 1175 } 1176 return 0; 1177 } 1178 1179 static int 1180 perf_event_crypto_adapter_setup(struct test_perf *t, struct prod_data *p) 1181 { 1182 struct rte_event_crypto_adapter_queue_conf conf; 1183 struct evt_options *opt = t->opt; 1184 uint32_t cap; 1185 int ret; 1186 1187 memset(&conf, 0, sizeof(conf)); 1188 1189 ret = rte_event_crypto_adapter_caps_get(p->dev_id, p->ca.cdev_id, &cap); 1190 if (ret) { 1191 evt_err("Failed to get crypto adapter capabilities"); 1192 return ret; 1193 } 1194 1195 if (((opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_NEW) && 1196 !(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW)) || 1197 ((opt->crypto_adptr_mode == RTE_EVENT_CRYPTO_ADAPTER_OP_FORWARD) && 1198 !(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD))) { 1199 evt_err("crypto adapter %s mode unsupported\n", 1200 opt->crypto_adptr_mode ? "OP_FORWARD" : "OP_NEW"); 1201 return -ENOTSUP; 1202 } else if (!(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)) { 1203 evt_err("Storing crypto session not supported"); 1204 return -ENOTSUP; 1205 } 1206 1207 if (opt->ena_vector) { 1208 struct rte_event_crypto_adapter_vector_limits limits; 1209 1210 if (!(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR)) { 1211 evt_err("Crypto adapter doesn't support event vector"); 1212 return -EINVAL; 1213 } 1214 1215 ret = rte_event_crypto_adapter_vector_limits_get(p->dev_id, p->ca.cdev_id, &limits); 1216 if (ret) { 1217 evt_err("Failed to get crypto adapter's vector limits"); 1218 return ret; 1219 } 1220 1221 if (opt->vector_size < limits.min_sz || opt->vector_size > limits.max_sz) { 1222 evt_err("Vector size [%d] not within limits max[%d] min[%d]", 1223 opt->vector_size, limits.max_sz, limits.min_sz); 1224 return -EINVAL; 1225 } 1226 1227 if (limits.log2_sz && !rte_is_power_of_2(opt->vector_size)) { 1228 evt_err("Vector size [%d] not power of 2", opt->vector_size); 1229 return -EINVAL; 1230 } 1231 1232 if (opt->vector_tmo_nsec > limits.max_timeout_ns || 1233 opt->vector_tmo_nsec < limits.min_timeout_ns) { 1234 evt_err("Vector timeout [%" PRIu64 "] not within limits " 1235 "max[%" PRIu64 "] min[%" PRIu64 "]", 1236 opt->vector_tmo_nsec, limits.max_timeout_ns, limits.min_timeout_ns); 1237 return -EINVAL; 1238 } 1239 1240 conf.vector_mp = t->ca_vector_pool; 1241 conf.vector_sz = opt->vector_size; 1242 conf.vector_timeout_ns = opt->vector_tmo_nsec; 1243 conf.flags |= RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR; 1244 } 1245 1246 if (cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { 1247 conf.ev.sched_type = RTE_SCHED_TYPE_ATOMIC; 1248 conf.ev.queue_id = p->queue_id; 1249 } 1250 1251 ret = rte_event_crypto_adapter_queue_pair_add( 1252 TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id, &conf); 1253 1254 return ret; 1255 } 1256 1257 static int 1258 perf_event_dma_adapter_setup(struct test_perf *t, struct prod_data *p) 1259 { 1260 struct evt_options *opt = t->opt; 1261 struct rte_event event; 1262 uint32_t cap; 1263 int ret; 1264 1265 ret = rte_event_dma_adapter_caps_get(p->dev_id, p->da.dma_dev_id, &cap); 1266 if (ret) { 1267 evt_err("Failed to get dma adapter capabilities"); 1268 return ret; 1269 } 1270 1271 if (((opt->dma_adptr_mode == RTE_EVENT_DMA_ADAPTER_OP_NEW) && 1272 !(cap & RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_NEW)) || 1273 ((opt->dma_adptr_mode == RTE_EVENT_DMA_ADAPTER_OP_FORWARD) && 1274 !(cap & RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_FWD))) { 1275 evt_err("dma adapter %s mode unsupported\n", 1276 opt->dma_adptr_mode ? "OP_FORWARD" : "OP_NEW"); 1277 return -ENOTSUP; 1278 } 1279 1280 if (cap & RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_VCHAN_EV_BIND) 1281 ret = rte_event_dma_adapter_vchan_add(TEST_PERF_DA_ID, p->da.dma_dev_id, 1282 p->da.vchan_id, &event); 1283 else 1284 ret = rte_event_dma_adapter_vchan_add(TEST_PERF_DA_ID, p->da.dma_dev_id, 1285 p->da.vchan_id, NULL); 1286 1287 return ret; 1288 } 1289 1290 static void * 1291 cryptodev_sym_sess_create(struct prod_data *p, struct test_perf *t) 1292 { 1293 const struct rte_cryptodev_symmetric_capability *cap; 1294 struct rte_cryptodev_sym_capability_idx cap_idx; 1295 enum rte_crypto_cipher_algorithm cipher_algo; 1296 struct rte_crypto_sym_xform cipher_xform; 1297 struct evt_options *opt = t->opt; 1298 uint16_t key_size; 1299 uint16_t iv_size; 1300 void *sess; 1301 1302 cipher_algo = opt->crypto_cipher_alg; 1303 key_size = opt->crypto_cipher_key_sz; 1304 iv_size = opt->crypto_cipher_iv_sz; 1305 1306 /* Check if device supports the algorithm */ 1307 cap_idx.type = RTE_CRYPTO_SYM_XFORM_CIPHER; 1308 cap_idx.algo.cipher = cipher_algo; 1309 1310 cap = rte_cryptodev_sym_capability_get(p->ca.cdev_id, &cap_idx); 1311 if (cap == NULL) { 1312 evt_err("Device doesn't support cipher algorithm [%s]. Test Skipped\n", 1313 rte_cryptodev_get_cipher_algo_string(cipher_algo)); 1314 return NULL; 1315 } 1316 1317 /* Check if device supports key size and IV size */ 1318 if (rte_cryptodev_sym_capability_check_cipher(cap, key_size, 1319 iv_size) < 0) { 1320 evt_err("Device doesn't support cipher configuration:\n" 1321 "cipher algo [%s], key sz [%d], iv sz [%d]. Test Skipped\n", 1322 rte_cryptodev_get_cipher_algo_string(cipher_algo), key_size, iv_size); 1323 return NULL; 1324 } 1325 1326 cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER; 1327 cipher_xform.cipher.algo = cipher_algo; 1328 cipher_xform.cipher.key.data = opt->crypto_cipher_key; 1329 cipher_xform.cipher.key.length = key_size; 1330 cipher_xform.cipher.iv.length = iv_size; 1331 cipher_xform.cipher.iv.offset = IV_OFFSET; 1332 cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT; 1333 cipher_xform.next = NULL; 1334 1335 sess = rte_cryptodev_sym_session_create(p->ca.cdev_id, &cipher_xform, 1336 t->ca_sess_pool); 1337 if (sess == NULL) { 1338 evt_err("Failed to create sym session"); 1339 return NULL; 1340 } 1341 1342 return sess; 1343 } 1344 1345 static void * 1346 cryptodev_asym_sess_create(struct prod_data *p, struct test_perf *t) 1347 { 1348 const struct rte_cryptodev_asymmetric_xform_capability *capability; 1349 struct rte_cryptodev_asym_capability_idx cap_idx; 1350 struct rte_crypto_asym_xform xform; 1351 void *sess; 1352 1353 xform.next = NULL; 1354 xform.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX; 1355 cap_idx.type = xform.xform_type; 1356 capability = rte_cryptodev_asym_capability_get(p->ca.cdev_id, &cap_idx); 1357 if (capability == NULL) { 1358 evt_err("Device doesn't support MODEX. Test Skipped\n"); 1359 return NULL; 1360 } 1361 1362 xform.modex.modulus.data = modex_test_case.modulus.data; 1363 xform.modex.modulus.length = modex_test_case.modulus.len; 1364 xform.modex.exponent.data = modex_test_case.exponent.data; 1365 xform.modex.exponent.length = modex_test_case.exponent.len; 1366 1367 if (rte_cryptodev_asym_session_create(p->ca.cdev_id, &xform, 1368 t->ca_asym_sess_pool, &sess)) { 1369 evt_err("Failed to create asym session"); 1370 return NULL; 1371 } 1372 1373 return sess; 1374 } 1375 1376 int 1377 perf_event_dev_port_setup(struct evt_test *test, struct evt_options *opt, 1378 uint8_t stride, uint8_t nb_queues, 1379 const struct rte_event_port_conf *port_conf) 1380 { 1381 struct test_perf *t = evt_test_priv(test); 1382 uint16_t port, prod; 1383 int ret = -1; 1384 1385 /* setup one port per worker, linking to all queues */ 1386 for (port = 0; port < evt_nr_active_lcores(opt->wlcores); 1387 port++) { 1388 struct worker_data *w = &t->worker[port]; 1389 1390 w->dev_id = opt->dev_id; 1391 w->port_id = port; 1392 w->t = t; 1393 w->processed_pkts = 0; 1394 w->latency = 0; 1395 1396 struct rte_event_port_conf conf = *port_conf; 1397 conf.event_port_cfg |= RTE_EVENT_PORT_CFG_HINT_WORKER; 1398 1399 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1400 if (ret) { 1401 evt_err("failed to setup port %d", port); 1402 return ret; 1403 } 1404 1405 ret = rte_event_port_link(opt->dev_id, port, NULL, NULL, 0); 1406 if (ret != nb_queues) { 1407 evt_err("failed to link all queues to port %d", port); 1408 return -EINVAL; 1409 } 1410 } 1411 1412 /* port for producers, no links */ 1413 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1414 for ( ; port < perf_nb_event_ports(opt); port++) { 1415 struct prod_data *p = &t->prod[port]; 1416 p->t = t; 1417 } 1418 1419 struct rte_event_port_conf conf = *port_conf; 1420 conf.event_port_cfg |= RTE_EVENT_PORT_CFG_HINT_PRODUCER; 1421 1422 ret = perf_event_rx_adapter_setup(opt, stride, conf); 1423 if (ret) 1424 return ret; 1425 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1426 prod = 0; 1427 for ( ; port < perf_nb_event_ports(opt); port++) { 1428 struct prod_data *p = &t->prod[port]; 1429 p->queue_id = prod * stride; 1430 p->t = t; 1431 prod++; 1432 } 1433 1434 ret = perf_event_timer_adapter_setup(t); 1435 if (ret) 1436 return ret; 1437 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 1438 struct rte_event_port_conf conf = *port_conf; 1439 uint8_t cdev_id = 0; 1440 uint16_t qp_id = 0; 1441 1442 ret = rte_event_crypto_adapter_create(TEST_PERF_CA_ID, 1443 opt->dev_id, &conf, 0); 1444 if (ret) { 1445 evt_err("Failed to create crypto adapter"); 1446 return ret; 1447 } 1448 1449 prod = 0; 1450 for (; port < perf_nb_event_ports(opt); port++) { 1451 union rte_event_crypto_metadata m_data; 1452 struct prod_data *p = &t->prod[port]; 1453 uint32_t flow_id; 1454 1455 if (qp_id == rte_cryptodev_queue_pair_count(cdev_id)) { 1456 cdev_id++; 1457 qp_id = 0; 1458 } 1459 1460 p->dev_id = opt->dev_id; 1461 p->port_id = port; 1462 p->queue_id = prod * stride; 1463 p->ca.cdev_id = cdev_id; 1464 p->ca.cdev_qp_id = qp_id; 1465 p->ca.crypto_sess = rte_zmalloc_socket( 1466 NULL, sizeof(void *) * t->nb_flows, 1467 RTE_CACHE_LINE_SIZE, opt->socket_id); 1468 p->t = t; 1469 1470 ret = perf_event_crypto_adapter_setup(t, p); 1471 if (ret) 1472 return ret; 1473 1474 m_data.request_info.cdev_id = p->ca.cdev_id; 1475 m_data.request_info.queue_pair_id = p->ca.cdev_qp_id; 1476 m_data.response_info.sched_type = RTE_SCHED_TYPE_ATOMIC; 1477 m_data.response_info.queue_id = p->queue_id; 1478 1479 for (flow_id = 0; flow_id < t->nb_flows; flow_id++) { 1480 m_data.response_info.flow_id = flow_id; 1481 if (opt->crypto_op_type == 1482 RTE_CRYPTO_OP_TYPE_SYMMETRIC) { 1483 void *sess; 1484 1485 sess = cryptodev_sym_sess_create(p, t); 1486 if (sess == NULL) 1487 return -ENOMEM; 1488 1489 ret = rte_cryptodev_session_event_mdata_set( 1490 cdev_id, 1491 sess, 1492 RTE_CRYPTO_OP_TYPE_SYMMETRIC, 1493 RTE_CRYPTO_OP_WITH_SESSION, 1494 &m_data, sizeof(m_data)); 1495 if (ret) 1496 return ret; 1497 p->ca.crypto_sess[flow_id] = sess; 1498 } else { 1499 void *sess; 1500 1501 sess = cryptodev_asym_sess_create(p, t); 1502 if (sess == NULL) 1503 return -ENOMEM; 1504 ret = rte_cryptodev_session_event_mdata_set( 1505 cdev_id, 1506 sess, 1507 RTE_CRYPTO_OP_TYPE_ASYMMETRIC, 1508 RTE_CRYPTO_OP_WITH_SESSION, 1509 &m_data, sizeof(m_data)); 1510 if (ret) 1511 return ret; 1512 p->ca.crypto_sess[flow_id] = sess; 1513 } 1514 } 1515 1516 conf.event_port_cfg |= 1517 RTE_EVENT_PORT_CFG_HINT_PRODUCER | 1518 RTE_EVENT_PORT_CFG_HINT_CONSUMER; 1519 1520 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1521 if (ret) { 1522 evt_err("failed to setup port %d", port); 1523 return ret; 1524 } 1525 1526 qp_id++; 1527 prod++; 1528 } 1529 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 1530 struct rte_event_port_conf conf = *port_conf; 1531 uint8_t dma_dev_id = 0; 1532 uint16_t vchan_id = 0; 1533 1534 ret = rte_event_dma_adapter_create(TEST_PERF_DA_ID, opt->dev_id, &conf, 0); 1535 if (ret) { 1536 evt_err("Failed to create dma adapter"); 1537 return ret; 1538 } 1539 1540 prod = 0; 1541 for (; port < perf_nb_event_ports(opt); port++) { 1542 struct prod_data *p = &t->prod[port]; 1543 1544 p->dev_id = opt->dev_id; 1545 p->port_id = port; 1546 p->queue_id = prod * stride; 1547 p->da.dma_dev_id = dma_dev_id; 1548 p->da.vchan_id = vchan_id; 1549 p->t = t; 1550 1551 ret = perf_event_dma_adapter_setup(t, p); 1552 if (ret) 1553 return ret; 1554 1555 conf.event_port_cfg |= 1556 RTE_EVENT_PORT_CFG_HINT_PRODUCER | 1557 RTE_EVENT_PORT_CFG_HINT_CONSUMER; 1558 1559 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1560 if (ret) { 1561 evt_err("failed to setup port %d", port); 1562 return ret; 1563 } 1564 1565 prod++; 1566 } 1567 } else { 1568 prod = 0; 1569 for ( ; port < perf_nb_event_ports(opt); port++) { 1570 struct prod_data *p = &t->prod[port]; 1571 1572 p->dev_id = opt->dev_id; 1573 p->port_id = port; 1574 p->queue_id = prod * stride; 1575 p->t = t; 1576 1577 struct rte_event_port_conf conf = *port_conf; 1578 conf.event_port_cfg |= 1579 RTE_EVENT_PORT_CFG_HINT_PRODUCER | 1580 RTE_EVENT_PORT_CFG_HINT_CONSUMER; 1581 1582 ret = rte_event_port_setup(opt->dev_id, port, &conf); 1583 if (ret) { 1584 evt_err("failed to setup port %d", port); 1585 return ret; 1586 } 1587 prod++; 1588 } 1589 } 1590 1591 return ret; 1592 } 1593 1594 int 1595 perf_opt_check(struct evt_options *opt, uint64_t nb_queues) 1596 { 1597 unsigned int lcores; 1598 1599 /* N producer + N worker + main when producer cores are used 1600 * Else N worker + main when Rx adapter is used 1601 */ 1602 lcores = opt->prod_type == EVT_PROD_TYPE_SYNT ? 3 : 2; 1603 1604 if (rte_lcore_count() < lcores) { 1605 evt_err("test need minimum %d lcores", lcores); 1606 return -1; 1607 } 1608 1609 /* Validate worker lcores */ 1610 if (evt_lcores_has_overlap(opt->wlcores, rte_get_main_lcore())) { 1611 evt_err("worker lcores overlaps with main lcore"); 1612 return -1; 1613 } 1614 if (evt_lcores_has_overlap_multi(opt->wlcores, opt->plcores)) { 1615 evt_err("worker lcores overlaps producer lcores"); 1616 return -1; 1617 } 1618 if (evt_has_disabled_lcore(opt->wlcores)) { 1619 evt_err("one or more workers lcores are not enabled"); 1620 return -1; 1621 } 1622 if (!evt_has_active_lcore(opt->wlcores)) { 1623 evt_err("minimum one worker is required"); 1624 return -1; 1625 } 1626 1627 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 1628 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR || 1629 opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR || 1630 opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 1631 /* Validate producer lcores */ 1632 if (evt_lcores_has_overlap(opt->plcores, 1633 rte_get_main_lcore())) { 1634 evt_err("producer lcores overlaps with main lcore"); 1635 return -1; 1636 } 1637 if (evt_has_disabled_lcore(opt->plcores)) { 1638 evt_err("one or more producer lcores are not enabled"); 1639 return -1; 1640 } 1641 if (!evt_has_active_lcore(opt->plcores)) { 1642 evt_err("minimum one producer is required"); 1643 return -1; 1644 } 1645 } 1646 1647 if (evt_has_invalid_stage(opt)) 1648 return -1; 1649 1650 if (evt_has_invalid_sched_type(opt)) 1651 return -1; 1652 1653 if (nb_queues > EVT_MAX_QUEUES) { 1654 evt_err("number of queues exceeds %d", EVT_MAX_QUEUES); 1655 return -1; 1656 } 1657 if (perf_nb_event_ports(opt) > EVT_MAX_PORTS) { 1658 evt_err("number of ports exceeds %d", EVT_MAX_PORTS); 1659 return -1; 1660 } 1661 1662 /* Fixups */ 1663 if ((opt->nb_stages == 1 && 1664 opt->prod_type != EVT_PROD_TYPE_EVENT_TIMER_ADPTR) && 1665 opt->fwd_latency) { 1666 evt_info("fwd_latency is valid when nb_stages > 1, disabling"); 1667 opt->fwd_latency = 0; 1668 } 1669 1670 if (opt->fwd_latency && !opt->q_priority) { 1671 evt_info("enabled queue priority for latency measurement"); 1672 opt->q_priority = 1; 1673 } 1674 if (opt->nb_pkts == 0) 1675 opt->nb_pkts = INT64_MAX/evt_nr_active_lcores(opt->plcores); 1676 1677 return 0; 1678 } 1679 1680 void 1681 perf_opt_dump(struct evt_options *opt, uint8_t nb_queues) 1682 { 1683 evt_dump("nb_prod_lcores", "%d", evt_nr_active_lcores(opt->plcores)); 1684 evt_dump_producer_lcores(opt); 1685 evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores)); 1686 evt_dump_worker_lcores(opt); 1687 evt_dump_nb_stages(opt); 1688 evt_dump("nb_evdev_ports", "%d", perf_nb_event_ports(opt)); 1689 evt_dump("nb_evdev_queues", "%d", nb_queues); 1690 evt_dump_queue_priority(opt); 1691 evt_dump_sched_type_list(opt); 1692 evt_dump_producer_type(opt); 1693 evt_dump("prod_enq_burst_sz", "%d", opt->prod_enq_burst_sz); 1694 } 1695 1696 static void 1697 perf_event_port_flush(uint8_t dev_id __rte_unused, struct rte_event ev, 1698 void *args) 1699 { 1700 rte_mempool_put(args, ev.event_ptr); 1701 } 1702 1703 void 1704 perf_worker_cleanup(struct rte_mempool *const pool, uint8_t dev_id, 1705 uint8_t port_id, struct rte_event events[], uint16_t nb_enq, 1706 uint16_t nb_deq) 1707 { 1708 int i; 1709 1710 if (nb_deq) { 1711 for (i = nb_enq; i < nb_deq; i++) 1712 rte_mempool_put(pool, events[i].event_ptr); 1713 1714 for (i = 0; i < nb_deq; i++) 1715 events[i].op = RTE_EVENT_OP_RELEASE; 1716 rte_event_enqueue_burst(dev_id, port_id, events, nb_deq); 1717 } 1718 rte_event_port_quiesce(dev_id, port_id, perf_event_port_flush, pool); 1719 } 1720 1721 void 1722 perf_eventdev_destroy(struct evt_test *test, struct evt_options *opt) 1723 { 1724 int i; 1725 struct test_perf *t = evt_test_priv(test); 1726 1727 if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 1728 for (i = 0; i < opt->nb_timer_adptrs; i++) 1729 rte_event_timer_adapter_stop(t->timer_adptr[i]); 1730 } 1731 rte_event_dev_stop(opt->dev_id); 1732 rte_event_dev_close(opt->dev_id); 1733 } 1734 1735 static inline void 1736 perf_elt_init(struct rte_mempool *mp, void *arg __rte_unused, 1737 void *obj, unsigned i __rte_unused) 1738 { 1739 memset(obj, 0, mp->elt_size); 1740 } 1741 1742 #define NB_RX_DESC 128 1743 #define NB_TX_DESC 512 1744 int 1745 perf_ethdev_setup(struct evt_test *test, struct evt_options *opt) 1746 { 1747 uint16_t i; 1748 int ret; 1749 struct test_perf *t = evt_test_priv(test); 1750 struct rte_eth_conf port_conf = { 1751 .rxmode = { 1752 .mq_mode = RTE_ETH_MQ_RX_RSS, 1753 }, 1754 .rx_adv_conf = { 1755 .rss_conf = { 1756 .rss_key = NULL, 1757 .rss_hf = RTE_ETH_RSS_IP, 1758 }, 1759 }, 1760 }; 1761 1762 if (opt->prod_type != EVT_PROD_TYPE_ETH_RX_ADPTR) 1763 return 0; 1764 1765 if (!rte_eth_dev_count_avail()) { 1766 evt_err("No ethernet ports found."); 1767 return -ENODEV; 1768 } 1769 1770 RTE_ETH_FOREACH_DEV(i) { 1771 struct rte_eth_dev_info dev_info; 1772 struct rte_eth_conf local_port_conf = port_conf; 1773 1774 ret = rte_eth_dev_info_get(i, &dev_info); 1775 if (ret != 0) { 1776 evt_err("Error during getting device (port %u) info: %s\n", 1777 i, strerror(-ret)); 1778 return ret; 1779 } 1780 1781 local_port_conf.rx_adv_conf.rss_conf.rss_hf &= 1782 dev_info.flow_type_rss_offloads; 1783 if (local_port_conf.rx_adv_conf.rss_conf.rss_hf != 1784 port_conf.rx_adv_conf.rss_conf.rss_hf) { 1785 evt_info("Port %u modified RSS hash function based on hardware support," 1786 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 1787 i, 1788 port_conf.rx_adv_conf.rss_conf.rss_hf, 1789 local_port_conf.rx_adv_conf.rss_conf.rss_hf); 1790 } 1791 1792 if (rte_eth_dev_configure(i, 1, 1, &local_port_conf) < 0) { 1793 evt_err("Failed to configure eth port [%d]", i); 1794 return -EINVAL; 1795 } 1796 1797 if (rte_eth_rx_queue_setup(i, 0, NB_RX_DESC, 1798 rte_socket_id(), NULL, t->pool) < 0) { 1799 evt_err("Failed to setup eth port [%d] rx_queue: %d.", 1800 i, 0); 1801 return -EINVAL; 1802 } 1803 1804 if (rte_eth_tx_queue_setup(i, 0, NB_TX_DESC, 1805 rte_socket_id(), NULL) < 0) { 1806 evt_err("Failed to setup eth port [%d] tx_queue: %d.", 1807 i, 0); 1808 return -EINVAL; 1809 } 1810 1811 ret = rte_eth_promiscuous_enable(i); 1812 if (ret != 0) { 1813 evt_err("Failed to enable promiscuous mode for eth port [%d]: %s", 1814 i, rte_strerror(-ret)); 1815 return ret; 1816 } 1817 } 1818 1819 return 0; 1820 } 1821 1822 void 1823 perf_ethdev_rx_stop(struct evt_test *test, struct evt_options *opt) 1824 { 1825 uint16_t i; 1826 RTE_SET_USED(test); 1827 1828 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1829 RTE_ETH_FOREACH_DEV(i) { 1830 rte_event_eth_rx_adapter_stop(i); 1831 rte_event_eth_rx_adapter_queue_del(i, i, -1); 1832 rte_eth_dev_rx_queue_stop(i, 0); 1833 } 1834 } 1835 } 1836 1837 void 1838 perf_ethdev_destroy(struct evt_test *test, struct evt_options *opt) 1839 { 1840 uint16_t i; 1841 RTE_SET_USED(test); 1842 1843 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 1844 RTE_ETH_FOREACH_DEV(i) { 1845 rte_event_eth_tx_adapter_stop(i); 1846 rte_event_eth_tx_adapter_queue_del(i, i, -1); 1847 rte_eth_dev_tx_queue_stop(i, 0); 1848 rte_eth_dev_stop(i); 1849 } 1850 } 1851 } 1852 1853 int 1854 perf_cryptodev_setup(struct evt_test *test, struct evt_options *opt) 1855 { 1856 uint8_t cdev_count, cdev_id, nb_plcores, nb_qps; 1857 struct test_perf *t = evt_test_priv(test); 1858 unsigned int max_session_size; 1859 uint32_t nb_sessions; 1860 int ret; 1861 1862 if (opt->prod_type != EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 1863 return 0; 1864 1865 cdev_count = rte_cryptodev_count(); 1866 if (cdev_count == 0) { 1867 evt_err("No crypto devices available\n"); 1868 return -ENODEV; 1869 } 1870 1871 t->ca_op_pool = rte_crypto_op_pool_create( 1872 "crypto_op_pool", opt->crypto_op_type, opt->pool_sz, 1873 128, sizeof(union rte_event_crypto_metadata) + EVT_CRYPTO_MAX_IV_SIZE, 1874 rte_socket_id()); 1875 if (t->ca_op_pool == NULL) { 1876 evt_err("Failed to create crypto op pool"); 1877 return -ENOMEM; 1878 } 1879 1880 nb_sessions = evt_nr_active_lcores(opt->plcores) * t->nb_flows; 1881 t->ca_asym_sess_pool = rte_cryptodev_asym_session_pool_create( 1882 "ca_asym_sess_pool", nb_sessions, 0, 1883 sizeof(union rte_event_crypto_metadata), SOCKET_ID_ANY); 1884 if (t->ca_asym_sess_pool == NULL) { 1885 evt_err("Failed to create sym session pool"); 1886 ret = -ENOMEM; 1887 goto err; 1888 } 1889 1890 max_session_size = 0; 1891 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 1892 unsigned int session_size; 1893 1894 session_size = 1895 rte_cryptodev_sym_get_private_session_size(cdev_id); 1896 if (session_size > max_session_size) 1897 max_session_size = session_size; 1898 } 1899 1900 t->ca_sess_pool = rte_cryptodev_sym_session_pool_create( 1901 "ca_sess_pool", nb_sessions, max_session_size, 0, 1902 sizeof(union rte_event_crypto_metadata), SOCKET_ID_ANY); 1903 if (t->ca_sess_pool == NULL) { 1904 evt_err("Failed to create sym session pool"); 1905 ret = -ENOMEM; 1906 goto err; 1907 } 1908 1909 if (opt->ena_vector) { 1910 unsigned int nb_elem = (opt->pool_sz / opt->vector_size) * 2; 1911 nb_elem = RTE_MAX(512U, nb_elem); 1912 nb_elem += evt_nr_active_lcores(opt->wlcores) * 32; 1913 t->ca_vector_pool = rte_event_vector_pool_create("vector_pool", nb_elem, 32, 1914 opt->vector_size, opt->socket_id); 1915 if (t->ca_vector_pool == NULL) { 1916 evt_err("Failed to create event vector pool"); 1917 ret = -ENOMEM; 1918 goto err; 1919 } 1920 } 1921 1922 /* 1923 * Calculate number of needed queue pairs, based on the amount of 1924 * available number of logical cores and crypto devices. For instance, 1925 * if there are 4 cores and 2 crypto devices, 2 queue pairs will be set 1926 * up per device. 1927 */ 1928 nb_plcores = evt_nr_active_lcores(opt->plcores); 1929 nb_qps = (nb_plcores % cdev_count) ? (nb_plcores / cdev_count) + 1 : 1930 nb_plcores / cdev_count; 1931 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 1932 struct rte_cryptodev_qp_conf qp_conf; 1933 struct rte_cryptodev_config conf; 1934 struct rte_cryptodev_info info; 1935 int qp_id; 1936 1937 rte_cryptodev_info_get(cdev_id, &info); 1938 if (nb_qps > info.max_nb_queue_pairs) { 1939 evt_err("Not enough queue pairs per cryptodev (%u)", 1940 nb_qps); 1941 ret = -EINVAL; 1942 goto err; 1943 } 1944 1945 conf.nb_queue_pairs = nb_qps; 1946 conf.socket_id = SOCKET_ID_ANY; 1947 conf.ff_disable = RTE_CRYPTODEV_FF_SECURITY; 1948 1949 ret = rte_cryptodev_configure(cdev_id, &conf); 1950 if (ret) { 1951 evt_err("Failed to configure cryptodev (%u)", cdev_id); 1952 goto err; 1953 } 1954 1955 qp_conf.nb_descriptors = NB_CRYPTODEV_DESCRIPTORS; 1956 qp_conf.mp_session = t->ca_sess_pool; 1957 1958 for (qp_id = 0; qp_id < conf.nb_queue_pairs; qp_id++) { 1959 ret = rte_cryptodev_queue_pair_setup( 1960 cdev_id, qp_id, &qp_conf, 1961 rte_cryptodev_socket_id(cdev_id)); 1962 if (ret) { 1963 evt_err("Failed to setup queue pairs on cryptodev %u\n", 1964 cdev_id); 1965 goto err; 1966 } 1967 } 1968 } 1969 1970 return 0; 1971 err: 1972 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) 1973 rte_cryptodev_close(cdev_id); 1974 1975 rte_mempool_free(t->ca_op_pool); 1976 rte_mempool_free(t->ca_sess_pool); 1977 rte_mempool_free(t->ca_asym_sess_pool); 1978 rte_mempool_free(t->ca_vector_pool); 1979 1980 return ret; 1981 } 1982 1983 void 1984 perf_cryptodev_destroy(struct evt_test *test, struct evt_options *opt) 1985 { 1986 uint8_t cdev_id, cdev_count = rte_cryptodev_count(); 1987 struct test_perf *t = evt_test_priv(test); 1988 uint16_t port; 1989 1990 if (opt->prod_type != EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 1991 return; 1992 1993 for (port = t->nb_workers; port < perf_nb_event_ports(opt); port++) { 1994 void *sess; 1995 struct prod_data *p = &t->prod[port]; 1996 uint32_t flow_id; 1997 uint8_t cdev_id; 1998 1999 for (flow_id = 0; flow_id < t->nb_flows; flow_id++) { 2000 sess = p->ca.crypto_sess[flow_id]; 2001 cdev_id = p->ca.cdev_id; 2002 rte_cryptodev_sym_session_free(cdev_id, sess); 2003 } 2004 2005 rte_event_crypto_adapter_queue_pair_del( 2006 TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id); 2007 } 2008 2009 rte_event_crypto_adapter_free(TEST_PERF_CA_ID); 2010 2011 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 2012 rte_cryptodev_stop(cdev_id); 2013 rte_cryptodev_close(cdev_id); 2014 } 2015 2016 rte_mempool_free(t->ca_op_pool); 2017 rte_mempool_free(t->ca_sess_pool); 2018 rte_mempool_free(t->ca_asym_sess_pool); 2019 rte_mempool_free(t->ca_vector_pool); 2020 } 2021 2022 int 2023 perf_dmadev_setup(struct evt_test *test, struct evt_options *opt) 2024 { 2025 const struct rte_dma_conf conf = { .nb_vchans = 1}; 2026 const struct rte_dma_vchan_conf qconf = { 2027 .direction = RTE_DMA_DIR_MEM_TO_MEM, 2028 .nb_desc = 1024, 2029 }; 2030 uint8_t dma_dev_count, dma_dev_id = 0; 2031 int vchan_id; 2032 int ret; 2033 2034 RTE_SET_USED(test); 2035 if (opt->prod_type != EVT_PROD_TYPE_EVENT_DMA_ADPTR) 2036 return 0; 2037 2038 dma_dev_count = rte_dma_count_avail(); 2039 if (dma_dev_count == 0) { 2040 evt_err("No dma devices available\n"); 2041 return -ENODEV; 2042 } 2043 2044 ret = rte_dma_configure(dma_dev_id, &conf); 2045 if (ret) { 2046 evt_err("Failed to configure dma dev (%u)", dma_dev_id); 2047 goto err; 2048 } 2049 2050 for (vchan_id = 0; vchan_id < conf.nb_vchans; vchan_id++) { 2051 ret = rte_dma_vchan_setup(dma_dev_id, vchan_id, &qconf); 2052 if (ret) { 2053 evt_err("Failed to setup vchan on dma dev %u\n", 2054 dma_dev_id); 2055 goto err; 2056 } 2057 } 2058 2059 return 0; 2060 err: 2061 rte_dma_close(dma_dev_id); 2062 2063 return ret; 2064 } 2065 2066 void 2067 perf_dmadev_destroy(struct evt_test *test, struct evt_options *opt) 2068 { 2069 uint8_t dma_dev_id = 0; 2070 struct test_perf *t = evt_test_priv(test); 2071 uint16_t port; 2072 2073 if (opt->prod_type != EVT_PROD_TYPE_EVENT_DMA_ADPTR) 2074 return; 2075 2076 for (port = t->nb_workers; port < perf_nb_event_ports(opt); port++) { 2077 struct prod_data *p = &t->prod[port]; 2078 2079 rte_event_dma_adapter_vchan_del(TEST_PERF_DA_ID, p->da.dma_dev_id, p->da.vchan_id); 2080 } 2081 2082 rte_event_dma_adapter_free(TEST_PERF_DA_ID); 2083 2084 rte_dma_stop(dma_dev_id); 2085 rte_dma_close(dma_dev_id); 2086 } 2087 2088 int 2089 perf_mempool_setup(struct evt_test *test, struct evt_options *opt) 2090 { 2091 struct test_perf *t = evt_test_priv(test); 2092 unsigned int cache_sz; 2093 2094 cache_sz = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, (opt->pool_sz / 1.5) / t->nb_workers); 2095 if (opt->prod_type == EVT_PROD_TYPE_SYNT || 2096 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 2097 t->pool = rte_mempool_create(test->name, /* mempool name */ 2098 opt->pool_sz, /* number of elements*/ 2099 sizeof(struct perf_elt), /* element size*/ 2100 cache_sz, /* cache size*/ 2101 0, NULL, NULL, 2102 perf_elt_init, /* obj constructor */ 2103 NULL, opt->socket_id, 0); /* flags */ 2104 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR && 2105 opt->crypto_op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { 2106 t->pool = rte_mempool_create(test->name, /* mempool name */ 2107 opt->pool_sz, /* number of elements*/ 2108 sizeof(struct perf_elt) + modex_test_case.result_len, 2109 /* element size*/ 2110 cache_sz, /* cache size*/ 2111 0, NULL, NULL, 2112 NULL, /* obj constructor */ 2113 NULL, opt->socket_id, 0); /* flags */ 2114 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 2115 t->pool = rte_mempool_create(test->name, /* mempool name */ 2116 opt->pool_sz, /* number of elements*/ 2117 sizeof(struct rte_event_dma_adapter_op) + 2118 (sizeof(struct rte_dma_sge) * 2), 2119 cache_sz, /* cache size*/ 2120 0, NULL, NULL, NULL, /* obj constructor */ 2121 NULL, opt->socket_id, 0); /* flags */ 2122 } else { 2123 t->pool = rte_pktmbuf_pool_create(test->name, /* mempool name */ 2124 opt->pool_sz, /* number of elements*/ 2125 cache_sz, /* cache size*/ 2126 0, 2127 RTE_MBUF_DEFAULT_BUF_SIZE, 2128 opt->socket_id); /* flags */ 2129 } 2130 2131 if (t->pool == NULL) { 2132 evt_err("failed to create mempool"); 2133 return -ENOMEM; 2134 } 2135 2136 return 0; 2137 } 2138 2139 void 2140 perf_mempool_destroy(struct evt_test *test, struct evt_options *opt) 2141 { 2142 RTE_SET_USED(opt); 2143 struct test_perf *t = evt_test_priv(test); 2144 2145 rte_mempool_free(t->pool); 2146 } 2147 2148 int 2149 perf_test_setup(struct evt_test *test, struct evt_options *opt) 2150 { 2151 void *test_perf; 2152 2153 test_perf = rte_zmalloc_socket(test->name, sizeof(struct test_perf), 2154 RTE_CACHE_LINE_SIZE, opt->socket_id); 2155 if (test_perf == NULL) { 2156 evt_err("failed to allocate test_perf memory"); 2157 goto nomem; 2158 } 2159 test->test_priv = test_perf; 2160 2161 struct test_perf *t = evt_test_priv(test); 2162 2163 if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 2164 t->outstand_pkts = opt->nb_timers * 2165 evt_nr_active_lcores(opt->plcores); 2166 t->nb_pkts = opt->nb_timers; 2167 } else { 2168 t->outstand_pkts = opt->nb_pkts * 2169 evt_nr_active_lcores(opt->plcores); 2170 t->nb_pkts = opt->nb_pkts; 2171 } 2172 2173 t->nb_workers = evt_nr_active_lcores(opt->wlcores); 2174 t->done = false; 2175 t->nb_flows = opt->nb_flows; 2176 t->result = EVT_TEST_FAILED; 2177 t->opt = opt; 2178 memcpy(t->sched_type_list, opt->sched_type_list, 2179 sizeof(opt->sched_type_list)); 2180 return 0; 2181 nomem: 2182 return -ENOMEM; 2183 } 2184 2185 void 2186 perf_test_destroy(struct evt_test *test, struct evt_options *opt) 2187 { 2188 RTE_SET_USED(opt); 2189 2190 rte_free(test->test_priv); 2191 } 2192