1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include "test_perf_common.h" 6 7 /* See http://doc.dpdk.org/guides/tools/testeventdev.html for test details */ 8 9 static inline int 10 atq_nb_event_queues(struct evt_options *opt) 11 { 12 /* nb_queues = number of producers */ 13 return opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR ? 14 rte_eth_dev_count_avail() : evt_nr_active_lcores(opt->plcores); 15 } 16 17 static __rte_always_inline void 18 atq_fwd_event(struct rte_event *const ev, uint8_t *const sched_type_list, 19 const uint8_t nb_stages) 20 { 21 ev->sub_event_type++; 22 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 23 ev->op = RTE_EVENT_OP_FORWARD; 24 ev->event_type = RTE_EVENT_TYPE_CPU; 25 } 26 27 static __rte_always_inline void 28 atq_fwd_event_vector(struct rte_event *const ev, uint8_t *const sched_type_list, 29 const uint8_t nb_stages) 30 { 31 ev->sub_event_type++; 32 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 33 ev->op = RTE_EVENT_OP_FORWARD; 34 ev->event_type = RTE_EVENT_TYPE_CPU_VECTOR; 35 } 36 37 static int 38 perf_atq_worker(void *arg, const int enable_fwd_latency) 39 { 40 uint16_t enq = 0, deq = 0; 41 struct rte_event ev; 42 PERF_WORKER_INIT; 43 44 while (t->done == false) { 45 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 46 47 if (!deq) { 48 rte_pause(); 49 continue; 50 } 51 52 if ((prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) && 53 (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 54 if (perf_handle_crypto_ev(&ev, &pe, enable_fwd_latency)) 55 continue; 56 } 57 58 stage = ev.sub_event_type % nb_stages; 59 if (enable_fwd_latency && !prod_timer_type && stage == 0) 60 /* first stage in pipeline, mark ts to compute fwd latency */ 61 perf_mark_fwd_latency(ev.event_ptr); 62 63 /* last stage in pipeline */ 64 if (unlikely(stage == laststage)) { 65 if (enable_fwd_latency) 66 cnt = perf_process_last_stage_latency(pool, prod_type, 67 &ev, w, bufs, sz, cnt); 68 else 69 cnt = perf_process_last_stage(pool, prod_type, &ev, w, 70 bufs, sz, cnt); 71 } else { 72 atq_fwd_event(&ev, sched_type_list, nb_stages); 73 do { 74 enq = rte_event_enqueue_burst(dev, port, &ev, 75 1); 76 } while (!enq && !t->done); 77 } 78 } 79 80 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 81 82 return 0; 83 } 84 85 static int 86 perf_atq_worker_burst(void *arg, const int enable_fwd_latency) 87 { 88 /* +1 to avoid prefetch out of array check */ 89 struct rte_event ev[BURST_SIZE + 1]; 90 uint16_t enq = 0, nb_rx = 0; 91 PERF_WORKER_INIT; 92 uint16_t i; 93 94 while (t->done == false) { 95 nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0); 96 97 if (!nb_rx) { 98 rte_pause(); 99 continue; 100 } 101 102 for (i = 0; i < nb_rx; i++) { 103 if ((prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) && 104 (ev[i].event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 105 if (perf_handle_crypto_ev(&ev[i], &pe, enable_fwd_latency)) 106 continue; 107 } 108 109 stage = ev[i].sub_event_type % nb_stages; 110 if (enable_fwd_latency && !prod_timer_type && stage == 0) { 111 rte_prefetch0(ev[i+1].event_ptr); 112 /* first stage in pipeline. 113 * mark time stamp to compute fwd latency 114 */ 115 perf_mark_fwd_latency(ev[i].event_ptr); 116 } 117 /* last stage in pipeline */ 118 if (unlikely(stage == laststage)) { 119 if (enable_fwd_latency) 120 cnt = perf_process_last_stage_latency(pool, 121 prod_type, &ev[i], w, bufs, sz, cnt); 122 else 123 cnt = perf_process_last_stage(pool, prod_type, 124 &ev[i], w, bufs, sz, cnt); 125 126 ev[i].op = RTE_EVENT_OP_RELEASE; 127 } else { 128 atq_fwd_event(&ev[i], sched_type_list, 129 nb_stages); 130 } 131 } 132 133 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx); 134 while ((enq < nb_rx) && !t->done) { 135 enq += rte_event_enqueue_burst(dev, port, 136 ev + enq, nb_rx - enq); 137 } 138 } 139 140 perf_worker_cleanup(pool, dev, port, ev, enq, nb_rx); 141 142 return 0; 143 } 144 145 static int 146 perf_atq_worker_vector(void *arg, const int enable_fwd_latency) 147 { 148 uint16_t enq = 0, deq = 0; 149 struct rte_event ev; 150 PERF_WORKER_INIT; 151 152 RTE_SET_USED(sz); 153 RTE_SET_USED(cnt); 154 RTE_SET_USED(prod_type); 155 156 while (t->done == false) { 157 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 158 159 if (!deq) 160 continue; 161 162 if (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV_VECTOR) { 163 if (perf_handle_crypto_vector_ev(&ev, &pe, enable_fwd_latency)) 164 continue; 165 } 166 167 stage = ev.sub_event_type % nb_stages; 168 /* First q in pipeline, mark timestamp to compute fwd latency */ 169 if (enable_fwd_latency && !prod_timer_type && stage == 0) 170 perf_mark_fwd_latency(pe); 171 172 /* Last stage in pipeline */ 173 if (unlikely(stage == laststage)) { 174 perf_process_vector_last_stage(pool, t->ca_op_pool, &ev, w, 175 enable_fwd_latency); 176 } else { 177 atq_fwd_event_vector(&ev, sched_type_list, nb_stages); 178 do { 179 enq = rte_event_enqueue_burst(dev, port, &ev, 1); 180 } while (!enq && !t->done); 181 } 182 } 183 184 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 185 186 return 0; 187 } 188 189 static int 190 worker_wrapper(void *arg) 191 { 192 struct worker_data *w = arg; 193 struct evt_options *opt = w->t->opt; 194 195 const bool burst = evt_has_burst_mode(w->dev_id); 196 const int fwd_latency = opt->fwd_latency; 197 198 /* allow compiler to optimize */ 199 if (opt->ena_vector && opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 200 return perf_atq_worker_vector(arg, fwd_latency); 201 else if (!burst && !fwd_latency) 202 return perf_atq_worker(arg, 0); 203 else if (!burst && fwd_latency) 204 return perf_atq_worker(arg, 1); 205 else if (burst && !fwd_latency) 206 return perf_atq_worker_burst(arg, 0); 207 else if (burst && fwd_latency) 208 return perf_atq_worker_burst(arg, 1); 209 210 rte_panic("invalid worker\n"); 211 } 212 213 static int 214 perf_atq_launch_lcores(struct evt_test *test, struct evt_options *opt) 215 { 216 return perf_launch_lcores(test, opt, worker_wrapper); 217 } 218 219 static int 220 perf_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt) 221 { 222 int ret; 223 uint8_t queue; 224 uint8_t nb_queues; 225 uint8_t nb_ports; 226 uint16_t prod; 227 struct rte_event_dev_info dev_info; 228 struct test_perf *t = evt_test_priv(test); 229 230 nb_ports = evt_nr_active_lcores(opt->wlcores); 231 nb_ports += (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR || 232 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) ? 0 : 233 evt_nr_active_lcores(opt->plcores); 234 235 nb_queues = atq_nb_event_queues(opt); 236 237 ret = rte_event_dev_info_get(opt->dev_id, &dev_info); 238 if (ret) { 239 evt_err("failed to get eventdev info %d", opt->dev_id); 240 return ret; 241 } 242 243 ret = evt_configure_eventdev(opt, nb_queues, nb_ports); 244 if (ret) { 245 evt_err("failed to configure eventdev %d", opt->dev_id); 246 return ret; 247 } 248 249 struct rte_event_queue_conf q_conf = { 250 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 251 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES, 252 .nb_atomic_flows = opt->nb_flows, 253 .nb_atomic_order_sequences = opt->nb_flows, 254 }; 255 /* queue configurations */ 256 for (queue = 0; queue < nb_queues; queue++) { 257 ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); 258 if (ret) { 259 evt_err("failed to setup queue=%d", queue); 260 return ret; 261 } 262 } 263 264 if (opt->wkr_deq_dep > dev_info.max_event_port_dequeue_depth) 265 opt->wkr_deq_dep = dev_info.max_event_port_dequeue_depth; 266 267 /* port configuration */ 268 const struct rte_event_port_conf p_conf = { 269 .dequeue_depth = opt->wkr_deq_dep, 270 .enqueue_depth = dev_info.max_event_port_dequeue_depth, 271 .new_event_threshold = dev_info.max_num_events, 272 }; 273 274 ret = perf_event_dev_port_setup(test, opt, 1 /* stride */, nb_queues, 275 &p_conf); 276 if (ret) 277 return ret; 278 279 if (!evt_has_distributed_sched(opt->dev_id)) { 280 uint32_t service_id; 281 rte_event_dev_service_id_get(opt->dev_id, &service_id); 282 ret = evt_service_setup(service_id); 283 if (ret) { 284 evt_err("No service lcore found to run event dev."); 285 return ret; 286 } 287 } 288 289 ret = rte_event_dev_start(opt->dev_id); 290 if (ret) { 291 evt_err("failed to start eventdev %d", opt->dev_id); 292 return ret; 293 } 294 295 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 296 RTE_ETH_FOREACH_DEV(prod) { 297 ret = rte_eth_dev_start(prod); 298 if (ret) { 299 evt_err("Ethernet dev [%d] failed to start. Using synthetic producer", 300 prod); 301 return ret; 302 } 303 304 ret = rte_event_eth_rx_adapter_start(prod); 305 if (ret) { 306 evt_err("Rx adapter[%d] start failed", prod); 307 return ret; 308 } 309 printf("%s: Port[%d] using Rx adapter[%d] started\n", 310 __func__, prod, prod); 311 } 312 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 313 for (prod = 0; prod < opt->nb_timer_adptrs; prod++) { 314 ret = rte_event_timer_adapter_start( 315 t->timer_adptr[prod]); 316 if (ret) { 317 evt_err("failed to Start event timer adapter %d" 318 , prod); 319 return ret; 320 } 321 } 322 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 323 uint8_t cdev_id, cdev_count; 324 325 cdev_count = rte_cryptodev_count(); 326 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 327 ret = rte_cryptodev_start(cdev_id); 328 if (ret) { 329 evt_err("Failed to start cryptodev %u", 330 cdev_id); 331 return ret; 332 } 333 } 334 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 335 uint8_t dma_dev_id = 0, dma_dev_count; 336 337 dma_dev_count = rte_dma_count_avail(); 338 if (dma_dev_count == 0) { 339 evt_err("No dma devices available\n"); 340 return -ENODEV; 341 } 342 343 ret = rte_dma_start(dma_dev_id); 344 if (ret) { 345 evt_err("Failed to start dmadev %u", dma_dev_id); 346 return ret; 347 } 348 } 349 350 return 0; 351 } 352 353 static void 354 perf_atq_opt_dump(struct evt_options *opt) 355 { 356 perf_opt_dump(opt, atq_nb_event_queues(opt)); 357 } 358 359 static int 360 perf_atq_opt_check(struct evt_options *opt) 361 { 362 return perf_opt_check(opt, atq_nb_event_queues(opt)); 363 } 364 365 static bool 366 perf_atq_capability_check(struct evt_options *opt) 367 { 368 struct rte_event_dev_info dev_info; 369 370 rte_event_dev_info_get(opt->dev_id, &dev_info); 371 if (dev_info.max_event_queues < atq_nb_event_queues(opt) || 372 dev_info.max_event_ports < perf_nb_event_ports(opt)) { 373 evt_err("not enough eventdev queues=%d/%d or ports=%d/%d", 374 atq_nb_event_queues(opt), dev_info.max_event_queues, 375 perf_nb_event_ports(opt), dev_info.max_event_ports); 376 } 377 if (!evt_has_all_types_queue(opt->dev_id)) 378 return false; 379 380 return true; 381 } 382 383 static const struct evt_test_ops perf_atq = { 384 .cap_check = perf_atq_capability_check, 385 .opt_check = perf_atq_opt_check, 386 .opt_dump = perf_atq_opt_dump, 387 .test_setup = perf_test_setup, 388 .ethdev_setup = perf_ethdev_setup, 389 .cryptodev_setup = perf_cryptodev_setup, 390 .dmadev_setup = perf_dmadev_setup, 391 .ethdev_rx_stop = perf_ethdev_rx_stop, 392 .mempool_setup = perf_mempool_setup, 393 .eventdev_setup = perf_atq_eventdev_setup, 394 .launch_lcores = perf_atq_launch_lcores, 395 .eventdev_destroy = perf_eventdev_destroy, 396 .mempool_destroy = perf_mempool_destroy, 397 .ethdev_destroy = perf_ethdev_destroy, 398 .cryptodev_destroy = perf_cryptodev_destroy, 399 .dmadev_destroy = perf_dmadev_destroy, 400 .test_result = perf_test_result, 401 .test_destroy = perf_test_destroy, 402 }; 403 404 EVT_TEST_REGISTER(perf_atq); 405