1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include "test_perf_common.h" 6 7 /* See http://doc.dpdk.org/guides/tools/testeventdev.html for test details */ 8 9 static inline int 10 atq_nb_event_queues(struct evt_options *opt) 11 { 12 /* nb_queues = number of producers */ 13 return opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR ? 14 rte_eth_dev_count_avail() : evt_nr_active_lcores(opt->plcores); 15 } 16 17 static __rte_always_inline void 18 atq_fwd_event(struct rte_event *const ev, uint8_t *const sched_type_list, 19 const uint8_t nb_stages) 20 { 21 ev->sub_event_type++; 22 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 23 ev->op = RTE_EVENT_OP_FORWARD; 24 ev->event_type = RTE_EVENT_TYPE_CPU; 25 } 26 27 static __rte_always_inline void 28 atq_fwd_event_vector(struct rte_event *const ev, uint8_t *const sched_type_list, 29 const uint8_t nb_stages) 30 { 31 ev->sub_event_type++; 32 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 33 ev->op = RTE_EVENT_OP_FORWARD; 34 ev->event_type = RTE_EVENT_TYPE_CPU_VECTOR; 35 } 36 37 static int 38 perf_atq_worker(void *arg, const int enable_fwd_latency) 39 { 40 uint16_t enq = 0, deq = 0; 41 struct rte_event ev; 42 PERF_WORKER_INIT; 43 44 RTE_SET_USED(pe); 45 while (t->done == false) { 46 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 47 48 if (!deq) { 49 rte_pause(); 50 continue; 51 } 52 53 if ((prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) && 54 (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 55 if (perf_handle_crypto_ev(&ev)) 56 continue; 57 } 58 59 stage = ev.sub_event_type % nb_stages; 60 if (enable_fwd_latency && !prod_timer_type && stage == 0) 61 /* first stage in pipeline, mark ts to compute fwd latency */ 62 perf_mark_fwd_latency(prod_type, &ev); 63 64 /* last stage in pipeline */ 65 if (unlikely(stage == laststage)) { 66 if (enable_fwd_latency) 67 cnt = perf_process_last_stage_latency(pool, prod_type, 68 &ev, w, bufs, sz, cnt); 69 else 70 cnt = perf_process_last_stage(pool, prod_type, &ev, w, 71 bufs, sz, cnt); 72 } else { 73 atq_fwd_event(&ev, sched_type_list, nb_stages); 74 do { 75 enq = rte_event_enqueue_burst(dev, port, &ev, 76 1); 77 } while (!enq && !t->done); 78 } 79 } 80 81 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 82 83 return 0; 84 } 85 86 static int 87 perf_atq_worker_burst(void *arg, const int enable_fwd_latency) 88 { 89 /* +1 to avoid prefetch out of array check */ 90 struct rte_event ev[BURST_SIZE + 1]; 91 uint16_t enq = 0, nb_rx = 0; 92 PERF_WORKER_INIT; 93 uint16_t i; 94 95 RTE_SET_USED(pe); 96 while (t->done == false) { 97 nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0); 98 99 if (!nb_rx) { 100 rte_pause(); 101 continue; 102 } 103 104 for (i = 0; i < nb_rx; i++) { 105 if ((prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) && 106 (ev[i].event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 107 if (perf_handle_crypto_ev(&ev[i])) 108 continue; 109 } 110 111 stage = ev[i].sub_event_type % nb_stages; 112 if (enable_fwd_latency && !prod_timer_type && stage == 0) { 113 rte_prefetch0(ev[i+1].event_ptr); 114 /* first stage in pipeline. 115 * mark time stamp to compute fwd latency 116 */ 117 perf_mark_fwd_latency(prod_type, &ev[i]); 118 } 119 /* last stage in pipeline */ 120 if (unlikely(stage == laststage)) { 121 if (enable_fwd_latency) 122 cnt = perf_process_last_stage_latency(pool, 123 prod_type, &ev[i], w, bufs, sz, cnt); 124 else 125 cnt = perf_process_last_stage(pool, prod_type, 126 &ev[i], w, bufs, sz, cnt); 127 128 ev[i].op = RTE_EVENT_OP_RELEASE; 129 } else { 130 atq_fwd_event(&ev[i], sched_type_list, 131 nb_stages); 132 } 133 } 134 135 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx); 136 while ((enq < nb_rx) && !t->done) { 137 enq += rte_event_enqueue_burst(dev, port, 138 ev + enq, nb_rx - enq); 139 } 140 } 141 142 perf_worker_cleanup(pool, dev, port, ev, enq, nb_rx); 143 144 return 0; 145 } 146 147 static int 148 perf_atq_worker_vector(void *arg, const int enable_fwd_latency) 149 { 150 uint16_t enq = 0, deq = 0; 151 struct rte_event ev; 152 PERF_WORKER_INIT; 153 154 RTE_SET_USED(sz); 155 RTE_SET_USED(cnt); 156 RTE_SET_USED(prod_type); 157 158 while (t->done == false) { 159 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 160 161 if (!deq) 162 continue; 163 164 if (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV_VECTOR) { 165 if (perf_handle_crypto_vector_ev(&ev, &pe, enable_fwd_latency)) 166 continue; 167 } 168 169 stage = ev.sub_event_type % nb_stages; 170 /* First q in pipeline, mark timestamp to compute fwd latency */ 171 if (enable_fwd_latency && !prod_timer_type && stage == 0) 172 pe->timestamp = rte_get_timer_cycles(); 173 174 /* Last stage in pipeline */ 175 if (unlikely(stage == laststage)) { 176 perf_process_vector_last_stage(pool, t->ca_op_pool, &ev, w, 177 enable_fwd_latency); 178 } else { 179 atq_fwd_event_vector(&ev, sched_type_list, nb_stages); 180 do { 181 enq = rte_event_enqueue_burst(dev, port, &ev, 1); 182 } while (!enq && !t->done); 183 } 184 } 185 186 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 187 188 return 0; 189 } 190 191 static int 192 worker_wrapper(void *arg) 193 { 194 struct worker_data *w = arg; 195 struct evt_options *opt = w->t->opt; 196 197 const bool burst = evt_has_burst_mode(w->dev_id); 198 const int fwd_latency = opt->fwd_latency; 199 200 /* allow compiler to optimize */ 201 if (opt->ena_vector && opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 202 return perf_atq_worker_vector(arg, fwd_latency); 203 else if (!burst && !fwd_latency) 204 return perf_atq_worker(arg, 0); 205 else if (!burst && fwd_latency) 206 return perf_atq_worker(arg, 1); 207 else if (burst && !fwd_latency) 208 return perf_atq_worker_burst(arg, 0); 209 else if (burst && fwd_latency) 210 return perf_atq_worker_burst(arg, 1); 211 212 rte_panic("invalid worker\n"); 213 } 214 215 static int 216 perf_atq_launch_lcores(struct evt_test *test, struct evt_options *opt) 217 { 218 return perf_launch_lcores(test, opt, worker_wrapper); 219 } 220 221 static int 222 perf_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt) 223 { 224 int ret; 225 uint8_t queue; 226 uint8_t nb_queues; 227 uint8_t nb_ports; 228 uint16_t prod; 229 struct rte_event_dev_info dev_info; 230 struct test_perf *t = evt_test_priv(test); 231 232 nb_ports = evt_nr_active_lcores(opt->wlcores); 233 nb_ports += (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR || 234 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) ? 0 : 235 evt_nr_active_lcores(opt->plcores); 236 237 nb_queues = atq_nb_event_queues(opt); 238 239 ret = rte_event_dev_info_get(opt->dev_id, &dev_info); 240 if (ret) { 241 evt_err("failed to get eventdev info %d", opt->dev_id); 242 return ret; 243 } 244 245 ret = evt_configure_eventdev(opt, nb_queues, nb_ports); 246 if (ret) { 247 evt_err("failed to configure eventdev %d", opt->dev_id); 248 return ret; 249 } 250 251 struct rte_event_queue_conf q_conf = { 252 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 253 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES, 254 .nb_atomic_flows = opt->nb_flows, 255 .nb_atomic_order_sequences = opt->nb_flows, 256 }; 257 /* queue configurations */ 258 for (queue = 0; queue < nb_queues; queue++) { 259 ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); 260 if (ret) { 261 evt_err("failed to setup queue=%d", queue); 262 return ret; 263 } 264 } 265 266 if (opt->wkr_deq_dep > dev_info.max_event_port_dequeue_depth) 267 opt->wkr_deq_dep = dev_info.max_event_port_dequeue_depth; 268 269 /* port configuration */ 270 const struct rte_event_port_conf p_conf = { 271 .dequeue_depth = opt->wkr_deq_dep, 272 .enqueue_depth = dev_info.max_event_port_dequeue_depth, 273 .new_event_threshold = dev_info.max_num_events, 274 }; 275 276 ret = perf_event_dev_port_setup(test, opt, 1 /* stride */, nb_queues, 277 &p_conf); 278 if (ret) 279 return ret; 280 281 if (!evt_has_distributed_sched(opt->dev_id)) { 282 uint32_t service_id; 283 rte_event_dev_service_id_get(opt->dev_id, &service_id); 284 ret = evt_service_setup(service_id); 285 if (ret) { 286 evt_err("No service lcore found to run event dev."); 287 return ret; 288 } 289 } 290 291 ret = rte_event_dev_start(opt->dev_id); 292 if (ret) { 293 evt_err("failed to start eventdev %d", opt->dev_id); 294 return ret; 295 } 296 297 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 298 RTE_ETH_FOREACH_DEV(prod) { 299 ret = rte_eth_dev_start(prod); 300 if (ret) { 301 evt_err("Ethernet dev [%d] failed to start. Using synthetic producer", 302 prod); 303 return ret; 304 } 305 306 ret = rte_event_eth_rx_adapter_start(prod); 307 if (ret) { 308 evt_err("Rx adapter[%d] start failed", prod); 309 return ret; 310 } 311 printf("%s: Port[%d] using Rx adapter[%d] started\n", 312 __func__, prod, prod); 313 } 314 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 315 for (prod = 0; prod < opt->nb_timer_adptrs; prod++) { 316 ret = rte_event_timer_adapter_start( 317 t->timer_adptr[prod]); 318 if (ret) { 319 evt_err("failed to Start event timer adapter %d" 320 , prod); 321 return ret; 322 } 323 } 324 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 325 uint8_t cdev_id, cdev_count; 326 327 cdev_count = rte_cryptodev_count(); 328 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 329 ret = rte_cryptodev_start(cdev_id); 330 if (ret) { 331 evt_err("Failed to start cryptodev %u", 332 cdev_id); 333 return ret; 334 } 335 } 336 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR) { 337 uint8_t dma_dev_id = 0, dma_dev_count; 338 339 dma_dev_count = rte_dma_count_avail(); 340 if (dma_dev_count == 0) { 341 evt_err("No dma devices available\n"); 342 return -ENODEV; 343 } 344 345 ret = rte_dma_start(dma_dev_id); 346 if (ret) { 347 evt_err("Failed to start dmadev %u", dma_dev_id); 348 return ret; 349 } 350 } 351 352 return 0; 353 } 354 355 static void 356 perf_atq_opt_dump(struct evt_options *opt) 357 { 358 perf_opt_dump(opt, atq_nb_event_queues(opt)); 359 } 360 361 static int 362 perf_atq_opt_check(struct evt_options *opt) 363 { 364 return perf_opt_check(opt, atq_nb_event_queues(opt)); 365 } 366 367 static bool 368 perf_atq_capability_check(struct evt_options *opt) 369 { 370 struct rte_event_dev_info dev_info; 371 372 rte_event_dev_info_get(opt->dev_id, &dev_info); 373 if (dev_info.max_event_queues < atq_nb_event_queues(opt) || 374 dev_info.max_event_ports < perf_nb_event_ports(opt)) { 375 evt_err("not enough eventdev queues=%d/%d or ports=%d/%d", 376 atq_nb_event_queues(opt), dev_info.max_event_queues, 377 perf_nb_event_ports(opt), dev_info.max_event_ports); 378 } 379 if (!evt_has_all_types_queue(opt->dev_id)) 380 return false; 381 382 return true; 383 } 384 385 static const struct evt_test_ops perf_atq = { 386 .cap_check = perf_atq_capability_check, 387 .opt_check = perf_atq_opt_check, 388 .opt_dump = perf_atq_opt_dump, 389 .test_setup = perf_test_setup, 390 .ethdev_setup = perf_ethdev_setup, 391 .cryptodev_setup = perf_cryptodev_setup, 392 .dmadev_setup = perf_dmadev_setup, 393 .ethdev_rx_stop = perf_ethdev_rx_stop, 394 .mempool_setup = perf_mempool_setup, 395 .eventdev_setup = perf_atq_eventdev_setup, 396 .launch_lcores = perf_atq_launch_lcores, 397 .eventdev_destroy = perf_eventdev_destroy, 398 .mempool_destroy = perf_mempool_destroy, 399 .ethdev_destroy = perf_ethdev_destroy, 400 .cryptodev_destroy = perf_cryptodev_destroy, 401 .dmadev_destroy = perf_dmadev_destroy, 402 .test_result = perf_test_result, 403 .test_destroy = perf_test_destroy, 404 }; 405 406 EVT_TEST_REGISTER(perf_atq); 407