1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include "test_perf_common.h" 6 7 /* See http://doc.dpdk.org/guides/tools/testeventdev.html for test details */ 8 9 static inline int 10 atq_nb_event_queues(struct evt_options *opt) 11 { 12 /* nb_queues = number of producers */ 13 return opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR ? 14 rte_eth_dev_count_avail() : evt_nr_active_lcores(opt->plcores); 15 } 16 17 static __rte_always_inline void 18 atq_fwd_event(struct rte_event *const ev, uint8_t *const sched_type_list, 19 const uint8_t nb_stages) 20 { 21 ev->sub_event_type++; 22 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 23 ev->op = RTE_EVENT_OP_FORWARD; 24 ev->event_type = RTE_EVENT_TYPE_CPU; 25 } 26 27 static __rte_always_inline void 28 atq_fwd_event_vector(struct rte_event *const ev, uint8_t *const sched_type_list, 29 const uint8_t nb_stages) 30 { 31 ev->sub_event_type++; 32 ev->sched_type = sched_type_list[ev->sub_event_type % nb_stages]; 33 ev->op = RTE_EVENT_OP_FORWARD; 34 ev->event_type = RTE_EVENT_TYPE_CPU_VECTOR; 35 } 36 37 static int 38 perf_atq_worker(void *arg, const int enable_fwd_latency) 39 { 40 uint16_t enq = 0, deq = 0; 41 struct rte_event ev; 42 PERF_WORKER_INIT; 43 44 while (t->done == false) { 45 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 46 47 if (!deq) { 48 rte_pause(); 49 continue; 50 } 51 52 if (prod_crypto_type && (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 53 if (perf_handle_crypto_ev(&ev, &pe, enable_fwd_latency)) 54 continue; 55 } 56 57 stage = ev.sub_event_type % nb_stages; 58 if (enable_fwd_latency && !prod_timer_type && stage == 0) 59 /* first stage in pipeline, mark ts to compute fwd latency */ 60 perf_mark_fwd_latency(ev.event_ptr); 61 62 /* last stage in pipeline */ 63 if (unlikely(stage == laststage)) { 64 if (enable_fwd_latency) 65 cnt = perf_process_last_stage_latency(pool, prod_crypto_type, 66 &ev, w, bufs, sz, cnt); 67 else 68 cnt = perf_process_last_stage(pool, prod_crypto_type, &ev, w, 69 bufs, sz, cnt); 70 } else { 71 atq_fwd_event(&ev, sched_type_list, nb_stages); 72 do { 73 enq = rte_event_enqueue_burst(dev, port, &ev, 74 1); 75 } while (!enq && !t->done); 76 } 77 } 78 79 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 80 81 return 0; 82 } 83 84 static int 85 perf_atq_worker_burst(void *arg, const int enable_fwd_latency) 86 { 87 /* +1 to avoid prefetch out of array check */ 88 struct rte_event ev[BURST_SIZE + 1]; 89 uint16_t enq = 0, nb_rx = 0; 90 PERF_WORKER_INIT; 91 uint16_t i; 92 93 while (t->done == false) { 94 nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0); 95 96 if (!nb_rx) { 97 rte_pause(); 98 continue; 99 } 100 101 for (i = 0; i < nb_rx; i++) { 102 if (prod_crypto_type && (ev[i].event_type == RTE_EVENT_TYPE_CRYPTODEV)) { 103 if (perf_handle_crypto_ev(&ev[i], &pe, enable_fwd_latency)) 104 continue; 105 } 106 107 stage = ev[i].sub_event_type % nb_stages; 108 if (enable_fwd_latency && !prod_timer_type && stage == 0) { 109 rte_prefetch0(ev[i+1].event_ptr); 110 /* first stage in pipeline. 111 * mark time stamp to compute fwd latency 112 */ 113 perf_mark_fwd_latency(ev[i].event_ptr); 114 } 115 /* last stage in pipeline */ 116 if (unlikely(stage == laststage)) { 117 if (enable_fwd_latency) 118 cnt = perf_process_last_stage_latency(pool, 119 prod_crypto_type, &ev[i], w, bufs, sz, cnt); 120 else 121 cnt = perf_process_last_stage(pool, prod_crypto_type, 122 &ev[i], w, bufs, sz, cnt); 123 124 ev[i].op = RTE_EVENT_OP_RELEASE; 125 } else { 126 atq_fwd_event(&ev[i], sched_type_list, 127 nb_stages); 128 } 129 } 130 131 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx); 132 while ((enq < nb_rx) && !t->done) { 133 enq += rte_event_enqueue_burst(dev, port, 134 ev + enq, nb_rx - enq); 135 } 136 } 137 138 perf_worker_cleanup(pool, dev, port, ev, enq, nb_rx); 139 140 return 0; 141 } 142 143 static int 144 perf_atq_worker_vector(void *arg, const int enable_fwd_latency) 145 { 146 uint16_t enq = 0, deq = 0; 147 struct rte_event ev; 148 PERF_WORKER_INIT; 149 150 RTE_SET_USED(sz); 151 RTE_SET_USED(cnt); 152 RTE_SET_USED(prod_crypto_type); 153 154 while (t->done == false) { 155 deq = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 156 157 if (!deq) 158 continue; 159 160 if (ev.event_type == RTE_EVENT_TYPE_CRYPTODEV_VECTOR) { 161 if (perf_handle_crypto_vector_ev(&ev, &pe, enable_fwd_latency)) 162 continue; 163 } 164 165 stage = ev.sub_event_type % nb_stages; 166 /* First q in pipeline, mark timestamp to compute fwd latency */ 167 if (enable_fwd_latency && !prod_timer_type && stage == 0) 168 perf_mark_fwd_latency(pe); 169 170 /* Last stage in pipeline */ 171 if (unlikely(stage == laststage)) { 172 perf_process_vector_last_stage(pool, t->ca_op_pool, &ev, w, 173 enable_fwd_latency); 174 } else { 175 atq_fwd_event_vector(&ev, sched_type_list, nb_stages); 176 do { 177 enq = rte_event_enqueue_burst(dev, port, &ev, 1); 178 } while (!enq && !t->done); 179 } 180 } 181 182 perf_worker_cleanup(pool, dev, port, &ev, enq, deq); 183 184 return 0; 185 } 186 187 static int 188 worker_wrapper(void *arg) 189 { 190 struct worker_data *w = arg; 191 struct evt_options *opt = w->t->opt; 192 193 const bool burst = evt_has_burst_mode(w->dev_id); 194 const int fwd_latency = opt->fwd_latency; 195 196 /* allow compiler to optimize */ 197 if (opt->ena_vector && opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) 198 return perf_atq_worker_vector(arg, fwd_latency); 199 else if (!burst && !fwd_latency) 200 return perf_atq_worker(arg, 0); 201 else if (!burst && fwd_latency) 202 return perf_atq_worker(arg, 1); 203 else if (burst && !fwd_latency) 204 return perf_atq_worker_burst(arg, 0); 205 else if (burst && fwd_latency) 206 return perf_atq_worker_burst(arg, 1); 207 208 rte_panic("invalid worker\n"); 209 } 210 211 static int 212 perf_atq_launch_lcores(struct evt_test *test, struct evt_options *opt) 213 { 214 return perf_launch_lcores(test, opt, worker_wrapper); 215 } 216 217 static int 218 perf_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt) 219 { 220 int ret; 221 uint8_t queue; 222 uint8_t nb_queues; 223 uint8_t nb_ports; 224 uint16_t prod; 225 struct rte_event_dev_info dev_info; 226 struct test_perf *t = evt_test_priv(test); 227 228 nb_ports = evt_nr_active_lcores(opt->wlcores); 229 nb_ports += (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR || 230 opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) ? 0 : 231 evt_nr_active_lcores(opt->plcores); 232 233 nb_queues = atq_nb_event_queues(opt); 234 235 ret = rte_event_dev_info_get(opt->dev_id, &dev_info); 236 if (ret) { 237 evt_err("failed to get eventdev info %d", opt->dev_id); 238 return ret; 239 } 240 241 ret = evt_configure_eventdev(opt, nb_queues, nb_ports); 242 if (ret) { 243 evt_err("failed to configure eventdev %d", opt->dev_id); 244 return ret; 245 } 246 247 struct rte_event_queue_conf q_conf = { 248 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 249 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES, 250 .nb_atomic_flows = opt->nb_flows, 251 .nb_atomic_order_sequences = opt->nb_flows, 252 }; 253 /* queue configurations */ 254 for (queue = 0; queue < nb_queues; queue++) { 255 ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); 256 if (ret) { 257 evt_err("failed to setup queue=%d", queue); 258 return ret; 259 } 260 } 261 262 if (opt->wkr_deq_dep > dev_info.max_event_port_dequeue_depth) 263 opt->wkr_deq_dep = dev_info.max_event_port_dequeue_depth; 264 265 /* port configuration */ 266 const struct rte_event_port_conf p_conf = { 267 .dequeue_depth = opt->wkr_deq_dep, 268 .enqueue_depth = dev_info.max_event_port_dequeue_depth, 269 .new_event_threshold = dev_info.max_num_events, 270 }; 271 272 ret = perf_event_dev_port_setup(test, opt, 1 /* stride */, nb_queues, 273 &p_conf); 274 if (ret) 275 return ret; 276 277 if (!evt_has_distributed_sched(opt->dev_id)) { 278 uint32_t service_id; 279 rte_event_dev_service_id_get(opt->dev_id, &service_id); 280 ret = evt_service_setup(service_id); 281 if (ret) { 282 evt_err("No service lcore found to run event dev."); 283 return ret; 284 } 285 } 286 287 ret = rte_event_dev_start(opt->dev_id); 288 if (ret) { 289 evt_err("failed to start eventdev %d", opt->dev_id); 290 return ret; 291 } 292 293 if (opt->prod_type == EVT_PROD_TYPE_ETH_RX_ADPTR) { 294 RTE_ETH_FOREACH_DEV(prod) { 295 ret = rte_eth_dev_start(prod); 296 if (ret) { 297 evt_err("Ethernet dev [%d] failed to start. Using synthetic producer", 298 prod); 299 return ret; 300 } 301 302 ret = rte_event_eth_rx_adapter_start(prod); 303 if (ret) { 304 evt_err("Rx adapter[%d] start failed", prod); 305 return ret; 306 } 307 printf("%s: Port[%d] using Rx adapter[%d] started\n", 308 __func__, prod, prod); 309 } 310 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR) { 311 for (prod = 0; prod < opt->nb_timer_adptrs; prod++) { 312 ret = rte_event_timer_adapter_start( 313 t->timer_adptr[prod]); 314 if (ret) { 315 evt_err("failed to Start event timer adapter %d" 316 , prod); 317 return ret; 318 } 319 } 320 } else if (opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) { 321 uint8_t cdev_id, cdev_count; 322 323 cdev_count = rte_cryptodev_count(); 324 for (cdev_id = 0; cdev_id < cdev_count; cdev_id++) { 325 ret = rte_cryptodev_start(cdev_id); 326 if (ret) { 327 evt_err("Failed to start cryptodev %u", 328 cdev_id); 329 return ret; 330 } 331 } 332 } 333 334 return 0; 335 } 336 337 static void 338 perf_atq_opt_dump(struct evt_options *opt) 339 { 340 perf_opt_dump(opt, atq_nb_event_queues(opt)); 341 } 342 343 static int 344 perf_atq_opt_check(struct evt_options *opt) 345 { 346 return perf_opt_check(opt, atq_nb_event_queues(opt)); 347 } 348 349 static bool 350 perf_atq_capability_check(struct evt_options *opt) 351 { 352 struct rte_event_dev_info dev_info; 353 354 rte_event_dev_info_get(opt->dev_id, &dev_info); 355 if (dev_info.max_event_queues < atq_nb_event_queues(opt) || 356 dev_info.max_event_ports < perf_nb_event_ports(opt)) { 357 evt_err("not enough eventdev queues=%d/%d or ports=%d/%d", 358 atq_nb_event_queues(opt), dev_info.max_event_queues, 359 perf_nb_event_ports(opt), dev_info.max_event_ports); 360 } 361 if (!evt_has_all_types_queue(opt->dev_id)) 362 return false; 363 364 return true; 365 } 366 367 static const struct evt_test_ops perf_atq = { 368 .cap_check = perf_atq_capability_check, 369 .opt_check = perf_atq_opt_check, 370 .opt_dump = perf_atq_opt_dump, 371 .test_setup = perf_test_setup, 372 .ethdev_setup = perf_ethdev_setup, 373 .cryptodev_setup = perf_cryptodev_setup, 374 .ethdev_rx_stop = perf_ethdev_rx_stop, 375 .mempool_setup = perf_mempool_setup, 376 .eventdev_setup = perf_atq_eventdev_setup, 377 .launch_lcores = perf_atq_launch_lcores, 378 .eventdev_destroy = perf_eventdev_destroy, 379 .mempool_destroy = perf_mempool_destroy, 380 .ethdev_destroy = perf_ethdev_destroy, 381 .cryptodev_destroy = perf_cryptodev_destroy, 382 .test_result = perf_test_result, 383 .test_destroy = perf_test_destroy, 384 }; 385 386 EVT_TEST_REGISTER(perf_atq); 387