1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 #include <rte_malloc.h> 5 #include <rte_cycles.h> 6 #include <rte_crypto.h> 7 #include <rte_cryptodev.h> 8 9 #include "cperf_test_latency.h" 10 #include "cperf_ops.h" 11 #include "cperf_test_common.h" 12 13 struct cperf_op_result { 14 uint64_t tsc_start; 15 uint64_t tsc_end; 16 enum rte_crypto_op_status status; 17 }; 18 19 struct cperf_latency_ctx { 20 uint8_t dev_id; 21 uint16_t qp_id; 22 uint8_t lcore_id; 23 24 struct rte_mempool *pool; 25 26 void *sess; 27 uint8_t sess_owner; 28 29 cperf_populate_ops_t populate_ops; 30 31 uint32_t src_buf_offset; 32 uint32_t dst_buf_offset; 33 34 const struct cperf_options *options; 35 const struct cperf_test_vector *test_vector; 36 struct cperf_op_result *res; 37 }; 38 39 struct priv_op_data { 40 struct cperf_op_result *result; 41 }; 42 43 static void 44 cperf_latency_test_free(struct cperf_latency_ctx *ctx) 45 { 46 if (ctx == NULL) 47 return; 48 49 if (ctx->sess != NULL && ctx->sess_owner) { 50 if (cperf_is_asym_test(ctx->options)) 51 rte_cryptodev_asym_session_free(ctx->dev_id, ctx->sess); 52 #ifdef RTE_LIB_SECURITY 53 else if (ctx->options->op_type == CPERF_PDCP || 54 ctx->options->op_type == CPERF_DOCSIS || 55 ctx->options->op_type == CPERF_TLS || 56 ctx->options->op_type == CPERF_IPSEC) { 57 void *sec_ctx = rte_cryptodev_get_sec_ctx(ctx->dev_id); 58 rte_security_session_destroy(sec_ctx, ctx->sess); 59 } 60 #endif 61 else 62 rte_cryptodev_sym_session_free(ctx->dev_id, ctx->sess); 63 } 64 65 rte_mempool_free(ctx->pool); 66 rte_free(ctx->res); 67 rte_free(ctx); 68 } 69 70 void * 71 cperf_latency_test_constructor(struct rte_mempool *sess_mp, 72 uint8_t dev_id, uint16_t qp_id, 73 const struct cperf_options *options, 74 const struct cperf_test_vector *test_vector, 75 const struct cperf_op_fns *op_fns, 76 void **sess) 77 { 78 struct cperf_latency_ctx *ctx = NULL; 79 size_t extra_op_priv_size = sizeof(struct priv_op_data); 80 81 ctx = rte_malloc(NULL, sizeof(struct cperf_latency_ctx), 0); 82 if (ctx == NULL) 83 goto err; 84 85 ctx->dev_id = dev_id; 86 ctx->qp_id = qp_id; 87 88 ctx->populate_ops = op_fns->populate_ops; 89 ctx->options = options; 90 ctx->test_vector = test_vector; 91 92 /* IV goes at the end of the crypto operation */ 93 uint16_t iv_offset = sizeof(struct rte_crypto_op) + 94 sizeof(struct rte_crypto_sym_op) + 95 sizeof(struct cperf_op_result *); 96 97 98 if (*sess != NULL) { 99 ctx->sess = *sess; 100 ctx->sess_owner = false; 101 } else { 102 ctx->sess = op_fns->sess_create(sess_mp, dev_id, options, test_vector, 103 iv_offset); 104 if (ctx->sess == NULL) 105 goto err; 106 *sess = ctx->sess; 107 ctx->sess_owner = true; 108 } 109 110 if (cperf_alloc_common_memory(options, test_vector, dev_id, qp_id, 111 extra_op_priv_size, 112 &ctx->src_buf_offset, &ctx->dst_buf_offset, 113 &ctx->pool) < 0) 114 goto err; 115 116 ctx->res = rte_malloc(NULL, sizeof(struct cperf_op_result) * 117 ctx->options->total_ops, 0); 118 119 if (ctx->res == NULL) 120 goto err; 121 122 return ctx; 123 err: 124 cperf_latency_test_free(ctx); 125 126 return NULL; 127 } 128 129 static inline void 130 store_timestamp(struct rte_crypto_op *op, uint64_t timestamp) 131 { 132 struct priv_op_data *priv_data; 133 134 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) 135 priv_data = (struct priv_op_data *) (op->sym + 1); 136 else 137 priv_data = (struct priv_op_data *) (op->asym + 1); 138 139 priv_data->result->status = op->status; 140 priv_data->result->tsc_end = timestamp; 141 } 142 143 int 144 cperf_latency_test_runner(void *arg) 145 { 146 struct cperf_latency_ctx *ctx = arg; 147 uint16_t test_burst_size; 148 uint8_t burst_size_idx = 0; 149 uint32_t imix_idx = 0; 150 int ret = 0; 151 152 static RTE_ATOMIC(uint16_t) display_once; 153 154 if (ctx == NULL) 155 return 0; 156 157 struct rte_crypto_op *ops[ctx->options->max_burst_size]; 158 struct rte_crypto_op *ops_processed[ctx->options->max_burst_size]; 159 uint64_t i; 160 struct priv_op_data *priv_data; 161 162 uint32_t lcore = rte_lcore_id(); 163 164 #ifdef CPERF_LINEARIZATION_ENABLE 165 struct rte_cryptodev_info dev_info; 166 int linearize = 0; 167 168 /* Check if source mbufs require coalescing */ 169 if (ctx->options->segment_sz < ctx->options->max_buffer_size) { 170 rte_cryptodev_info_get(ctx->dev_id, &dev_info); 171 if ((dev_info.feature_flags & 172 RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER) == 0) 173 linearize = 1; 174 } 175 #endif /* CPERF_LINEARIZATION_ENABLE */ 176 177 ctx->lcore_id = lcore; 178 179 /* Warm up the host CPU before starting the test */ 180 for (i = 0; i < ctx->options->total_ops; i++) 181 rte_cryptodev_enqueue_burst(ctx->dev_id, ctx->qp_id, NULL, 0); 182 183 /* Get first size from range or list */ 184 if (ctx->options->inc_burst_size != 0) 185 test_burst_size = ctx->options->min_burst_size; 186 else 187 test_burst_size = ctx->options->burst_size_list[0]; 188 189 uint16_t iv_offset = sizeof(struct rte_crypto_op) + 190 sizeof(struct rte_crypto_sym_op) + 191 sizeof(struct cperf_op_result *); 192 193 while (test_burst_size <= ctx->options->max_burst_size) { 194 uint64_t ops_enqd = 0, ops_deqd = 0; 195 uint64_t b_idx = 0; 196 197 uint64_t tsc_val, tsc_end, tsc_start; 198 uint64_t tsc_max = 0, tsc_min = ~0UL, tsc_tot = 0, tsc_idx = 0; 199 uint64_t enqd_max = 0, enqd_min = ~0UL, enqd_tot = 0; 200 uint64_t deqd_max = 0, deqd_min = ~0UL, deqd_tot = 0; 201 202 while (enqd_tot < ctx->options->total_ops) { 203 204 uint16_t burst_size = ((enqd_tot + test_burst_size) 205 <= ctx->options->total_ops) ? 206 test_burst_size : 207 ctx->options->total_ops - 208 enqd_tot; 209 210 /* Allocate objects containing crypto operations and mbufs */ 211 if (rte_mempool_get_bulk(ctx->pool, (void **)ops, 212 burst_size) != 0) { 213 RTE_LOG(ERR, USER1, 214 "Failed to allocate more crypto operations " 215 "from the crypto operation pool.\n" 216 "Consider increasing the pool size " 217 "with --pool-sz\n"); 218 return -1; 219 } 220 221 /* Setup crypto op, attach mbuf etc */ 222 (ctx->populate_ops)(ops, ctx->src_buf_offset, 223 ctx->dst_buf_offset, 224 burst_size, ctx->sess, ctx->options, 225 ctx->test_vector, iv_offset, 226 &imix_idx, &tsc_start); 227 228 /* Populate the mbuf with the test vector */ 229 if (!cperf_is_asym_test(ctx->options)) 230 for (i = 0; i < burst_size; i++) 231 cperf_mbuf_set(ops[i]->sym->m_src, 232 ctx->options, 233 ctx->test_vector); 234 235 tsc_start = rte_rdtsc_precise(); 236 237 #ifdef CPERF_LINEARIZATION_ENABLE 238 if (linearize) { 239 /* PMD doesn't support scatter-gather and source buffer 240 * is segmented. 241 * We need to linearize it before enqueuing. 242 */ 243 for (i = 0; i < burst_size; i++) 244 rte_pktmbuf_linearize(ops[i]->sym->m_src); 245 } 246 #endif /* CPERF_LINEARIZATION_ENABLE */ 247 248 /* Enqueue burst of ops on crypto device */ 249 ops_enqd = rte_cryptodev_enqueue_burst(ctx->dev_id, ctx->qp_id, 250 ops, burst_size); 251 252 /* Dequeue processed burst of ops from crypto device */ 253 ops_deqd = rte_cryptodev_dequeue_burst(ctx->dev_id, ctx->qp_id, 254 ops_processed, test_burst_size); 255 256 tsc_end = rte_rdtsc_precise(); 257 258 /* Free memory for not enqueued operations */ 259 if (ops_enqd != burst_size) 260 rte_mempool_put_bulk(ctx->pool, 261 (void **)&ops[ops_enqd], 262 burst_size - ops_enqd); 263 264 for (i = 0; i < ops_enqd; i++) { 265 ctx->res[tsc_idx].tsc_start = tsc_start; 266 /* 267 * Private data structure starts after the end of the 268 * rte_crypto_sym_op (or rte_crypto_asym_op) structure. 269 */ 270 if (ops[i]->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) 271 priv_data = (struct priv_op_data *) (ops[i]->sym + 1); 272 else 273 priv_data = (struct priv_op_data *) (ops[i]->asym + 1); 274 275 priv_data->result = (void *)&ctx->res[tsc_idx]; 276 tsc_idx++; 277 } 278 279 if (likely(ops_deqd)) { 280 for (i = 0; i < ops_deqd; i++) { 281 struct rte_crypto_op *op = ops_processed[i]; 282 283 if (op->status != RTE_CRYPTO_OP_STATUS_SUCCESS) 284 ret = -1; 285 286 store_timestamp(ops_processed[i], tsc_end); 287 } 288 289 /* Free crypto ops so they can be reused. */ 290 rte_mempool_put_bulk(ctx->pool, 291 (void **)ops_processed, ops_deqd); 292 293 deqd_tot += ops_deqd; 294 deqd_max = RTE_MAX(ops_deqd, deqd_max); 295 deqd_min = RTE_MIN(ops_deqd, deqd_min); 296 } 297 298 enqd_tot += ops_enqd; 299 enqd_max = RTE_MAX(ops_enqd, enqd_max); 300 enqd_min = RTE_MIN(ops_enqd, enqd_min); 301 302 b_idx++; 303 } 304 305 /* Dequeue any operations still in the crypto device */ 306 while (deqd_tot < ctx->options->total_ops) { 307 /* Sending 0 length burst to flush sw crypto device */ 308 rte_cryptodev_enqueue_burst(ctx->dev_id, ctx->qp_id, NULL, 0); 309 310 /* dequeue burst */ 311 ops_deqd = rte_cryptodev_dequeue_burst(ctx->dev_id, ctx->qp_id, 312 ops_processed, test_burst_size); 313 314 tsc_end = rte_rdtsc_precise(); 315 316 if (ops_deqd != 0) { 317 for (i = 0; i < ops_deqd; i++) { 318 struct rte_crypto_op *op = ops_processed[i]; 319 320 if (op->status != RTE_CRYPTO_OP_STATUS_SUCCESS) 321 ret = -1; 322 323 store_timestamp(ops_processed[i], tsc_end); 324 } 325 326 rte_mempool_put_bulk(ctx->pool, 327 (void **)ops_processed, ops_deqd); 328 329 deqd_tot += ops_deqd; 330 deqd_max = RTE_MAX(ops_deqd, deqd_max); 331 deqd_min = RTE_MIN(ops_deqd, deqd_min); 332 } 333 } 334 335 /* If there was any failure in crypto op, exit */ 336 if (ret) 337 return ret; 338 339 for (i = 0; i < tsc_idx; i++) { 340 tsc_val = ctx->res[i].tsc_end - ctx->res[i].tsc_start; 341 tsc_max = RTE_MAX(tsc_val, tsc_max); 342 tsc_min = RTE_MIN(tsc_val, tsc_min); 343 tsc_tot += tsc_val; 344 } 345 346 double time_tot, time_avg, time_max, time_min; 347 348 const uint64_t tunit = 1000000; /* us */ 349 const uint64_t tsc_hz = rte_get_tsc_hz(); 350 351 uint64_t enqd_avg = enqd_tot / b_idx; 352 uint64_t deqd_avg = deqd_tot / b_idx; 353 uint64_t tsc_avg = tsc_tot / tsc_idx; 354 355 time_tot = tunit*(double)(tsc_tot) / tsc_hz; 356 time_avg = tunit*(double)(tsc_avg) / tsc_hz; 357 time_max = tunit*(double)(tsc_max) / tsc_hz; 358 time_min = tunit*(double)(tsc_min) / tsc_hz; 359 360 uint16_t exp = 0; 361 if (ctx->options->csv) { 362 if (rte_atomic_compare_exchange_strong_explicit(&display_once, &exp, 1, 363 rte_memory_order_relaxed, rte_memory_order_relaxed)) 364 printf("\n# lcore, Buffer Size, Burst Size, Pakt Seq #, " 365 "cycles, time (us)"); 366 367 for (i = 0; i < ctx->options->total_ops; i++) { 368 369 printf("\n%u,%u,%u,%"PRIu64",%"PRIu64",%.3f", 370 ctx->lcore_id, ctx->options->test_buffer_size, 371 test_burst_size, i + 1, 372 ctx->res[i].tsc_end - ctx->res[i].tsc_start, 373 tunit * (double) (ctx->res[i].tsc_end 374 - ctx->res[i].tsc_start) 375 / tsc_hz); 376 377 } 378 } else { 379 printf("\n# Device %d on lcore %u\n", ctx->dev_id, 380 ctx->lcore_id); 381 printf("\n# total operations: %u", ctx->options->total_ops); 382 printf("\n# Buffer size: %u", ctx->options->test_buffer_size); 383 printf("\n# Burst size: %u", test_burst_size); 384 printf("\n# Number of bursts: %"PRIu64, 385 b_idx); 386 387 printf("\n#"); 388 printf("\n# \t Total\t Average\t " 389 "Maximum\t Minimum"); 390 printf("\n# enqueued\t%12"PRIu64"\t%10"PRIu64"\t" 391 "%10"PRIu64"\t%10"PRIu64, enqd_tot, 392 enqd_avg, enqd_max, enqd_min); 393 printf("\n# dequeued\t%12"PRIu64"\t%10"PRIu64"\t" 394 "%10"PRIu64"\t%10"PRIu64, deqd_tot, 395 deqd_avg, deqd_max, deqd_min); 396 printf("\n# cycles\t%12"PRIu64"\t%10"PRIu64"\t" 397 "%10"PRIu64"\t%10"PRIu64, tsc_tot, 398 tsc_avg, tsc_max, tsc_min); 399 printf("\n# time [us]\t%12.0f\t%10.3f\t%10.3f\t%10.3f", 400 time_tot, time_avg, time_max, time_min); 401 printf("\n\n"); 402 403 } 404 405 /* Get next size from range or list */ 406 if (ctx->options->inc_burst_size != 0) 407 test_burst_size += ctx->options->inc_burst_size; 408 else { 409 if (++burst_size_idx == ctx->options->burst_size_count) 410 break; 411 test_burst_size = 412 ctx->options->burst_size_list[burst_size_idx]; 413 } 414 } 415 416 return 0; 417 } 418 419 void 420 cperf_latency_test_destructor(void *arg) 421 { 422 struct cperf_latency_ctx *ctx = arg; 423 424 if (ctx == NULL) 425 return; 426 427 cperf_latency_test_free(ctx); 428 } 429