1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "include/logger_interface.h"
29
30 #include "../dce110/irq_service_dce110.h"
31
32 #include "dcn/dcn_1_0_offset.h"
33 #include "dcn/dcn_1_0_sh_mask.h"
34 #include "soc15_hw_ip.h"
35 #include "vega10_ip_offset.h"
36
37 #include "irq_service_dcn10.h"
38
39 #include "ivsrcid/irqsrcs_dcn_1_0.h"
40
41 static
to_dal_irq_source_dcn10(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)42 enum dc_irq_source to_dal_irq_source_dcn10(
43 struct irq_service *irq_service,
44 uint32_t src_id,
45 uint32_t ext_id)
46 {
47 switch (src_id) {
48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK1;
50 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK2;
52 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
53 return DC_IRQ_SOURCE_VBLANK3;
54 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK4;
56 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK5;
58 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
59 return DC_IRQ_SOURCE_VBLANK6;
60 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
61 return DC_IRQ_SOURCE_PFLIP1;
62 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
63 return DC_IRQ_SOURCE_PFLIP2;
64 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
65 return DC_IRQ_SOURCE_PFLIP3;
66 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
67 return DC_IRQ_SOURCE_PFLIP4;
68 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
69 return DC_IRQ_SOURCE_PFLIP5;
70 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
71 return DC_IRQ_SOURCE_PFLIP6;
72
73 case DCN_1_0__SRCID__DC_HPD1_INT:
74 /* generic src_id for all HPD and HPDRX interrupts */
75 switch (ext_id) {
76 case DCN_1_0__CTXID__DC_HPD1_INT:
77 return DC_IRQ_SOURCE_HPD1;
78 case DCN_1_0__CTXID__DC_HPD2_INT:
79 return DC_IRQ_SOURCE_HPD2;
80 case DCN_1_0__CTXID__DC_HPD3_INT:
81 return DC_IRQ_SOURCE_HPD3;
82 case DCN_1_0__CTXID__DC_HPD4_INT:
83 return DC_IRQ_SOURCE_HPD4;
84 case DCN_1_0__CTXID__DC_HPD5_INT:
85 return DC_IRQ_SOURCE_HPD5;
86 case DCN_1_0__CTXID__DC_HPD6_INT:
87 return DC_IRQ_SOURCE_HPD6;
88 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
89 return DC_IRQ_SOURCE_HPD1RX;
90 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
91 return DC_IRQ_SOURCE_HPD2RX;
92 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
93 return DC_IRQ_SOURCE_HPD3RX;
94 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
95 return DC_IRQ_SOURCE_HPD4RX;
96 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
97 return DC_IRQ_SOURCE_HPD5RX;
98 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
99 return DC_IRQ_SOURCE_HPD6RX;
100 default:
101 return DC_IRQ_SOURCE_INVALID;
102 }
103 break;
104
105 default:
106 return DC_IRQ_SOURCE_INVALID;
107 }
108 }
109
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)110 static bool hpd_ack(
111 struct irq_service *irq_service,
112 const struct irq_source_info *info)
113 {
114 uint32_t addr = info->status_reg;
115 uint32_t value = dm_read_reg(irq_service->ctx, addr);
116 uint32_t current_status =
117 get_reg_field_value(
118 value,
119 HPD0_DC_HPD_INT_STATUS,
120 DC_HPD_SENSE_DELAYED);
121
122 dal_irq_service_ack_generic(irq_service, info);
123
124 value = dm_read_reg(irq_service->ctx, info->enable_reg);
125
126 set_reg_field_value(
127 value,
128 current_status ? 0 : 1,
129 HPD0_DC_HPD_INT_CONTROL,
130 DC_HPD_INT_POLARITY);
131
132 dm_write_reg(irq_service->ctx, info->enable_reg, value);
133
134 return true;
135 }
136
137 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
138 .set = NULL,
139 .ack = hpd_ack
140 };
141
142 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
143 .set = NULL,
144 .ack = NULL
145 };
146
147 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
148 .set = NULL,
149 .ack = NULL
150 };
151
152 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
153 .set = NULL,
154 .ack = NULL
155 };
156
157 #define BASE_INNER(seg) \
158 DCE_BASE__INST0_SEG ## seg
159
160 #define BASE(seg) \
161 BASE_INNER(seg)
162
163 #define SRI(reg_name, block, id)\
164 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 mm ## block ## id ## _ ## reg_name
166
167
168 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
169 .enable_reg = SRI(reg1, block, reg_num),\
170 .enable_mask = \
171 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
172 .enable_value = {\
173 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
174 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
175 },\
176 .ack_reg = SRI(reg2, block, reg_num),\
177 .ack_mask = \
178 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
179 .ack_value = \
180 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
181
182 #define hpd_int_entry(reg_num)\
183 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
184 IRQ_REG_ENTRY(HPD, reg_num,\
185 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
186 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
187 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
188 .funcs = &hpd_irq_info_funcs\
189 }
190
191 #define hpd_rx_int_entry(reg_num)\
192 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
193 IRQ_REG_ENTRY(HPD, reg_num,\
194 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
195 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
196 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
197 .funcs = &hpd_rx_irq_info_funcs\
198 }
199 #define pflip_int_entry(reg_num)\
200 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
201 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
202 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
203 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
204 .funcs = &pflip_irq_info_funcs\
205 }
206
207 #define vupdate_int_entry(reg_num)\
208 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
209 IRQ_REG_ENTRY(OTG, reg_num,\
210 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
211 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
212 .funcs = &vblank_irq_info_funcs\
213 }
214
215 #define vblank_int_entry(reg_num)\
216 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
217 IRQ_REG_ENTRY(OTG, reg_num,\
218 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
219 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
220 .funcs = &vblank_irq_info_funcs\
221 }
222
223 #define dummy_irq_entry() \
224 {\
225 .funcs = &dummy_irq_info_funcs\
226 }
227
228 #define i2c_int_entry(reg_num) \
229 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
230
231 #define dp_sink_int_entry(reg_num) \
232 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
233
234 #define gpio_pad_int_entry(reg_num) \
235 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
236
237 #define dc_underflow_int_entry(reg_num) \
238 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
239
240 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
241 .set = dal_irq_service_dummy_set,
242 .ack = dal_irq_service_dummy_ack
243 };
244
245 static const struct irq_source_info
246 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
247 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
248 hpd_int_entry(0),
249 hpd_int_entry(1),
250 hpd_int_entry(2),
251 hpd_int_entry(3),
252 hpd_int_entry(4),
253 hpd_int_entry(5),
254 hpd_rx_int_entry(0),
255 hpd_rx_int_entry(1),
256 hpd_rx_int_entry(2),
257 hpd_rx_int_entry(3),
258 hpd_rx_int_entry(4),
259 hpd_rx_int_entry(5),
260 i2c_int_entry(1),
261 i2c_int_entry(2),
262 i2c_int_entry(3),
263 i2c_int_entry(4),
264 i2c_int_entry(5),
265 i2c_int_entry(6),
266 dp_sink_int_entry(1),
267 dp_sink_int_entry(2),
268 dp_sink_int_entry(3),
269 dp_sink_int_entry(4),
270 dp_sink_int_entry(5),
271 dp_sink_int_entry(6),
272 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
273 pflip_int_entry(0),
274 pflip_int_entry(1),
275 pflip_int_entry(2),
276 pflip_int_entry(3),
277 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
278 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
279 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
280 gpio_pad_int_entry(0),
281 gpio_pad_int_entry(1),
282 gpio_pad_int_entry(2),
283 gpio_pad_int_entry(3),
284 gpio_pad_int_entry(4),
285 gpio_pad_int_entry(5),
286 gpio_pad_int_entry(6),
287 gpio_pad_int_entry(7),
288 gpio_pad_int_entry(8),
289 gpio_pad_int_entry(9),
290 gpio_pad_int_entry(10),
291 gpio_pad_int_entry(11),
292 gpio_pad_int_entry(12),
293 gpio_pad_int_entry(13),
294 gpio_pad_int_entry(14),
295 gpio_pad_int_entry(15),
296 gpio_pad_int_entry(16),
297 gpio_pad_int_entry(17),
298 gpio_pad_int_entry(18),
299 gpio_pad_int_entry(19),
300 gpio_pad_int_entry(20),
301 gpio_pad_int_entry(21),
302 gpio_pad_int_entry(22),
303 gpio_pad_int_entry(23),
304 gpio_pad_int_entry(24),
305 gpio_pad_int_entry(25),
306 gpio_pad_int_entry(26),
307 gpio_pad_int_entry(27),
308 gpio_pad_int_entry(28),
309 gpio_pad_int_entry(29),
310 gpio_pad_int_entry(30),
311 dc_underflow_int_entry(1),
312 dc_underflow_int_entry(2),
313 dc_underflow_int_entry(3),
314 dc_underflow_int_entry(4),
315 dc_underflow_int_entry(5),
316 dc_underflow_int_entry(6),
317 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
318 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
319 vupdate_int_entry(0),
320 vupdate_int_entry(1),
321 vupdate_int_entry(2),
322 vupdate_int_entry(3),
323 vupdate_int_entry(4),
324 vupdate_int_entry(5),
325 vblank_int_entry(0),
326 vblank_int_entry(1),
327 vblank_int_entry(2),
328 vblank_int_entry(3),
329 vblank_int_entry(4),
330 vblank_int_entry(5),
331 };
332
333 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
334 .to_dal_irq_source = to_dal_irq_source_dcn10
335 };
336
construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)337 static void construct(
338 struct irq_service *irq_service,
339 struct irq_service_init_data *init_data)
340 {
341 dal_irq_service_construct(irq_service, init_data);
342
343 irq_service->info = irq_source_info_dcn10;
344 irq_service->funcs = &irq_service_funcs_dcn10;
345 }
346
dal_irq_service_dcn10_create(struct irq_service_init_data * init_data)347 struct irq_service *dal_irq_service_dcn10_create(
348 struct irq_service_init_data *init_data)
349 {
350 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
351 GFP_KERNEL);
352
353 if (!irq_service)
354 return NULL;
355
356 construct(irq_service, init_data);
357 return irq_service;
358 }
359