1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Kevin E. Martin <martin@xfree86.org> 30 * Rickard E. Faith <faith@valinux.com> 31 * Alan Hourihane <alanh@fairlite.demon.co.uk> 32 * 33 * References: 34 * 35 * !!!! FIXME !!!! 36 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 37 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 38 * 1999. 39 * 40 * !!!! FIXME !!!! 41 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 42 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 43 * 44 * !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h 45 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT 46 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! 47 */ 48 49 #define BIOS8(r, o) ((uchar) (r->bios[o])) 50 #define BIOS16(r, o) ((ushort)(r->bios[o] | (r->bios[(o) + 1] << 8))) 51 #define BIOS32(r, o) ((ulong) (r->bios[o] | (r->bios[(o) + 1] << 8) | \ 52 (r->bios[(o) + 2] << 16) | (r->bios[(o) + 3] << 24))) 53 54 enum { 55 BIOS_START = 0x48, 56 }; 57 58 /* Registers for 2D/Video/Overlay */ 59 #define ADAPTER_ID 0x0f2c /* PCI */ 60 #define AGP_BASE 0x0170 61 #define AGP_CNTL 0x0174 62 # define AGP_APER_SIZE_256MB (0x00 << 0) 63 # define AGP_APER_SIZE_128MB (0x20 << 0) 64 # define AGP_APER_SIZE_64MB (0x30 << 0) 65 # define AGP_APER_SIZE_32MB (0x38 << 0) 66 # define AGP_APER_SIZE_16MB (0x3c << 0) 67 # define AGP_APER_SIZE_8MB (0x3e << 0) 68 # define AGP_APER_SIZE_4MB (0x3f << 0) 69 # define AGP_APER_SIZE_MASK (0x3f << 0) 70 #define AGP_COMMAND 0x0f60 /* PCI */ 71 #define AGP_PLL_CNTL 0x000b /* PLL */ 72 #define AGP_STATUS 0x0f5c /* PCI */ 73 # define AGP_1X_MODE 0x01 74 # define AGP_2X_MODE 0x02 75 # define AGP_4X_MODE 0x04 76 # define AGP_FW_MODE 0x10 77 # define AGP_MODE_MASK 0x17 78 #define ATTRDR 0x03c1 /* VGA */ 79 #define ATTRDW 0x03c0 /* VGA */ 80 #define ATTRX 0x03c0 /* VGA */ 81 #define AUX_SC_CNTL 0x1660 82 # define AUX1_SC_EN (1 << 0) 83 # define AUX1_SC_MODE_OR (0 << 1) 84 # define AUX1_SC_MODE_NAND (1 << 1) 85 # define AUX2_SC_EN (1 << 2) 86 # define AUX2_SC_MODE_OR (0 << 3) 87 # define AUX2_SC_MODE_NAND (1 << 3) 88 # define AUX3_SC_EN (1 << 4) 89 # define AUX3_SC_MODE_OR (0 << 5) 90 # define AUX3_SC_MODE_NAND (1 << 5) 91 #define AUX1_SC_BOTTOM 0x1670 92 #define AUX1_SC_LEFT 0x1664 93 #define AUX1_SC_RIGHT 0x1668 94 #define AUX1_SC_TOP 0x166c 95 #define AUX2_SC_BOTTOM 0x1680 96 #define AUX2_SC_LEFT 0x1674 97 #define AUX2_SC_RIGHT 0x1678 98 #define AUX2_SC_TOP 0x167c 99 #define AUX3_SC_BOTTOM 0x1690 100 #define AUX3_SC_LEFT 0x1684 101 #define AUX3_SC_RIGHT 0x1688 102 #define AUX3_SC_TOP 0x168c 103 #define AUX_WINDOW_HORZ_CNTL 0x02d8 104 #define AUX_WINDOW_VERT_CNTL 0x02dc 105 106 #define BASE_CODE 0x0f0b 107 #define BIOS_0_SCRATCH 0x0010 108 #define BIOS_1_SCRATCH 0x0014 109 #define BIOS_2_SCRATCH 0x0018 110 #define BIOS_3_SCRATCH 0x001c 111 #define BIOS_4_SCRATCH 0x0020 112 #define BIOS_5_SCRATCH 0x0024 113 #define BIOS_6_SCRATCH 0x0028 114 #define BIOS_7_SCRATCH 0x002c 115 #define BIOS_ROM 0x0f30 /* PCI */ 116 #define BIST 0x0f0f /* PCI */ 117 #define BRUSH_DATA0 0x1480 118 #define BRUSH_DATA1 0x1484 119 #define BRUSH_DATA10 0x14a8 120 #define BRUSH_DATA11 0x14ac 121 #define BRUSH_DATA12 0x14b0 122 #define BRUSH_DATA13 0x14b4 123 #define BRUSH_DATA14 0x14b8 124 #define BRUSH_DATA15 0x14bc 125 #define BRUSH_DATA16 0x14c0 126 #define BRUSH_DATA17 0x14c4 127 #define BRUSH_DATA18 0x14c8 128 #define BRUSH_DATA19 0x14cc 129 #define BRUSH_DATA2 0x1488 130 #define BRUSH_DATA20 0x14d0 131 #define BRUSH_DATA21 0x14d4 132 #define BRUSH_DATA22 0x14d8 133 #define BRUSH_DATA23 0x14dc 134 #define BRUSH_DATA24 0x14e0 135 #define BRUSH_DATA25 0x14e4 136 #define BRUSH_DATA26 0x14e8 137 #define BRUSH_DATA27 0x14ec 138 #define BRUSH_DATA28 0x14f0 139 #define BRUSH_DATA29 0x14f4 140 #define BRUSH_DATA3 0x148c 141 #define BRUSH_DATA30 0x14f8 142 #define BRUSH_DATA31 0x14fc 143 #define BRUSH_DATA32 0x1500 144 #define BRUSH_DATA33 0x1504 145 #define BRUSH_DATA34 0x1508 146 #define BRUSH_DATA35 0x150c 147 #define BRUSH_DATA36 0x1510 148 #define BRUSH_DATA37 0x1514 149 #define BRUSH_DATA38 0x1518 150 #define BRUSH_DATA39 0x151c 151 #define BRUSH_DATA4 0x1490 152 #define BRUSH_DATA40 0x1520 153 #define BRUSH_DATA41 0x1524 154 #define BRUSH_DATA42 0x1528 155 #define BRUSH_DATA43 0x152c 156 #define BRUSH_DATA44 0x1530 157 #define BRUSH_DATA45 0x1534 158 #define BRUSH_DATA46 0x1538 159 #define BRUSH_DATA47 0x153c 160 #define BRUSH_DATA48 0x1540 161 #define BRUSH_DATA49 0x1544 162 #define BRUSH_DATA5 0x1494 163 #define BRUSH_DATA50 0x1548 164 #define BRUSH_DATA51 0x154c 165 #define BRUSH_DATA52 0x1550 166 #define BRUSH_DATA53 0x1554 167 #define BRUSH_DATA54 0x1558 168 #define BRUSH_DATA55 0x155c 169 #define BRUSH_DATA56 0x1560 170 #define BRUSH_DATA57 0x1564 171 #define BRUSH_DATA58 0x1568 172 #define BRUSH_DATA59 0x156c 173 #define BRUSH_DATA6 0x1498 174 #define BRUSH_DATA60 0x1570 175 #define BRUSH_DATA61 0x1574 176 #define BRUSH_DATA62 0x1578 177 #define BRUSH_DATA63 0x157c 178 #define BRUSH_DATA7 0x149c 179 #define BRUSH_DATA8 0x14a0 180 #define BRUSH_DATA9 0x14a4 181 #define BRUSH_SCALE 0x1470 182 #define BRUSH_Y_X 0x1474 183 #define BUS_CNTL 0x0030 184 # define BUS_MASTER_DIS (1 << 6) 185 # define BUS_RD_DISCARD_EN (1 << 24) 186 # define BUS_RD_ABORT_EN (1 << 25) 187 # define BUS_MSTR_DISCONNECT_EN (1 << 28) 188 # define BUS_WRT_BURST (1 << 29) 189 # define BUS_READ_BURST (1 << 30) 190 #define BUS_CNTL1 0x0034 191 # define BUS_WAIT_ON_LOCK_EN (1 << 4) 192 193 #define CACHE_CNTL 0x1724 194 #define CACHE_LINE 0x0f0c /* PCI */ 195 #define CAP0_TRIG_CNTL 0x0950 /* ? */ 196 #define CAP1_TRIG_CNTL 0x09c0 /* ? */ 197 #define CAPABILITIES_ID 0x0f50 /* PCI */ 198 #define CAPABILITIES_PTR 0x0f34 /* PCI */ 199 #define CLK_PIN_CNTL 0x0001 /* PLL */ 200 #define CLOCK_CNTL_DATA 0x000c 201 #define CLOCK_CNTL_INDEX 0x0008 202 # define PLL_WR_EN (1 << 7) 203 # define PLL_DIV_SEL (3 << 8) 204 # define PLL2_DIV_SEL_MASK ~(3 << 8) 205 #define CLR_CMP_CLR_3D 0x1a24 206 #define CLR_CMP_CLR_DST 0x15c8 207 #define CLR_CMP_CLR_SRC 0x15c4 208 #define CLR_CMP_CNTL 0x15c0 209 # define SRC_CMP_EQ_COLOR (4 << 0) 210 # define SRC_CMP_NEQ_COLOR (5 << 0) 211 # define CLR_CMP_SRC_SOURCE (1 << 24) 212 #define CLR_CMP_MASK 0x15cc 213 # define CLR_CMP_MSK 0xffffffff 214 #define CLR_CMP_MASK_3D 0x1A28 215 #define COMMAND 0x0f04 /* PCI */ 216 #define COMPOSITE_SHADOW_ID 0x1a0c 217 #define CONFIG_APER_0_BASE 0x0100 218 #define CONFIG_APER_1_BASE 0x0104 219 #define CONFIG_APER_SIZE 0x0108 220 #define CONFIG_BONDS 0x00e8 221 #define CONFIG_CNTL 0x00e0 222 # define CFG_ATI_REV_A11 (0 << 16) 223 # define CFG_ATI_REV_A12 (1 << 16) 224 # define CFG_ATI_REV_A13 (2 << 16) 225 # define CFG_ATI_REV_ID_MASK (0xf << 16) 226 #define CONFIG_MEMSIZE 0x00f8 227 #define CONFIG_MEMSIZE_EMBEDDED 0x0114 228 #define CONFIG_REG_1_BASE 0x010c 229 #define CONFIG_REG_APER_SIZE 0x0110 230 #define CONFIG_XSTRAP 0x00e4 231 #define CONSTANT_COLOR_C 0x1d34 232 # define CONSTANT_COLOR_MASK 0x00ffffff 233 # define CONSTANT_COLOR_ONE 0x00ffffff 234 # define CONSTANT_COLOR_ZERO 0x00000000 235 #define CRC_CMDFIFO_ADDR 0x0740 236 #define CRC_CMDFIFO_DOUT 0x0744 237 #define CRTC_CRNT_FRAME 0x0214 238 #define CRTC_EXT_CNTL 0x0054 239 # define CRTC_VGA_XOVERSCAN (1 << 0) 240 # define VGA_ATI_LINEAR (1 << 3) 241 # define XCRT_CNT_EN (1 << 6) 242 # define CRTC_HSYNC_DIS (1 << 8) 243 # define CRTC_VSYNC_DIS (1 << 9) 244 # define CRTC_DISPLAY_DIS (1 << 10) 245 # define CRTC_SYNC_TRISTAT (1 << 11) 246 # define CRTC_CRT_ON (1 << 15) 247 #define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 248 # define CRTC_HSYNC_DIS_BYTE (1 << 0) 249 # define CRTC_VSYNC_DIS_BYTE (1 << 1) 250 # define CRTC_DISPLAY_DIS_BYTE (1 << 2) 251 #define CRTC_GEN_CNTL 0x0050 252 # define CRTC_DBL_SCAN_EN (1 << 0) 253 # define CRTC_INTERLACE_EN (1 << 1) 254 # define CRTC_CSYNC_EN (1 << 4) 255 # define CRTC_CUR_EN (1 << 16) 256 # define CRTC_CUR_MODE_MASK (7 << 17) 257 # define CRTC_ICON_EN (1 << 20) 258 # define CRTC_EXT_DISP_EN (1 << 24) 259 # define CRTC_EN (1 << 25) 260 # define CRTC_DISP_REQ_EN_B (1 << 26) 261 #define CRTC2_GEN_CNTL 0x03f8 262 # define CRTC2_DBL_SCAN_EN (1 << 0) 263 # define CRTC2_INTERLACE_EN (1 << 1) 264 # define CRTC2_SYNC_TRISTAT (1 << 4) 265 # define CRTC2_HSYNC_TRISTAT (1 << 5) 266 # define CRTC2_VSYNC_TRISTAT (1 << 6) 267 # define CRTC2_CRT2_ON (1 << 7) 268 # define CRTC2_ICON_EN (1 << 15) 269 # define CRTC2_CUR_EN (1 << 16) 270 # define CRTC2_CUR_MODE_MASK (7 << 20) 271 # define CRTC2_DISP_DIS (1 << 23) 272 # define CRTC2_EN (1 << 25) 273 # define CRTC2_DISP_REQ_EN_B (1 << 26) 274 # define CRTC2_CSYNC_EN (1 << 27) 275 # define CRTC2_HSYNC_DIS (1 << 28) 276 # define CRTC2_VSYNC_DIS (1 << 29) 277 #define CRTC_GUI_TRIG_VLINE 0x0218 278 #define CRTC_H_SYNC_STRT_WID 0x0204 279 # define CRTC_H_SYNC_STRT_PIX (0x07 << 0) 280 # define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) 281 # define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 282 # define CRTC_H_SYNC_WID (0x3f << 16) 283 # define CRTC_H_SYNC_WID_SHIFT 16 284 # define CRTC_H_SYNC_POL (1 << 23) 285 #define CRTC2_H_SYNC_STRT_WID 0x0304 286 # define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 287 # define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) 288 # define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 289 # define CRTC2_H_SYNC_WID (0x3f << 16) 290 # define CRTC2_H_SYNC_WID_SHIFT 16 291 # define CRTC2_H_SYNC_POL (1 << 23) 292 #define CRTC_H_TOTAL_DISP 0x0200 293 # define CRTC_H_TOTAL (0x03ff << 0) 294 # define CRTC_H_TOTAL_SHIFT 0 295 # define CRTC_H_DISP (0x01ff << 16) 296 # define CRTC_H_DISP_SHIFT 16 297 #define CRTC2_H_TOTAL_DISP 0x0300 298 # define CRTC2_H_TOTAL (0x03ff << 0) 299 # define CRTC2_H_TOTAL_SHIFT 0 300 # define CRTC2_H_DISP (0x01ff << 16) 301 # define CRTC2_H_DISP_SHIFT 16 302 #define CRTC_OFFSET 0x0224 303 #define CRTC2_OFFSET 0x0324 304 #define CRTC_OFFSET_CNTL 0x0228 305 # define CRTC_TILE_EN (1 << 15) 306 #define CRTC2_OFFSET_CNTL 0x0328 307 # define CRTC2_TILE_EN (1 << 15) 308 #define CRTC_PITCH 0x022c 309 #define CRTC2_PITCH 0x032c 310 #define CRTC_STATUS 0x005c 311 # define CRTC_VBLANK_SAVE (1 << 1) 312 # define CRTC_VBLANK_SAVE_CLEAR (1 << 1) 313 #define CRTC2_STATUS 0x03fc 314 # define CRTC2_VBLANK_SAVE (1 << 1) 315 # define CRTC2_VBLANK_SAVE_CLEAR (1 << 1) 316 #define CRTC_V_SYNC_STRT_WID 0x020c 317 # define CRTC_V_SYNC_STRT (0x7ff << 0) 318 # define CRTC_V_SYNC_STRT_SHIFT 0 319 # define CRTC_V_SYNC_WID (0x1f << 16) 320 # define CRTC_V_SYNC_WID_SHIFT 16 321 # define CRTC_V_SYNC_POL (1 << 23) 322 #define CRTC2_V_SYNC_STRT_WID 0x030c 323 # define CRTC2_V_SYNC_STRT (0x7ff << 0) 324 # define CRTC2_V_SYNC_STRT_SHIFT 0 325 # define CRTC2_V_SYNC_WID (0x1f << 16) 326 # define CRTC2_V_SYNC_WID_SHIFT 16 327 # define CRTC2_V_SYNC_POL (1 << 23) 328 #define CRTC_V_TOTAL_DISP 0x0208 329 # define CRTC_V_TOTAL (0x07ff << 0) 330 # define CRTC_V_TOTAL_SHIFT 0 331 # define CRTC_V_DISP (0x07ff << 16) 332 # define CRTC_V_DISP_SHIFT 16 333 #define CRTC2_V_TOTAL_DISP 0x0308 334 # define CRTC2_V_TOTAL (0x07ff << 0) 335 # define CRTC2_V_TOTAL_SHIFT 0 336 # define CRTC2_V_DISP (0x07ff << 16) 337 # define CRTC2_V_DISP_SHIFT 16 338 #define CRTC_VLINE_CRNT_VLINE 0x0210 339 # define CRTC_CRNT_VLINE_MASK (0x7ff << 16) 340 #define CRTC2_CRNT_FRAME 0x0314 341 #define CRTC2_GUI_TRIG_VLINE 0x0318 342 #define CRTC2_VLINE_CRNT_VLINE 0x0310 343 #define CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 344 #define CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 345 #define CUR_CLR0 0x026c 346 #define CUR_CLR1 0x0270 347 #define CUR_HORZ_VERT_OFF 0x0268 348 #define CUR_HORZ_VERT_POSN 0x0264 349 #define CUR_OFFSET 0x0260 350 # define CUR_LOCK (1 << 31) 351 #define CUR2_CLR0 0x036c 352 #define CUR2_CLR1 0x0370 353 #define CUR2_HORZ_VERT_OFF 0x0368 354 #define CUR2_HORZ_VERT_POSN 0x0364 355 #define CUR2_OFFSET 0x0360 356 # define CUR2_LOCK (1 << 31) 357 358 #define DAC_CNTL 0x0058 359 # define DAC_RANGE_CNTL (3 << 0) 360 # define DAC_BLANKING (1 << 2) 361 # define DAC_8BIT_EN (1 << 8) 362 # define DAC_VGA_ADR_EN (1 << 13) 363 # define DAC_PDWN (1 << 15) 364 # define DAC_MASK_ALL (0xff << 24) 365 #define DAC_CNTL2 0x007c 366 # define DAC2_DAC_CLK_SEL (1 << 0) 367 # define DAC2_DAC2_CLK_SEL (1 << 1) 368 # define DAC2_PALETTE_ACC_CTL (1 << 5) 369 #define TV_DAC_CNTL 0x088c 370 # define TV_DAC_STD_MASK 0x0300 371 # define TV_DAC_RDACPD (1 << 24) 372 # define TV_DAC_GDACPD (1 << 25) 373 # define TV_DAC_BDACPD (1 << 26) 374 #define DISP_HW_DEBUG 0x0d14 375 # define CRT2_DISP1_SEL (1 << 5) 376 #define DISP_OUTPUT_CNTL 0x0d64 377 # define DISP_DAC_SOURCE_MASK 0x03 378 # define DISP_DAC_SOURCE_CRTC2 0x01 379 #define DAC_CRC_SIG 0x02cc 380 #define DAC_DATA 0x03c9 /* VGA */ 381 #define DAC_MASK 0x03c6 /* VGA */ 382 #define DAC_R_INDEX 0x03c7 /* VGA */ 383 #define DAC_W_INDEX 0x03c8 /* VGA */ 384 #define DDA_CONFIG 0x02e0 385 #define DDA_ON_OFF 0x02e4 386 #define DEFAULT_OFFSET 0x16e0 387 #define DEFAULT_PITCH 0x16e4 388 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 389 # define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 390 # define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 391 #define DESTINATION_3D_CLR_CMP_VAL 0x1820 392 #define DESTINATION_3D_CLR_CMP_MSK 0x1824 393 #define DEVICE_ID 0x0f02 /* PCI */ 394 #define DISP_MISC_CNTL 0x0d00 395 # define SOFT_RESET_GRPH_PP (1 << 0) 396 #define DP_BRUSH_BKGD_CLR 0x1478 397 #define DP_BRUSH_FRGD_CLR 0x147c 398 #define DP_CNTL 0x16c0 399 # define DST_X_LEFT_TO_RIGHT (1 << 0) 400 # define DST_Y_TOP_TO_BOTTOM (1 << 1) 401 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 402 # define DST_Y_MAJOR (1 << 2) 403 # define DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 404 # define DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 405 #define DP_DATATYPE 0x16c4 406 # define HOST_BIG_ENDIAN_EN (1 << 29) 407 #define DP_GUI_MASTER_CNTL 0x146c 408 # define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 409 # define GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 410 # define GMC_SRC_CLIPPING (1 << 2) 411 # define GMC_DST_CLIPPING (1 << 3) 412 # define GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 413 # define GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 414 # define GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 415 # define GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 416 # define GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 417 # define GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 418 # define GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 419 # define GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 420 # define GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 421 # define GMC_BRUSH_8x8_COLOR (10 << 4) 422 # define GMC_BRUSH_1X8_COLOR (12 << 4) 423 # define GMC_BRUSH_SOLID_COLOR (13 << 4) 424 # define GMC_BRUSH_NONE (15 << 4) 425 # define GMC_DST_8BPP_CI (2 << 8) 426 # define GMC_DST_15BPP (3 << 8) 427 # define GMC_DST_16BPP (4 << 8) 428 # define GMC_DST_24BPP (5 << 8) 429 # define GMC_DST_32BPP (6 << 8) 430 # define GMC_DST_8BPP_RGB (7 << 8) 431 # define GMC_DST_Y8 (8 << 8) 432 # define GMC_DST_RGB8 (9 << 8) 433 # define GMC_DST_VYUY (11 << 8) 434 # define GMC_DST_YVYU (12 << 8) 435 # define GMC_DST_AYUV444 (14 << 8) 436 # define GMC_DST_ARGB4444 (15 << 8) 437 # define GMC_DST_DATATYPE_MASK (0x0f << 8) 438 # define GMC_DST_DATATYPE_SHIFT 8 439 # define GMC_SRC_DATATYPE_MASK (3 << 12) 440 # define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 441 # define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 442 # define GMC_SRC_DATATYPE_COLOR (3 << 12) 443 # define GMC_BYTE_PIX_ORDER (1 << 14) 444 # define GMC_BYTE_MSB_TO_LSB (0 << 14) 445 # define GMC_BYTE_LSB_TO_MSB (1 << 14) 446 # define GMC_CONVERSION_TEMP (1 << 15) 447 # define GMC_CONVERSION_TEMP_6500 (0 << 15) 448 # define GMC_CONVERSION_TEMP_9300 (1 << 15) 449 # define GMC_ROP3_MASK (0xff << 16) 450 # define DP_SRC_SOURCE_MASK (7 << 24) 451 # define DP_SRC_SOURCE_MEMORY (2 << 24) 452 # define DP_SRC_SOURCE_HOST_DATA (3 << 24) 453 # define GMC_3D_FCN_EN (1 << 27) 454 # define GMC_CLR_CMP_CNTL_DIS (1 << 28) 455 # define GMC_AUX_CLIP_DIS (1 << 29) 456 # define GMC_WR_MSK_DIS (1 << 30) 457 # define GMC_LD_BRUSH_Y_X (1 << 31) 458 # define ROP3_ZERO 0x00000000 459 # define ROP3_DSa 0x00880000 460 # define ROP3_SDna 0x00440000 461 # define ROP3_S 0x00cc0000 462 # define ROP3_DSna 0x00220000 463 # define ROP3_D 0x00aa0000 464 # define ROP3_DSx 0x00660000 465 # define ROP3_DSo 0x00ee0000 466 # define ROP3_DSon 0x00110000 467 # define ROP3_DSxn 0x00990000 468 # define ROP3_Dn 0x00550000 469 # define ROP3_SDno 0x00dd0000 470 # define ROP3_Sn 0x00330000 471 # define ROP3_DSno 0x00bb0000 472 # define ROP3_DSan 0x00770000 473 # define ROP3_ONE 0x00ff0000 474 # define ROP3_DPa 0x00a00000 475 # define ROP3_PDna 0x00500000 476 # define ROP3_P 0x00f00000 477 # define ROP3_DPna 0x000a0000 478 # define ROP3_DPo 0x00fa0000 479 # define ROP3_DPon 0x00050000 480 # define ROP3_PDxn 0x00a50000 481 # define ROP3_DPx 0x005a0000 482 # define ROP3_PDno 0x00f50000 483 # define ROP3_Pn 0x000f0000 484 # define ROP3_DPno 0x00af0000 485 # define ROP3_DPan 0x005f0000 486 #define DP_GUI_MASTER_CNTL_C 0x1c84 487 #define DP_MIX 0x16c8 488 #define DP_SRC_BKGD_CLR 0x15dc 489 #define DP_SRC_FRGD_CLR 0x15d8 490 #define DP_WRITE_MASK 0x16cc 491 #define DST_BRES_DEC 0x1630 492 #define DST_BRES_ERR 0x1628 493 #define DST_BRES_INC 0x162c 494 #define DST_BRES_LNTH 0x1634 495 #define DST_BRES_LNTH_SUB 0x1638 496 #define DST_HEIGHT 0x1410 497 #define DST_HEIGHT_WIDTH 0x143c 498 #define DST_HEIGHT_WIDTH_8 0x158c 499 #define DST_HEIGHT_WIDTH_BW 0x15b4 500 #define DST_HEIGHT_Y 0x15a0 501 #define DST_LINE_START 0x1600 502 #define DST_LINE_END 0x1604 503 #define DST_LINE_PATCOUNT 0x1608 504 # define BRES_CNTL_SHIFT 8 505 #define DST_OFFSET 0x1404 506 #define DST_PITCH 0x1408 507 #define DST_PITCH_OFFSET 0x142c 508 #define DST_PITCH_OFFSET_C 0x1c80 509 # define PITCH_SHIFT 21 510 # define DST_TILE_LINEAR (0 << 30) 511 # define DST_TILE_MACRO (1 << 30) 512 # define DST_TILE_MICRO (2 << 30) 513 # define DST_TILE_BOTH (3 << 30) 514 #define DST_WIDTH 0x140c 515 #define DST_WIDTH_HEIGHT 0x1598 516 #define DST_WIDTH_X 0x1588 517 #define DST_WIDTH_X_INCY 0x159c 518 #define DST_X 0x141c 519 #define DST_X_SUB 0x15a4 520 #define DST_X_Y 0x1594 521 #define DST_Y 0x1420 522 #define DST_Y_SUB 0x15a8 523 #define DST_Y_X 0x1438 524 525 #define FCP_CNTL 0x0910 526 # define FCP0_SRC_PCICLK 0 527 # define FCP0_SRC_PCLK 1 528 # define FCP0_SRC_PCLKb 2 529 # define FCP0_SRC_HREF 3 530 # define FCP0_SRC_GND 4 531 # define FCP0_SRC_HREFb 5 532 #define FLUSH_1 0x1704 533 #define FLUSH_2 0x1708 534 #define FLUSH_3 0x170c 535 #define FLUSH_4 0x1710 536 #define FLUSH_5 0x1714 537 #define FLUSH_6 0x1718 538 #define FLUSH_7 0x171c 539 #define FOG_3D_TABLE_START 0x1810 540 #define FOG_3D_TABLE_END 0x1814 541 #define FOG_3D_TABLE_DENSITY 0x181c 542 #define FOG_TABLE_INDEX 0x1a14 543 #define FOG_TABLE_DATA 0x1a18 544 #define FP_CRTC_H_TOTAL_DISP 0x0250 545 #define FP_CRTC_V_TOTAL_DISP 0x0254 546 #define FP_CRTC2_H_TOTAL_DISP 0x0350 547 #define FP_CRTC2_V_TOTAL_DISP 0x0354 548 # define FP_CRTC_H_TOTAL_MASK 0x000003ff 549 # define FP_CRTC_H_DISP_MASK 0x01ff0000 550 # define FP_CRTC_V_TOTAL_MASK 0x00000fff 551 # define FP_CRTC_V_DISP_MASK 0x0fff0000 552 # define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 553 # define FP_H_SYNC_WID_MASK 0x003f0000 554 # define FP_V_SYNC_STRT_MASK 0x00000fff 555 # define FP_V_SYNC_WID_MASK 0x001f0000 556 # define FP_CRTC_H_TOTAL_SHIFT 0x00000000 557 # define FP_CRTC_H_DISP_SHIFT 0x00000010 558 # define FP_CRTC_V_TOTAL_SHIFT 0x00000000 559 # define FP_CRTC_V_DISP_SHIFT 0x00000010 560 # define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 561 # define FP_H_SYNC_WID_SHIFT 0x00000010 562 # define FP_V_SYNC_STRT_SHIFT 0x00000000 563 # define FP_V_SYNC_WID_SHIFT 0x00000010 564 #define FP_GEN_CNTL 0x0284 565 # define FP_FPON (1 << 0) 566 # define FP_TMDS_EN (1 << 2) 567 # define FP_PANEL_FORMAT (1 << 3) 568 # define FP_EN_TMDS (1 << 7) 569 # define FP_DETECT_SENSE (1 << 8) 570 # define FP_SEL_CRTC2 (1 << 13) 571 # define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 572 # define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 573 # define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 574 # define FP_CRTC_USE_SHADOW_VEND (1 << 18) 575 # define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 576 # define FP_DFP_SYNC_SEL (1 << 21) 577 # define FP_CRTC_LOCK_8DOT (1 << 22) 578 # define FP_CRT_SYNC_SEL (1 << 23) 579 # define FP_USE_SHADOW_EN (1 << 24) 580 # define FP_CRT_SYNC_ALT (1 << 26) 581 #define FP2_GEN_CNTL 0x0288 582 # define FP2_BLANK_EN (1 << 1) 583 # define FP2_ON (1 << 2) 584 # define FP2_PANEL_FORMAT (1 << 3) 585 # define FP2_SEL_CRTC2 (1 << 13) 586 # define FP2_FP_POL (1 << 16) 587 # define FP2_LP_POL (1 << 17) 588 # define FP2_SCK_POL (1 << 18) 589 # define FP2_LCD_CNTL_MASK (7 << 19) 590 # define FP2_PAD_FLOP_EN (1 << 22) 591 # define FP2_CRC_EN (1 << 23) 592 # define FP2_CRC_READ_EN (1 << 24) 593 #define FP_H_SYNC_STRT_WID 0x02c4 594 #define FP_H2_SYNC_STRT_WID 0x03c4 595 #define FP_HORZ_STRETCH 0x028c 596 #define FP_HORZ2_STRETCH 0x038c 597 # define HORZ_STRETCH_RATIO_MASK 0xffff 598 # define HORZ_STRETCH_RATIO_MAX 4096 599 # define HORZ_PANEL_SIZE (0x1ff << 16) 600 # define HORZ_PANEL_SHIFT 16 601 # define HORZ_STRETCH_PIXREP (0 << 25) 602 # define HORZ_STRETCH_BLEND (1 << 26) 603 # define HORZ_STRETCH_ENABLE (1 << 25) 604 # define HORZ_AUTO_RATIO (1 << 27) 605 # define HORZ_FP_LOOP_STRETCH (0x7 << 28) 606 # define HORZ_AUTO_RATIO_INC (1 << 31) 607 #define FP_V_SYNC_STRT_WID 0x02c8 608 #define FP_VERT_STRETCH 0x0290 609 #define FP_V2_SYNC_STRT_WID 0x03c8 610 #define FP_VERT2_STRETCH 0x0390 611 # define VERT_PANEL_SIZE (0xfff << 12) 612 # define VERT_PANEL_SHIFT 12 613 # define VERT_STRETCH_RATIO_MASK 0xfff 614 # define VERT_STRETCH_RATIO_SHIFT 0 615 # define VERT_STRETCH_RATIO_MAX 4096 616 # define VERT_STRETCH_ENABLE (1 << 25) 617 # define VERT_STRETCH_LINEREP (0 << 26) 618 # define VERT_STRETCH_BLEND (1 << 26) 619 # define VERT_AUTO_RATIO_EN (1 << 27) 620 # define VERT_STRETCH_RESERVED 0xf1000000 621 622 #define GEN_INT_CNTL 0x0040 623 #define GEN_INT_STATUS 0x0044 624 # define VSYNC_INT_AK (1 << 2) 625 # define VSYNC_INT (1 << 2) 626 # define VSYNC2_INT_AK (1 << 6) 627 # define VSYNC2_INT (1 << 6) 628 #define GENENB 0x03c3 /* VGA */ 629 #define GENFC_RD 0x03ca /* VGA */ 630 #define GENFC_WT 0x03da /* VGA, 0x03ba */ 631 #define GENMO_RD 0x03cc /* VGA */ 632 #define GENMO_WT 0x03c2 /* VGA */ 633 #define GENS0 0x03c2 /* VGA */ 634 #define GENS1 0x03da /* VGA, 0x03ba */ 635 #define GPIO_MONID 0x0068 /* DDC interface via I2C */ 636 #define GPIO_MONIDB 0x006c 637 #define GPIO_CRT2_DDC 0x006c 638 #define GPIO_DVI_DDC 0x0064 639 #define GPIO_VGA_DDC 0x0060 640 # define GPIO_A_0 (1 << 0) 641 # define GPIO_A_1 (1 << 1) 642 # define GPIO_Y_0 (1 << 8) 643 # define GPIO_Y_1 (1 << 9) 644 # define GPIO_Y_SHIFT_0 8 645 # define GPIO_Y_SHIFT_1 9 646 # define GPIO_EN_0 (1 << 16) 647 # define GPIO_EN_1 (1 << 17) 648 # define GPIO_MASK_0 (1 << 24) /*??*/ 649 # define GPIO_MASK_1 (1 << 25) /*??*/ 650 #define GRPH8_DATA 0x03cf /* VGA */ 651 #define GRPH8_IDX 0x03ce /* VGA */ 652 #define GUI_SCRATCH_REG0 0x15e0 653 #define GUI_SCRATCH_REG1 0x15e4 654 #define GUI_SCRATCH_REG2 0x15e8 655 #define GUI_SCRATCH_REG3 0x15ec 656 #define GUI_SCRATCH_REG4 0x15f0 657 #define GUI_SCRATCH_REG5 0x15f4 658 659 #define HEADER 0x0f0e /* PCI */ 660 #define HOST_DATA0 0x17c0 661 #define HOST_DATA1 0x17c4 662 #define HOST_DATA2 0x17c8 663 #define HOST_DATA3 0x17cc 664 #define HOST_DATA4 0x17d0 665 #define HOST_DATA5 0x17d4 666 #define HOST_DATA6 0x17d8 667 #define HOST_DATA7 0x17dc 668 #define HOST_DATA_LAST 0x17e0 669 #define HOST_PATH_CNTL 0x0130 670 # define HDP_SOFT_RESET (1 << 26) 671 #define HTOTAL_CNTL 0x0009 /* PLL */ 672 #define HTOTAL2_CNTL 0x002e /* PLL */ 673 674 #define I2C_CNTL_1 0x0094 /* ? */ 675 #define DVI_I2C_CNTL_1 0x02e4 /* ? */ 676 #define INTERRUPT_LINE 0x0f3c /* PCI */ 677 #define INTERRUPT_PIN 0x0f3d /* PCI */ 678 #define IO_BASE 0x0f14 /* PCI */ 679 680 #define LATENCY 0x0f0d /* PCI */ 681 #define LEAD_BRES_DEC 0x1608 682 #define LEAD_BRES_LNTH 0x161c 683 #define LEAD_BRES_LNTH_SUB 0x1624 684 #define LVDS_GEN_CNTL 0x02d0 685 # define LVDS_ON (1 << 0) 686 # define LVDS_DISPLAY_DIS (1 << 1) 687 # define LVDS_PANEL_TYPE (1 << 2) 688 # define LVDS_PANEL_FORMAT (1 << 3) 689 # define LVDS_EN (1 << 7) 690 # define LVDS_DIGON (1 << 18) 691 # define LVDS_BLON (1 << 19) 692 # define LVDS_SEL_CRTC2 (1 << 23) 693 #define LVDS_PLL_CNTL 0x02d4 694 # define HSYNC_DELAY_SHIFT 28 695 # define HSYNC_DELAY_MASK (0xf << 28) 696 697 #define MAX_LATENCY 0x0f3f /* PCI */ 698 #define MC_AGP_LOCATION 0x014c 699 #define MC_FB_LOCATION 0x0148 700 #define MCLK_CNTL 0x0012 /* PLL */ 701 # define FORCEON_MCLKA (1 << 16) 702 # define FORCEON_MCLKB (1 << 17) 703 # define FORCEON_YCLKA (1 << 18) 704 # define FORCEON_YCLKB (1 << 19) 705 # define FORCEON_MC (1 << 20) 706 # define FORCEON_AIC (1 << 21) 707 #define MDGPIO_A_REG 0x01ac 708 #define MDGPIO_EN_REG 0x01b0 709 #define MDGPIO_MASK 0x0198 710 #define MDGPIO_Y_REG 0x01b4 711 #define MEM_ADDR_CONFIG 0x0148 712 #define MEM_BASE 0x0f10 /* PCI */ 713 #define MEM_CNTL 0x0140 714 #define MEM_INIT_LAT_TIMER 0x0154 715 #define MEM_INTF_CNTL 0x014c 716 #define MEM_SDRAM_MODE_REG 0x0158 717 #define MEM_STR_CNTL 0x0150 718 #define MEM_VGA_RP_SEL 0x003c 719 #define MEM_VGA_WP_SEL 0x0038 720 #define MIN_GRANT 0x0f3e /* PCI */ 721 #define MM_DATA 0x0004 722 #define MM_INDEX 0x0000 723 #define MPLL_CNTL 0x000e /* PLL */ 724 #define MPP_TB_CONFIG 0x01c0 /* ? */ 725 #define MPP_GP_CONFIG 0x01c8 /* ? */ 726 727 728 #define N_VIF_COUNT 0x0248 729 730 #define OV0_AUTO_FLIP_CNTL 0x0470 731 #define OV0_COLOUR_CNTL 0x04E0 732 #define OV0_DEINTERLACE_PATTERN 0x0474 733 #define OV0_TEST 0x04F8 734 #define OV0_EXCLUSIVE_HORZ 0x0408 735 # define EXCL_HORZ_START_MASK 0x000000ff 736 # define EXCL_HORZ_END_MASK 0x0000ff00 737 # define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 738 # define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 739 #define OV0_EXCLUSIVE_VERT 0x040C 740 # define EXCL_VERT_START_MASK 0x000003ff 741 # define EXCL_VERT_END_MASK 0x03ff0000 742 #define OV0_FILTER_CNTL 0x04A0 743 #define OV0_FOUR_TAP_COEF_0 0x04B0 744 #define OV0_FOUR_TAP_COEF_1 0x04B4 745 #define OV0_FOUR_TAP_COEF_2 0x04B8 746 #define OV0_FOUR_TAP_COEF_3 0x04BC 747 #define OV0_FOUR_TAP_COEF_4 0x04C0 748 #define OV0_GAMMA_000_00F 0x0d40 749 #define OV0_GAMMA_010_01F 0x0d44 750 #define OV0_GAMMA_020_03F 0x0d48 751 #define OV0_GAMMA_040_07F 0x0d4c 752 #define OV0_GAMMA_080_0BF 0x0e00 753 #define OV0_GAMMA_0C0_0FF 0x0e04 754 #define OV0_GAMMA_100_13F 0x0e08 755 #define OV0_GAMMA_140_17F 0x0e0c 756 #define OV0_GAMMA_180_1BF 0x0e10 757 #define OV0_GAMMA_1C0_1FF 0x0e14 758 #define OV0_GAMMA_200_23F 0x0e18 759 #define OV0_GAMMA_240_27F 0x0e1c 760 #define OV0_GAMMA_280_2BF 0x0e20 761 #define OV0_GAMMA_2C0_2FF 0x0e24 762 #define OV0_GAMMA_300_33F 0x0e28 763 #define OV0_GAMMA_340_37F 0x0e2c 764 #define OV0_GAMMA_380_3BF 0x0d50 765 #define OV0_GAMMA_3C0_3FF 0x0d54 766 #define OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 767 #define OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 768 #define OV0_H_INC 0x0480 769 #define OV0_KEY_CNTL 0x04F4 770 # define VIDEO_KEY_FN_MASK 0x00000003L 771 # define VIDEO_KEY_FN_FALSE 0x00000000L 772 # define VIDEO_KEY_FN_TRUE 0x00000001L 773 # define VIDEO_KEY_FN_EQ 0x00000002L 774 # define VIDEO_KEY_FN_NE 0x00000003L 775 # define GRAPHIC_KEY_FN_MASK 0x00000030L 776 # define GRAPHIC_KEY_FN_FALSE 0x00000000L 777 # define GRAPHIC_KEY_FN_TRUE 0x00000010L 778 # define GRAPHIC_KEY_FN_EQ 0x00000020L 779 # define GRAPHIC_KEY_FN_NE 0x00000030L 780 # define CMP_MIX_MASK 0x00000100L 781 # define CMP_MIX_OR 0x00000000L 782 # define CMP_MIX_AND 0x00000100L 783 #define OV0_LIN_TRANS_A 0x0d20 784 #define OV0_LIN_TRANS_B 0x0d24 785 #define OV0_LIN_TRANS_C 0x0d28 786 #define OV0_LIN_TRANS_D 0x0d2c 787 #define OV0_LIN_TRANS_E 0x0d30 788 #define OV0_LIN_TRANS_F 0x0d34 789 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 790 # define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 791 # define P1_ACTIVE_LINES_M1 0x0fff0000L 792 #define OV0_P1_H_ACCUM_INIT 0x0488 793 #define OV0_P1_V_ACCUM_INIT 0x0428 794 # define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 795 # define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 796 #define OV0_P1_X_START_END 0x0494 797 #define OV0_P2_X_START_END 0x0498 798 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 799 # define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 800 # define P23_ACTIVE_LINES_M1 0x07ff0000L 801 #define OV0_P23_H_ACCUM_INIT 0x048C 802 #define OV0_P23_V_ACCUM_INIT 0x042C 803 #define OV0_P3_X_START_END 0x049C 804 #define OV0_REG_LOAD_CNTL 0x0410 805 # define REG_LD_CTL_LOCK 0x00000001L 806 # define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 807 # define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 808 # define REG_LD_CTL_LOCK_READBACK 0x00000008L 809 #define OV0_SCALE_CNTL 0x0420 810 # define SCALER_HORZ_PICK_NEAREST 0x00000004L 811 # define SCALER_VERT_PICK_NEAREST 0x00000008L 812 # define SCALER_SIGNED_UV 0x00000010L 813 # define SCALER_GAMMA_SEL_MASK 0x00000060L 814 # define SCALER_GAMMA_SEL_BRIGHT 0x00000000L 815 # define SCALER_GAMMA_SEL_G22 0x00000020L 816 # define SCALER_GAMMA_SEL_G18 0x00000040L 817 # define SCALER_GAMMA_SEL_G14 0x00000060L 818 # define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 819 # define SCALER_SURFAC_FORMAT 0x00000f00L 820 # define SCALER_SOURCE_15BPP 0x00000300L 821 # define SCALER_SOURCE_16BPP 0x00000400L 822 # define SCALER_SOURCE_32BPP 0x00000600L 823 # define SCALER_SOURCE_YUV9 0x00000900L 824 # define SCALER_SOURCE_YUV12 0x00000A00L 825 # define SCALER_SOURCE_VYUY422 0x00000B00L 826 # define SCALER_SOURCE_YVYU422 0x00000C00L 827 # define SCALER_ADAPTIVE_DEINT 0x00001000L 828 # define SCALER_TEMPORAL_DEINT 0x00002000L 829 # define SCALER_SMART_SWITCH 0x00008000L 830 # define SCALER_BURST_PER_PLANE 0x007F0000L 831 # define SCALER_DOUBLE_BUFFER 0x01000000L 832 # define SCALER_DIS_LIMIT 0x08000000L 833 # define SCALER_INT_EMU 0x20000000L 834 # define SCALER_ENABLE 0x40000000L 835 # define SCALER_SOFT_RESET 0x80000000L 836 #define OV0_STEP_BY 0x0484 837 #define OV0_V_INC 0x0424 838 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 839 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 840 #define OV0_VID_BUF0_BASE_ADRS 0x0440 841 # define VIF_BUF0_PITCH_SEL 0x00000001L 842 # define VIF_BUF0_TILE_ADRS 0x00000002L 843 # define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 844 # define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 845 #define OV0_VID_BUF1_BASE_ADRS 0x0444 846 # define VIF_BUF1_PITCH_SEL 0x00000001L 847 # define VIF_BUF1_TILE_ADRS 0x00000002L 848 # define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 849 # define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 850 #define OV0_VID_BUF2_BASE_ADRS 0x0448 851 # define VIF_BUF2_PITCH_SEL 0x00000001L 852 # define VIF_BUF2_TILE_ADRS 0x00000002L 853 # define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 854 # define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 855 #define OV0_VID_BUF3_BASE_ADRS 0x044C 856 #define OV0_VID_BUF4_BASE_ADRS 0x0450 857 #define OV0_VID_BUF5_BASE_ADRS 0x0454 858 #define OV0_VIDEO_KEY_CLR_HIGH 0x04E8 859 #define OV0_VIDEO_KEY_CLR_LOW 0x04E4 860 #define OV0_Y_X_START 0x0400 861 #define OV0_Y_X_END 0x0404 862 #define OV1_Y_X_START 0x0600 863 #define OV1_Y_X_END 0x0604 864 #define OVR_CLR 0x0230 865 #define OVR_WID_LEFT_RIGHT 0x0234 866 #define OVR_WID_TOP_BOTTOM 0x0238 867 868 #define P2PLL_CNTL 0x002a /* P2PLL */ 869 # define P2PLL_RESET (1 << 0) 870 # define P2PLL_SLEEP (1 << 1) 871 # define P2PLL_ATOMIC_UPDATE_EN (1 << 16) 872 # define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 873 # define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 874 #define P2PLL_DIV_0 0x002c 875 # define P2PLL_FB0_DIV_MASK 0x07ff 876 # define P2PLL_POST0_DIV_MASK 0x00070000 877 #define P2PLL_REF_DIV 0x002B /* PLL */ 878 # define P2PLL_REF_DIV_MASK 0x03ff 879 # define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 880 # define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 881 # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff < 18) 882 # define R300_PPLL_REF_DIV_ACC_SHIFT 18 883 #define PALETTE_DATA 0x00b4 884 #define PALETTE_30_DATA 0x00b8 885 #define PALETTE_INDEX 0x00b0 886 #define PCI_GART_PAGE 0x017c 887 #define PIXCLKS_CNTL 0x002d 888 # define PIX2CLK_SRC_SEL_MASK 0x03 889 # define PIX2CLK_SRC_SEL_CPUCLK 0x00 890 # define PIX2CLK_SRC_SEL_PSCANCLK 0x01 891 # define PIX2CLK_SRC_SEL_BYTECLK 0x02 892 # define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 893 #define PLANE_3D_MASK_C 0x1d44 894 #define PLL_TEST_CNTL 0x0013 /* PLL */ 895 #define PMI_CAP_ID 0x0f5c /* PCI */ 896 #define PMI_DATA 0x0f63 /* PCI */ 897 #define PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 898 #define PMI_PMC_REG 0x0f5e /* PCI */ 899 #define PMI_PMCSR_REG 0x0f60 /* PCI */ 900 #define PMI_REGISTER 0x0f5c /* PCI */ 901 #define PPLL_CNTL 0x0002 /* PLL */ 902 # define PPLL_RESET (1 << 0) 903 # define PPLL_SLEEP (1 << 1) 904 # define PPLL_ATOMIC_UPDATE_EN (1 << 16) 905 # define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 906 # define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 907 #define PPLL_DIV_0 0x0004 /* PLL */ 908 #define PPLL_DIV_1 0x0005 /* PLL */ 909 #define PPLL_DIV_2 0x0006 /* PLL */ 910 #define PPLL_DIV_3 0x0007 /* PLL */ 911 # define PPLL_FB3_DIV_MASK 0x07ff 912 # define PPLL_POST3_DIV_MASK 0x00070000 913 #define PPLL_REF_DIV 0x0003 /* PLL */ 914 # define PPLL_REF_DIV_MASK 0x03ff 915 # define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 916 # define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 917 #define PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 918 919 #define RBBM_GUICNTL 0x172c 920 # define HOST_DATA_SWAP_NONE (0 << 0) 921 # define HOST_DATA_SWAP_16BIT (1 << 0) 922 # define HOST_DATA_SWAP_32BIT (2 << 0) 923 # define HOST_DATA_SWAP_HDW (3 << 0) 924 #define RBBM_SOFT_RESET 0x00f0 925 # define SOFT_RESET_CP (1 << 0) 926 # define SOFT_RESET_HI (1 << 1) 927 # define SOFT_RESET_SE (1 << 2) 928 # define SOFT_RESET_RE (1 << 3) 929 # define SOFT_RESET_PP (1 << 4) 930 # define SOFT_RESET_E2 (1 << 5) 931 # define SOFT_RESET_RB (1 << 6) 932 # define SOFT_RESET_HDP (1 << 7) 933 #define RBBM_STATUS 0x0e40 934 # define RBBM_FIFOCNT_MASK 0x007f 935 # define RBBM_ACTIVE (1 << 31) 936 #define RB2D_DSTCACHE_CTLSTAT 0x342c 937 # define RB2D_DC_FLUSH (3 << 0) 938 # define RB2D_DC_FREE (3 << 2) 939 # define RB2D_DC_FLUSH_ALL 0xf 940 # define RB2D_DC_BUSY (1 << 31) 941 #define RB2D_DSTCACHE_MODE 0x3428 942 #define REG_BASE 0x0f18 /* PCI */ 943 #define REGPROG_INF 0x0f09 /* PCI */ 944 #define REVISION_ID 0x0f08 /* PCI */ 945 946 #define SC_BOTTOM 0x164c 947 #define SC_BOTTOM_RIGHT 0x16f0 948 #define SC_BOTTOM_RIGHT_C 0x1c8c 949 #define SC_LEFT 0x1640 950 #define SC_RIGHT 0x1644 951 #define SC_TOP 0x1648 952 #define SC_TOP_LEFT 0x16ec 953 #define SC_TOP_LEFT_C 0x1c88 954 # define SC_SIGN_MASK_LO 0x8000 955 # define SC_SIGN_MASK_HI 0x80000000 956 #define SCLK_CNTL 0x000d /* PLL */ 957 # define DYN_STOP_LAT_MASK 0x00007ff8 958 # define CP_MAX_DYN_STOP_LAT 0x0008 959 # define SCLK_FORCEON_MASK 0xffff8000 960 #define SCLK_MORE_CNTL 0x0035 /* PLL */ 961 # define SCLK_MORE_FORCEON 0x0700 962 #define SDRAM_MODE_REG 0x0158 963 #define SEQ8_DATA 0x03c5 /* VGA */ 964 #define SEQ8_IDX 0x03c4 /* VGA */ 965 #define SNAPSHOT_F_COUNT 0x0244 966 #define SNAPSHOT_VH_COUNTS 0x0240 967 #define SNAPSHOT_VIF_COUNT 0x024c 968 #define SRC_OFFSET 0x15ac 969 #define SRC_PITCH 0x15b0 970 #define SRC_PITCH_OFFSET 0x1428 971 #define SRC_SC_BOTTOM 0x165c 972 #define SRC_SC_BOTTOM_RIGHT 0x16f4 973 #define SRC_SC_RIGHT 0x1654 974 #define SRC_X 0x1414 975 #define SRC_X_Y 0x1590 976 #define SRC_Y 0x1418 977 #define SRC_Y_X 0x1434 978 #define STATUS 0x0f06 /* PCI */ 979 #define SUBPIC_CNTL 0x0540 /* ? */ 980 #define SUB_CLASS 0x0f0a /* PCI */ 981 #define SURFACE_CNTL 0x0b00 982 # define SURF_TRANSLATION_DIS (1 << 8) 983 # define NONSURF_AP0_SWP_16BPP (1 << 20) 984 # define NONSURF_AP0_SWP_32BPP (1 << 21) 985 #define SURFACE0_INFO 0x0b0c 986 #define SURFACE0_LOWER_BOUND 0x0b04 987 #define SURFACE0_UPPER_BOUND 0x0b08 988 #define SURFACE1_INFO 0x0b1c 989 #define SURFACE1_LOWER_BOUND 0x0b14 990 #define SURFACE1_UPPER_BOUND 0x0b18 991 #define SURFACE2_INFO 0x0b2c 992 #define SURFACE2_LOWER_BOUND 0x0b24 993 #define SURFACE2_UPPER_BOUND 0x0b28 994 #define SURFACE3_INFO 0x0b3c 995 #define SURFACE3_LOWER_BOUND 0x0b34 996 #define SURFACE3_UPPER_BOUND 0x0b38 997 #define SURFACE4_INFO 0x0b4c 998 #define SURFACE4_LOWER_BOUND 0x0b44 999 #define SURFACE4_UPPER_BOUND 0x0b48 1000 #define SURFACE5_INFO 0x0b5c 1001 #define SURFACE5_LOWER_BOUND 0x0b54 1002 #define SURFACE5_UPPER_BOUND 0x0b58 1003 #define SURFACE6_INFO 0x0b6c 1004 #define SURFACE6_LOWER_BOUND 0x0b64 1005 #define SURFACE6_UPPER_BOUND 0x0b68 1006 #define SURFACE7_INFO 0x0b7c 1007 #define SURFACE7_LOWER_BOUND 0x0b74 1008 #define SURFACE7_UPPER_BOUND 0x0b78 1009 #define SW_SEMAPHORE 0x013c 1010 1011 #define TEST_DEBUG_CNTL 0x0120 1012 #define TEST_DEBUG_MUX 0x0124 1013 #define TEST_DEBUG_OUT 0x012c 1014 #define TMDS_PLL_CNTL 0x02a8 1015 #define TRAIL_BRES_DEC 0x1614 1016 #define TRAIL_BRES_ERR 0x160c 1017 #define TRAIL_BRES_INC 0x1610 1018 #define TRAIL_X 0x1618 1019 #define TRAIL_X_SUB 0x1620 1020 1021 #define VCLK_ECP_CNTL 0x0008 /* PLL */ 1022 # define VCLK_SRC_SEL_MASK 0x03 1023 # define VCLK_SRC_SEL_CPUCLK 0x00 1024 # define VCLK_SRC_SEL_PSCANCLK 0x01 1025 # define VCLK_SRC_SEL_BYTECLK 0x02 1026 # define VCLK_SRC_SEL_PPLLCLK 0x03 1027 #define VENDOR_ID 0x0f00 /* PCI */ 1028 #define VGA_DDA_CONFIG 0x02e8 1029 #define VGA_DDA_ON_OFF 0x02ec 1030 #define VID_BUFFER_CONTROL 0x0900 1031 #define VIDEOMUX_CNTL 0x0190 1032 #define VIPH_CONTROL 0x0c40 /* ? */ 1033 1034 #define WAIT_UNTIL 0x1720 1035 # define WAIT_CRTC_PFLIP (1 << 0) 1036 # define WAIT_2D_IDLECLEAN (1 << 16) 1037 # define WAIT_3D_IDLECLEAN (1 << 17) 1038 # define WAIT_HOST_IDLECLEAN (1 << 18) 1039 1040 #define X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1041 #define XCLK_CNTL 0x000d /* PLL */ 1042 #define XDLL_CNTL 0x000c /* PLL */ 1043 #define XPLL_CNTL 0x000b /* PLL */ 1044 1045 1046 1047 /* Registers for 3D/TCL */ 1048 #define PP_BORDER_COLOR_0 0x1d40 1049 #define PP_BORDER_COLOR_1 0x1d44 1050 #define PP_BORDER_COLOR_2 0x1d48 1051 #define PP_CNTL 0x1c38 1052 # define STIPPLE_ENABLE (1 << 0) 1053 # define SCISSOR_ENABLE (1 << 1) 1054 # define PATTERN_ENABLE (1 << 2) 1055 # define SHADOW_ENABLE (1 << 3) 1056 # define TEX_ENABLE_MASK (0xf << 4) 1057 # define TEX_0_ENABLE (1 << 4) 1058 # define TEX_1_ENABLE (1 << 5) 1059 # define TEX_2_ENABLE (1 << 6) 1060 # define TEX_3_ENABLE (1 << 7) 1061 # define TEX_BLEND_ENABLE_MASK (0xf << 12) 1062 # define TEX_BLEND_0_ENABLE (1 << 12) 1063 # define TEX_BLEND_1_ENABLE (1 << 13) 1064 # define TEX_BLEND_2_ENABLE (1 << 14) 1065 # define TEX_BLEND_3_ENABLE (1 << 15) 1066 # define PLANAR_YUV_ENABLE (1 << 20) 1067 # define SPECULAR_ENABLE (1 << 21) 1068 # define FOG_ENABLE (1 << 22) 1069 # define ALPHA_TEST_ENABLE (1 << 23) 1070 # define ANTI_ALIAS_NONE (0 << 24) 1071 # define ANTI_ALIAS_LINE (1 << 24) 1072 # define ANTI_ALIAS_POLY (2 << 24) 1073 # define ANTI_ALIAS_LINE_POLY (3 << 24) 1074 # define BUMP_MAP_ENABLE (1 << 26) 1075 # define BUMPED_MAP_T0 (0 << 27) 1076 # define BUMPED_MAP_T1 (1 << 27) 1077 # define BUMPED_MAP_T2 (2 << 27) 1078 # define TEX_3D_ENABLE_0 (1 << 29) 1079 # define TEX_3D_ENABLE_1 (1 << 30) 1080 # define MC_ENABLE (1 << 31) 1081 #define PP_FOG_COLOR 0x1c18 1082 # define FOG_COLOR_MASK 0x00ffffff 1083 # define FOG_VERTEX (0 << 24) 1084 # define FOG_TABLE (1 << 24) 1085 # define FOG_USE_DEPTH (0 << 25) 1086 # define FOG_USE_DIFFUSE_ALPHA (2 << 25) 1087 # define FOG_USE_SPEC_ALPHA (3 << 25) 1088 #define PP_LUM_MATRIX 0x1d00 1089 #define PP_MISC 0x1c14 1090 # define REF_ALPHA_MASK 0x000000ff 1091 # define ALPHA_TEST_FAIL (0 << 8) 1092 # define ALPHA_TEST_LESS (1 << 8) 1093 # define ALPHA_TEST_LEQUAL (2 << 8) 1094 # define ALPHA_TEST_EQUAL (3 << 8) 1095 # define ALPHA_TEST_GEQUAL (4 << 8) 1096 # define ALPHA_TEST_GREATER (5 << 8) 1097 # define ALPHA_TEST_NEQUAL (6 << 8) 1098 # define ALPHA_TEST_PASS (7 << 8) 1099 # define ALPHA_TEST_OP_MASK (7 << 8) 1100 # define CHROMA_FUNC_FAIL (0 << 16) 1101 # define CHROMA_FUNC_PASS (1 << 16) 1102 # define CHROMA_FUNC_NEQUAL (2 << 16) 1103 # define CHROMA_FUNC_EQUAL (3 << 16) 1104 # define CHROMA_KEY_NEAREST (0 << 18) 1105 # define CHROMA_KEY_ZERO (1 << 18) 1106 # define SHADOW_ID_AUTO_INC (1 << 20) 1107 # define SHADOW_FUNC_EQUAL (0 << 21) 1108 # define SHADOW_FUNC_NEQUAL (1 << 21) 1109 # define SHADOW_PASS_1 (0 << 22) 1110 # define SHADOW_PASS_2 (1 << 22) 1111 # define RIGHT_HAND_CUBE_D3D (0 << 24) 1112 # define RIGHT_HAND_CUBE_OGL (1 << 24) 1113 #define PP_ROT_MATRIX_0 0x1d58 1114 #define PP_ROT_MATRIX_1 0x1d5c 1115 #define PP_TXFILTER_0 0x1c54 1116 #define PP_TXFILTER_1 0x1c6c 1117 #define PP_TXFILTER_2 0x1c84 1118 # define MAG_FILTER_NEAREST (0 << 0) 1119 # define MAG_FILTER_LINEAR (1 << 0) 1120 # define MAG_FILTER_MASK (1 << 0) 1121 # define MIN_FILTER_NEAREST (0 << 1) 1122 # define MIN_FILTER_LINEAR (1 << 1) 1123 # define MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 1124 # define MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 1125 # define MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 1126 # define MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 1127 # define MIN_FILTER_ANISO_NEAREST (8 << 1) 1128 # define MIN_FILTER_ANISO_LINEAR (9 << 1) 1129 # define MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 1130 # define MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 1131 # define MIN_FILTER_MASK (15 << 1) 1132 # define MAX_ANISO_1_TO_1 (0 << 5) 1133 # define MAX_ANISO_2_TO_1 (1 << 5) 1134 # define MAX_ANISO_4_TO_1 (2 << 5) 1135 # define MAX_ANISO_8_TO_1 (3 << 5) 1136 # define MAX_ANISO_16_TO_1 (4 << 5) 1137 # define MAX_ANISO_MASK (7 << 5) 1138 # define LOD_BIAS_MASK (0xff << 8) 1139 # define LOD_BIAS_SHIFT 8 1140 # define MAX_MIP_LEVEL_MASK (0x0f << 16) 1141 # define MAX_MIP_LEVEL_SHIFT 16 1142 # define WRAPEN_S (1 << 22) 1143 # define CLAMP_S_WRAP (0 << 23) 1144 # define CLAMP_S_MIRROR (1 << 23) 1145 # define CLAMP_S_CLAMP_LAST (2 << 23) 1146 # define CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 1147 # define CLAMP_S_CLAMP_BORDER (4 << 23) 1148 # define CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 1149 # define CLAMP_S_MASK (7 << 23) 1150 # define WRAPEN_T (1 << 26) 1151 # define CLAMP_T_WRAP (0 << 27) 1152 # define CLAMP_T_MIRROR (1 << 27) 1153 # define CLAMP_T_CLAMP_LAST (2 << 27) 1154 # define CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 1155 # define CLAMP_T_CLAMP_BORDER (4 << 27) 1156 # define CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 1157 # define CLAMP_T_MASK (7 << 27) 1158 # define BORDER_MODE_OGL (0 << 31) 1159 # define BORDER_MODE_D3D (1 << 31) 1160 #define PP_TXFORMAT_0 0x1c58 1161 #define PP_TXFORMAT_1 0x1c70 1162 #define PP_TXFORMAT_2 0x1c88 1163 # define TXFORMAT_I8 (0 << 0) 1164 # define TXFORMAT_AI88 (1 << 0) 1165 # define TXFORMAT_RGB332 (2 << 0) 1166 # define TXFORMAT_ARGB1555 (3 << 0) 1167 # define TXFORMAT_RGB565 (4 << 0) 1168 # define TXFORMAT_ARGB4444 (5 << 0) 1169 # define TXFORMAT_ARGB8888 (6 << 0) 1170 # define TXFORMAT_RGBA8888 (7 << 0) 1171 # define TXFORMAT_Y8 (8 << 0) 1172 # define TXFORMAT_FORMAT_MASK (31 << 0) 1173 # define TXFORMAT_FORMAT_SHIFT 0 1174 # define TXFORMAT_APPLE_YUV_MODE (1 << 5) 1175 # define TXFORMAT_ALPHA_IN_MAP (1 << 6) 1176 # define TXFORMAT_NON_POWER2 (1 << 7) 1177 # define TXFORMAT_WIDTH_MASK (15 << 8) 1178 # define TXFORMAT_WIDTH_SHIFT 8 1179 # define TXFORMAT_HEIGHT_MASK (15 << 12) 1180 # define TXFORMAT_HEIGHT_SHIFT 12 1181 # define TXFORMAT_F5_WIDTH_MASK (15 << 16) 1182 # define TXFORMAT_F5_WIDTH_SHIFT 16 1183 # define TXFORMAT_F5_HEIGHT_MASK (15 << 20) 1184 # define TXFORMAT_F5_HEIGHT_SHIFT 20 1185 # define TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 1186 # define TXFORMAT_ST_ROUTE_MASK (3 << 24) 1187 # define TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 1188 # define TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 1189 # define TXFORMAT_ENDIAN_NO_SWAP (0 << 26) 1190 # define TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) 1191 # define TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) 1192 # define TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) 1193 # define TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 1194 # define TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 1195 # define TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 1196 # define TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) 1197 #define PP_CUBIC_FACES_0 0x1d24 1198 #define PP_CUBIC_FACES_1 0x1d28 1199 #define PP_CUBIC_FACES_2 0x1d2c 1200 # define FACE_WIDTH_1_SHIFT 0 1201 # define FACE_HEIGHT_1_SHIFT 4 1202 # define FACE_WIDTH_1_MASK (0xf << 0) 1203 # define FACE_HEIGHT_1_MASK (0xf << 4) 1204 # define FACE_WIDTH_2_SHIFT 8 1205 # define FACE_HEIGHT_2_SHIFT 12 1206 # define FACE_WIDTH_2_MASK (0xf << 8) 1207 # define FACE_HEIGHT_2_MASK (0xf << 12) 1208 # define FACE_WIDTH_3_SHIFT 16 1209 # define FACE_HEIGHT_3_SHIFT 20 1210 # define FACE_WIDTH_3_MASK (0xf << 16) 1211 # define FACE_HEIGHT_3_MASK (0xf << 20) 1212 # define FACE_WIDTH_4_SHIFT 24 1213 # define FACE_HEIGHT_4_SHIFT 28 1214 # define FACE_WIDTH_4_MASK (0xf << 24) 1215 # define FACE_HEIGHT_4_MASK (0xf << 28) 1216 1217 #define PP_TXOFFSET_0 0x1c5c 1218 #define PP_TXOFFSET_1 0x1c74 1219 #define PP_TXOFFSET_2 0x1c8c 1220 # define TXO_ENDIAN_NO_SWAP (0 << 0) 1221 # define TXO_ENDIAN_BYTE_SWAP (1 << 0) 1222 # define TXO_ENDIAN_WORD_SWAP (2 << 0) 1223 # define TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1224 # define TXO_MACRO_LINEAR (0 << 2) 1225 # define TXO_MACRO_TILE (1 << 2) 1226 # define TXO_MICRO_LINEAR (0 << 3) 1227 # define TXO_MICRO_TILE_X2 (1 << 3) 1228 # define TXO_MICRO_TILE_OPT (2 << 3) 1229 # define TXO_OFFSET_MASK 0xffffffe0 1230 # define TXO_OFFSET_SHIFT 5 1231 1232 #define PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1233 #define PP_CUBIC_OFFSET_T0_1 0x1dd4 1234 #define PP_CUBIC_OFFSET_T0_2 0x1dd8 1235 #define PP_CUBIC_OFFSET_T0_3 0x1ddc 1236 #define PP_CUBIC_OFFSET_T0_4 0x1de0 1237 #define PP_CUBIC_OFFSET_T1_0 0x1e00 1238 #define PP_CUBIC_OFFSET_T1_1 0x1e04 1239 #define PP_CUBIC_OFFSET_T1_2 0x1e08 1240 #define PP_CUBIC_OFFSET_T1_3 0x1e0c 1241 #define PP_CUBIC_OFFSET_T1_4 0x1e10 1242 #define PP_CUBIC_OFFSET_T2_0 0x1e14 1243 #define PP_CUBIC_OFFSET_T2_1 0x1e18 1244 #define PP_CUBIC_OFFSET_T2_2 0x1e1c 1245 #define PP_CUBIC_OFFSET_T2_3 0x1e20 1246 #define PP_CUBIC_OFFSET_T2_4 0x1e24 1247 1248 #define PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1249 #define PP_TEX_SIZE_1 0x1d0c 1250 #define PP_TEX_SIZE_2 0x1d14 1251 # define TEX_USIZE_MASK (0x7ff << 0) 1252 # define TEX_USIZE_SHIFT 0 1253 # define TEX_VSIZE_MASK (0x7ff << 16) 1254 # define TEX_VSIZE_SHIFT 16 1255 # define SIGNED_RGB_MASK (1 << 30) 1256 # define SIGNED_RGB_SHIFT 30 1257 # define SIGNED_ALPHA_MASK (1 << 31) 1258 # define SIGNED_ALPHA_SHIFT 31 1259 1260 #define PP_TXCBLEND_0 0x1c60 1261 #define PP_TXCBLEND_1 0x1c78 1262 #define PP_TXCBLEND_2 0x1c90 1263 # define COLOR_ARG_A_SHIFT 0 1264 # define COLOR_ARG_A_MASK (0x1f << 0) 1265 # define COLOR_ARG_A_ZERO (0 << 0) 1266 # define COLOR_ARG_A_CURRENT_COLOR (2 << 0) 1267 # define COLOR_ARG_A_CURRENT_ALPHA (3 << 0) 1268 # define COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) 1269 # define COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) 1270 # define COLOR_ARG_A_SPECULAR_COLOR (6 << 0) 1271 # define COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) 1272 # define COLOR_ARG_A_TFACTOR_COLOR (8 << 0) 1273 # define COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) 1274 # define COLOR_ARG_A_T0_COLOR (10 << 0) 1275 # define COLOR_ARG_A_T0_ALPHA (11 << 0) 1276 # define COLOR_ARG_A_T1_COLOR (12 << 0) 1277 # define COLOR_ARG_A_T1_ALPHA (13 << 0) 1278 # define COLOR_ARG_A_T2_COLOR (14 << 0) 1279 # define COLOR_ARG_A_T2_ALPHA (15 << 0) 1280 # define COLOR_ARG_A_T3_COLOR (16 << 0) 1281 # define COLOR_ARG_A_T3_ALPHA (17 << 0) 1282 # define COLOR_ARG_B_SHIFT 5 1283 # define COLOR_ARG_B_MASK (0x1f << 5) 1284 # define COLOR_ARG_B_ZERO (0 << 5) 1285 # define COLOR_ARG_B_CURRENT_COLOR (2 << 5) 1286 # define COLOR_ARG_B_CURRENT_ALPHA (3 << 5) 1287 # define COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) 1288 # define COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) 1289 # define COLOR_ARG_B_SPECULAR_COLOR (6 << 5) 1290 # define COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) 1291 # define COLOR_ARG_B_TFACTOR_COLOR (8 << 5) 1292 # define COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) 1293 # define COLOR_ARG_B_T0_COLOR (10 << 5) 1294 # define COLOR_ARG_B_T0_ALPHA (11 << 5) 1295 # define COLOR_ARG_B_T1_COLOR (12 << 5) 1296 # define COLOR_ARG_B_T1_ALPHA (13 << 5) 1297 # define COLOR_ARG_B_T2_COLOR (14 << 5) 1298 # define COLOR_ARG_B_T2_ALPHA (15 << 5) 1299 # define COLOR_ARG_B_T3_COLOR (16 << 5) 1300 # define COLOR_ARG_B_T3_ALPHA (17 << 5) 1301 # define COLOR_ARG_C_SHIFT 10 1302 # define COLOR_ARG_C_MASK (0x1f << 10) 1303 # define COLOR_ARG_C_ZERO (0 << 10) 1304 # define COLOR_ARG_C_CURRENT_COLOR (2 << 10) 1305 # define COLOR_ARG_C_CURRENT_ALPHA (3 << 10) 1306 # define COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) 1307 # define COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) 1308 # define COLOR_ARG_C_SPECULAR_COLOR (6 << 10) 1309 # define COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) 1310 # define COLOR_ARG_C_TFACTOR_COLOR (8 << 10) 1311 # define COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) 1312 # define COLOR_ARG_C_T0_COLOR (10 << 10) 1313 # define COLOR_ARG_C_T0_ALPHA (11 << 10) 1314 # define COLOR_ARG_C_T1_COLOR (12 << 10) 1315 # define COLOR_ARG_C_T1_ALPHA (13 << 10) 1316 # define COLOR_ARG_C_T2_COLOR (14 << 10) 1317 # define COLOR_ARG_C_T2_ALPHA (15 << 10) 1318 # define COLOR_ARG_C_T3_COLOR (16 << 10) 1319 # define COLOR_ARG_C_T3_ALPHA (17 << 10) 1320 # define COMP_ARG_A (1 << 15) 1321 # define COMP_ARG_A_SHIFT 15 1322 # define COMP_ARG_B (1 << 16) 1323 # define COMP_ARG_B_SHIFT 16 1324 # define COMP_ARG_C (1 << 17) 1325 # define COMP_ARG_C_SHIFT 17 1326 # define BLEND_CTL_MASK (7 << 18) 1327 # define BLEND_CTL_ADD (0 << 18) 1328 # define BLEND_CTL_SUBTRACT (1 << 18) 1329 # define BLEND_CTL_ADDSIGNED (2 << 18) 1330 # define BLEND_CTL_BLEND (3 << 18) 1331 # define BLEND_CTL_DOT3 (4 << 18) 1332 # define SCALE_SHIFT 21 1333 # define SCALE_MASK (3 << 21) 1334 # define SCALE_1X (0 << 21) 1335 # define SCALE_2X (1 << 21) 1336 # define SCALE_4X (2 << 21) 1337 # define CLAMP_TX (1 << 23) 1338 # define T0_EQ_TCUR (1 << 24) 1339 # define T1_EQ_TCUR (1 << 25) 1340 # define T2_EQ_TCUR (1 << 26) 1341 # define T3_EQ_TCUR (1 << 27) 1342 # define COLOR_ARG_MASK 0x1f 1343 # define COMP_ARG_SHIFT 15 1344 #define PP_TXABLEND_0 0x1c64 1345 #define PP_TXABLEND_1 0x1c7c 1346 #define PP_TXABLEND_2 0x1c94 1347 # define ALPHA_ARG_A_SHIFT 0 1348 # define ALPHA_ARG_A_MASK (0xf << 0) 1349 # define ALPHA_ARG_A_ZERO (0 << 0) 1350 # define ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) 1351 # define ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) 1352 # define ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) 1353 # define ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) 1354 # define ALPHA_ARG_A_T0_ALPHA (5 << 0) 1355 # define ALPHA_ARG_A_T1_ALPHA (6 << 0) 1356 # define ALPHA_ARG_A_T2_ALPHA (7 << 0) 1357 # define ALPHA_ARG_A_T3_ALPHA (8 << 0) 1358 # define ALPHA_ARG_B_SHIFT 4 1359 # define ALPHA_ARG_B_MASK (0xf << 4) 1360 # define ALPHA_ARG_B_ZERO (0 << 4) 1361 # define ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) 1362 # define ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) 1363 # define ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) 1364 # define ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) 1365 # define ALPHA_ARG_B_T0_ALPHA (5 << 4) 1366 # define ALPHA_ARG_B_T1_ALPHA (6 << 4) 1367 # define ALPHA_ARG_B_T2_ALPHA (7 << 4) 1368 # define ALPHA_ARG_B_T3_ALPHA (8 << 4) 1369 # define ALPHA_ARG_C_SHIFT 8 1370 # define ALPHA_ARG_C_MASK (0xf << 8) 1371 # define ALPHA_ARG_C_ZERO (0 << 8) 1372 # define ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) 1373 # define ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) 1374 # define ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) 1375 # define ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) 1376 # define ALPHA_ARG_C_T0_ALPHA (5 << 8) 1377 # define ALPHA_ARG_C_T1_ALPHA (6 << 8) 1378 # define ALPHA_ARG_C_T2_ALPHA (7 << 8) 1379 # define ALPHA_ARG_C_T3_ALPHA (8 << 8) 1380 # define DOT_ALPHA_DONT_REPLICATE (1 << 9) 1381 # define ALPHA_ARG_MASK 0xf 1382 1383 #define PP_TFACTOR_0 0x1c68 1384 #define PP_TFACTOR_1 0x1c80 1385 #define PP_TFACTOR_2 0x1c98 1386 1387 #define RB3D_BLENDCNTL 0x1c20 1388 # define COMB_FCN_MASK (3 << 12) 1389 # define COMB_FCN_ADD_CLAMP (0 << 12) 1390 # define COMB_FCN_ADD_NOCLAMP (1 << 12) 1391 # define COMB_FCN_SUB_CLAMP (2 << 12) 1392 # define COMB_FCN_SUB_NOCLAMP (3 << 12) 1393 # define SRC_BLEND_GL_ZERO (32 << 16) 1394 # define SRC_BLEND_GL_ONE (33 << 16) 1395 # define SRC_BLEND_GL_SRC_COLOR (34 << 16) 1396 # define SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 1397 # define SRC_BLEND_GL_DST_COLOR (36 << 16) 1398 # define SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 1399 # define SRC_BLEND_GL_SRC_ALPHA (38 << 16) 1400 # define SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 1401 # define SRC_BLEND_GL_DST_ALPHA (40 << 16) 1402 # define SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 1403 # define SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 1404 # define SRC_BLEND_MASK (63 << 16) 1405 # define DST_BLEND_GL_ZERO (32 << 24) 1406 # define DST_BLEND_GL_ONE (33 << 24) 1407 # define DST_BLEND_GL_SRC_COLOR (34 << 24) 1408 # define DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 1409 # define DST_BLEND_GL_DST_COLOR (36 << 24) 1410 # define DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 1411 # define DST_BLEND_GL_SRC_ALPHA (38 << 24) 1412 # define DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 1413 # define DST_BLEND_GL_DST_ALPHA (40 << 24) 1414 # define DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 1415 # define DST_BLEND_MASK (63 << 24) 1416 #define RB3D_CNTL 0x1c3c 1417 # define ALPHA_BLEND_ENABLE (1 << 0) 1418 # define PLANE_MASK_ENABLE (1 << 1) 1419 # define DITHER_ENABLE (1 << 2) 1420 # define ROUND_ENABLE (1 << 3) 1421 # define SCALE_DITHER_ENABLE (1 << 4) 1422 # define DITHER_INIT (1 << 5) 1423 # define ROP_ENABLE (1 << 6) 1424 # define STENCIL_ENABLE (1 << 7) 1425 # define Z_ENABLE (1 << 8) 1426 # define DEPTH_XZ_OFFEST_ENABLE (1 << 9) 1427 # define COLOR_FORMAT_ARGB1555 (3 << 10) 1428 # define COLOR_FORMAT_RGB565 (4 << 10) 1429 # define COLOR_FORMAT_ARGB8888 (6 << 10) 1430 # define COLOR_FORMAT_RGB332 (7 << 10) 1431 # define COLOR_FORMAT_Y8 (8 << 10) 1432 # define COLOR_FORMAT_RGB8 (9 << 10) 1433 # define COLOR_FORMAT_YUV422_VYUY (11 << 10) 1434 # define COLOR_FORMAT_YUV422_YVYU (12 << 10) 1435 # define COLOR_FORMAT_aYUV444 (14 << 10) 1436 # define COLOR_FORMAT_ARGB4444 (15 << 10) 1437 # define CLRCMP_FLIP_ENABLE (1 << 14) 1438 #define RB3D_COLOROFFSET 0x1c40 1439 # define COLOROFFSET_MASK 0xfffffff0 1440 #define RB3D_COLORPITCH 0x1c48 1441 # define COLORPITCH_MASK 0x000001ff8 1442 # define COLOR_TILE_ENABLE (1 << 16) 1443 # define COLOR_MICROTILE_ENABLE (1 << 17) 1444 # define COLOR_ENDIAN_NO_SWAP (0 << 18) 1445 # define COLOR_ENDIAN_WORD_SWAP (1 << 18) 1446 # define COLOR_ENDIAN_DWORD_SWAP (2 << 18) 1447 #define RB3D_DEPTHOFFSET 0x1c24 1448 #define RB3D_DEPTHPITCH 0x1c28 1449 # define DEPTHPITCH_MASK 0x00001ff8 1450 # define DEPTH_ENDIAN_NO_SWAP (0 << 18) 1451 # define DEPTH_ENDIAN_WORD_SWAP (1 << 18) 1452 # define DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 1453 #define RB3D_PLANEMASK 0x1d84 1454 #define RB3D_ROPCNTL 0x1d80 1455 # define ROP_MASK (15 << 8) 1456 # define ROP_CLEAR (0 << 8) 1457 # define ROP_NOR (1 << 8) 1458 # define ROP_AND_INVERTED (2 << 8) 1459 # define ROP_COPY_INVERTED (3 << 8) 1460 # define ROP_AND_REVERSE (4 << 8) 1461 # define ROP_INVERT (5 << 8) 1462 # define ROP_XOR (6 << 8) 1463 # define ROP_NAND (7 << 8) 1464 # define ROP_AND (8 << 8) 1465 # define ROP_EQUIV (9 << 8) 1466 # define ROP_NOOP (10 << 8) 1467 # define ROP_OR_INVERTED (11 << 8) 1468 # define ROP_COPY (12 << 8) 1469 # define ROP_OR_REVERSE (13 << 8) 1470 # define ROP_OR (14 << 8) 1471 # define ROP_SET (15 << 8) 1472 #define RB3D_STENCILREFMASK 0x1d7c 1473 # define STENCIL_REF_SHIFT 0 1474 # define STENCIL_REF_MASK (0xff << 0) 1475 # define STENCIL_MASK_SHIFT 16 1476 # define STENCIL_VALUE_MASK (0xff << 16) 1477 # define STENCIL_WRITEMASK_SHIFT 24 1478 # define STENCIL_WRITE_MASK (0xff << 24) 1479 #define RB3D_ZSTENCILCNTL 0x1c2c 1480 # define DEPTH_FORMAT_MASK (0xf << 0) 1481 # define DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1482 # define DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1483 # define DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 1484 # define DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 1485 # define DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 1486 # define DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) 1487 # define DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 1488 # define DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 1489 # define Z_TEST_NEVER (0 << 4) 1490 # define Z_TEST_LESS (1 << 4) 1491 # define Z_TEST_LEQUAL (2 << 4) 1492 # define Z_TEST_EQUAL (3 << 4) 1493 # define Z_TEST_GEQUAL (4 << 4) 1494 # define Z_TEST_GREATER (5 << 4) 1495 # define Z_TEST_NEQUAL (6 << 4) 1496 # define Z_TEST_ALWAYS (7 << 4) 1497 # define Z_TEST_MASK (7 << 4) 1498 # define STENCIL_TEST_NEVER (0 << 12) 1499 # define STENCIL_TEST_LESS (1 << 12) 1500 # define STENCIL_TEST_LEQUAL (2 << 12) 1501 # define STENCIL_TEST_EQUAL (3 << 12) 1502 # define STENCIL_TEST_GEQUAL (4 << 12) 1503 # define STENCIL_TEST_GREATER (5 << 12) 1504 # define STENCIL_TEST_NEQUAL (6 << 12) 1505 # define STENCIL_TEST_ALWAYS (7 << 12) 1506 # define STENCIL_TEST_MASK (0x7 << 12) 1507 # define STENCIL_FAIL_KEEP (0 << 16) 1508 # define STENCIL_FAIL_ZERO (1 << 16) 1509 # define STENCIL_FAIL_REPLACE (2 << 16) 1510 # define STENCIL_FAIL_INC (3 << 16) 1511 # define STENCIL_FAIL_DEC (4 << 16) 1512 # define STENCIL_FAIL_INVERT (5 << 16) 1513 # define STENCIL_FAIL_MASK (0x7 << 16) 1514 # define STENCIL_ZPASS_KEEP (0 << 20) 1515 # define STENCIL_ZPASS_ZERO (1 << 20) 1516 # define STENCIL_ZPASS_REPLACE (2 << 20) 1517 # define STENCIL_ZPASS_INC (3 << 20) 1518 # define STENCIL_ZPASS_DEC (4 << 20) 1519 # define STENCIL_ZPASS_INVERT (5 << 20) 1520 # define STENCIL_ZPASS_MASK (0x7 << 20) 1521 # define STENCIL_ZFAIL_KEEP (0 << 24) 1522 # define STENCIL_ZFAIL_ZERO (1 << 24) 1523 # define STENCIL_ZFAIL_REPLACE (2 << 24) 1524 # define STENCIL_ZFAIL_INC (3 << 24) 1525 # define STENCIL_ZFAIL_DEC (4 << 24) 1526 # define STENCIL_ZFAIL_INVERT (5 << 24) 1527 # define STENCIL_ZFAIL_MASK (0x7 << 24) 1528 # define Z_COMPRESSION_ENABLE (1 << 28) 1529 # define FORCE_Z_DIRTY (1 << 29) 1530 # define Z_WRITE_ENABLE (1 << 30) 1531 #define RE_LINE_PATTERN 0x1cd0 1532 # define LINE_PATTERN_MASK 0x0000ffff 1533 # define LINE_REPEAT_COUNT_SHIFT 16 1534 # define LINE_PATTERN_START_SHIFT 24 1535 # define LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 1536 # define LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 1537 # define LINE_PATTERN_AUTO_RESET (1 << 29) 1538 #define RE_LINE_STATE 0x1cd4 1539 # define LINE_CURRENT_PTR_SHIFT 0 1540 # define LINE_CURRENT_COUNT_SHIFT 8 1541 #define RE_MISC 0x26c4 1542 # define STIPPLE_COORD_MASK 0x1f 1543 # define STIPPLE_X_OFFSET_SHIFT 0 1544 # define STIPPLE_X_OFFSET_MASK (0x1f << 0) 1545 # define STIPPLE_Y_OFFSET_SHIFT 8 1546 # define STIPPLE_Y_OFFSET_MASK (0x1f << 8) 1547 # define STIPPLE_LITTLE_BIT_ORDER (0 << 16) 1548 # define STIPPLE_BIG_BIT_ORDER (1 << 16) 1549 #define RE_SOLID_COLOR 0x1c1c 1550 #define RE_TOP_LEFT 0x26c0 1551 # define RE_LEFT_SHIFT 0 1552 # define RE_TOP_SHIFT 16 1553 #define RE_WIDTH_HEIGHT 0x1c44 1554 # define RE_WIDTH_SHIFT 0 1555 # define RE_HEIGHT_SHIFT 16 1556 1557 #define SE_CNTL 0x1c4c 1558 # define FFACE_CULL_CW (0 << 0) 1559 # define FFACE_CULL_CCW (1 << 0) 1560 # define FFACE_CULL_DIR_MASK (1 << 0) 1561 # define BFACE_CULL (0 << 1) 1562 # define BFACE_SOLID (3 << 1) 1563 # define FFACE_CULL (0 << 3) 1564 # define FFACE_SOLID (3 << 3) 1565 # define FFACE_CULL_MASK (3 << 3) 1566 # define BADVTX_CULL_DISABLE (1 << 5) 1567 # define FLAT_SHADE_VTX_0 (0 << 6) 1568 # define FLAT_SHADE_VTX_1 (1 << 6) 1569 # define FLAT_SHADE_VTX_2 (2 << 6) 1570 # define FLAT_SHADE_VTX_LAST (3 << 6) 1571 # define DIFFUSE_SHADE_SOLID (0 << 8) 1572 # define DIFFUSE_SHADE_FLAT (1 << 8) 1573 # define DIFFUSE_SHADE_GOURAUD (2 << 8) 1574 # define DIFFUSE_SHADE_MASK (3 << 8) 1575 # define ALPHA_SHADE_SOLID (0 << 10) 1576 # define ALPHA_SHADE_FLAT (1 << 10) 1577 # define ALPHA_SHADE_GOURAUD (2 << 10) 1578 # define ALPHA_SHADE_MASK (3 << 10) 1579 # define SPECULAR_SHADE_SOLID (0 << 12) 1580 # define SPECULAR_SHADE_FLAT (1 << 12) 1581 # define SPECULAR_SHADE_GOURAUD (2 << 12) 1582 # define SPECULAR_SHADE_MASK (3 << 12) 1583 # define FOG_SHADE_SOLID (0 << 14) 1584 # define FOG_SHADE_FLAT (1 << 14) 1585 # define FOG_SHADE_GOURAUD (2 << 14) 1586 # define FOG_SHADE_MASK (3 << 14) 1587 # define ZBIAS_ENABLE_POINT (1 << 16) 1588 # define ZBIAS_ENABLE_LINE (1 << 17) 1589 # define ZBIAS_ENABLE_TRI (1 << 18) 1590 # define WIDELINE_ENABLE (1 << 20) 1591 # define VPORT_XY_XFORM_ENABLE (1 << 24) 1592 # define VPORT_Z_XFORM_ENABLE (1 << 25) 1593 # define VTX_PIX_CENTER_D3D (0 << 27) 1594 # define VTX_PIX_CENTER_OGL (1 << 27) 1595 # define ROUND_MODE_TRUNC (0 << 28) 1596 # define ROUND_MODE_ROUND (1 << 28) 1597 # define ROUND_MODE_ROUND_EVEN (2 << 28) 1598 # define ROUND_MODE_ROUND_ODD (3 << 28) 1599 # define ROUND_PREC_16TH_PIX (0 << 30) 1600 # define ROUND_PREC_8TH_PIX (1 << 30) 1601 # define ROUND_PREC_4TH_PIX (2 << 30) 1602 # define ROUND_PREC_HALF_PIX (3 << 30) 1603 #define SE_CNTL_STATUS 0x2140 1604 # define VC_NO_SWAP (0 << 0) 1605 # define VC_16BIT_SWAP (1 << 0) 1606 # define VC_32BIT_SWAP (2 << 0) 1607 # define VC_HALF_DWORD_SWAP (3 << 0) 1608 # define TCL_BYPASS (1 << 8) 1609 #define SE_COORD_FMT 0x1c50 1610 # define VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) 1611 # define VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) 1612 # define VTX_ST0_NONPARAMETRIC (1 << 8) 1613 # define VTX_ST1_NONPARAMETRIC (1 << 9) 1614 # define VTX_ST2_NONPARAMETRIC (1 << 10) 1615 # define VTX_ST3_NONPARAMETRIC (1 << 11) 1616 # define VTX_W0_NORMALIZE (1 << 12) 1617 # define VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) 1618 # define VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) 1619 # define VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) 1620 # define VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) 1621 # define VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) 1622 # define TEX1_W_ROUTING_USE_W0 (0 << 26) 1623 # define TEX1_W_ROUTING_USE_Q1 (1 << 26) 1624 #define SE_LINE_WIDTH 0x1db8 1625 #define SE_TCL_LIGHT_MODEL_CTL 0x226c 1626 # define LIGHTING_ENABLE (1 << 0) 1627 # define LIGHT_IN_MODELSPACE (1 << 1) 1628 # define LOCAL_VIEWER (1 << 2) 1629 # define NORMALIZE_NORMALS (1 << 3) 1630 # define RESCALE_NORMALS (1 << 4) 1631 # define SPECULAR_LIGHTS (1 << 5) 1632 # define DIFFUSE_SPECULAR_COMBINE (1 << 6) 1633 # define LIGHT_ALPHA (1 << 7) 1634 # define LOCAL_LIGHT_VEC_GL (1 << 8) 1635 # define LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) 1636 # define LM_SOURCE_STATE_PREMULT 0 1637 # define LM_SOURCE_STATE_MULT 1 1638 # define LM_SOURCE_VERTEX_DIFFUSE 2 1639 # define LM_SOURCE_VERTEX_SPECULAR 3 1640 # define EMISSIVE_SOURCE_SHIFT 16 1641 # define AMBIENT_SOURCE_SHIFT 18 1642 # define DIFFUSE_SOURCE_SHIFT 20 1643 # define SPECULAR_SOURCE_SHIFT 22 1644 #define SE_TCL_MATERIAL_AMBIENT_RED 0x2220 1645 #define SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 1646 #define SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 1647 #define SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c 1648 #define SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 1649 #define SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 1650 #define SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 1651 #define SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c 1652 #define SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1653 #define SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 1654 #define SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 1655 #define SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c 1656 #define SE_TCL_MATERIAL_SPECULAR_RED 0x2240 1657 #define SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 1658 #define SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 1659 #define SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c 1660 #define SE_TCL_MATRIX_SELECT_0 0x225c 1661 # define MODELVIEW_0_SHIFT 0 1662 # define MODELVIEW_1_SHIFT 4 1663 # define MODELVIEW_2_SHIFT 8 1664 # define MODELVIEW_3_SHIFT 12 1665 # define IT_MODELVIEW_0_SHIFT 16 1666 # define IT_MODELVIEW_1_SHIFT 20 1667 # define IT_MODELVIEW_2_SHIFT 24 1668 # define IT_MODELVIEW_3_SHIFT 28 1669 #define SE_TCL_MATRIX_SELECT_1 0x2260 1670 # define MODELPROJECT_0_SHIFT 0 1671 # define MODELPROJECT_1_SHIFT 4 1672 # define MODELPROJECT_2_SHIFT 8 1673 # define MODELPROJECT_3_SHIFT 12 1674 # define TEXMAT_0_SHIFT 16 1675 # define TEXMAT_1_SHIFT 20 1676 # define TEXMAT_2_SHIFT 24 1677 # define TEXMAT_3_SHIFT 28 1678 1679 1680 #define SE_TCL_OUTPUT_VTX_FMT 0x2254 1681 # define TCL_VTX_W0 (1 << 0) 1682 # define TCL_VTX_FP_DIFFUSE (1 << 1) 1683 # define TCL_VTX_FP_ALPHA (1 << 2) 1684 # define TCL_VTX_PK_DIFFUSE (1 << 3) 1685 # define TCL_VTX_FP_SPEC (1 << 4) 1686 # define TCL_VTX_FP_FOG (1 << 5) 1687 # define TCL_VTX_PK_SPEC (1 << 6) 1688 # define TCL_VTX_ST0 (1 << 7) 1689 # define TCL_VTX_ST1 (1 << 8) 1690 # define TCL_VTX_Q1 (1 << 9) 1691 # define TCL_VTX_ST2 (1 << 10) 1692 # define TCL_VTX_Q2 (1 << 11) 1693 # define TCL_VTX_ST3 (1 << 12) 1694 # define TCL_VTX_Q3 (1 << 13) 1695 # define TCL_VTX_Q0 (1 << 14) 1696 # define TCL_VTX_WEIGHT_COUNT_SHIFT 15 1697 # define TCL_VTX_NORM0 (1 << 18) 1698 # define TCL_VTX_XY1 (1 << 27) 1699 # define TCL_VTX_Z1 (1 << 28) 1700 # define TCL_VTX_W1 (1 << 29) 1701 # define TCL_VTX_NORM1 (1 << 30) 1702 # define TCL_VTX_Z0 (1 << 31) 1703 1704 #define SE_TCL_OUTPUT_VTX_SEL 0x2258 1705 # define TCL_COMPUTE_XYZW (1 << 0) 1706 # define TCL_COMPUTE_DIFFUSE (1 << 1) 1707 # define TCL_COMPUTE_SPECULAR (1 << 2) 1708 # define TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) 1709 # define TCL_FORCE_INORDER_PROC (1 << 4) 1710 # define TCL_TEX_INPUT_TEX_0 0 1711 # define TCL_TEX_INPUT_TEX_1 1 1712 # define TCL_TEX_INPUT_TEX_2 2 1713 # define TCL_TEX_INPUT_TEX_3 3 1714 # define TCL_TEX_COMPUTED_TEX_0 8 1715 # define TCL_TEX_COMPUTED_TEX_1 9 1716 # define TCL_TEX_COMPUTED_TEX_2 10 1717 # define TCL_TEX_COMPUTED_TEX_3 11 1718 # define TCL_TEX_0_OUTPUT_SHIFT 16 1719 # define TCL_TEX_1_OUTPUT_SHIFT 20 1720 # define TCL_TEX_2_OUTPUT_SHIFT 24 1721 # define TCL_TEX_3_OUTPUT_SHIFT 28 1722 1723 #define SE_TCL_PER_LIGHT_CTL_0 0x2270 1724 # define LIGHT_0_ENABLE (1 << 0) 1725 # define LIGHT_0_ENABLE_AMBIENT (1 << 1) 1726 # define LIGHT_0_ENABLE_SPECULAR (1 << 2) 1727 # define LIGHT_0_IS_LOCAL (1 << 3) 1728 # define LIGHT_0_IS_SPOT (1 << 4) 1729 # define LIGHT_0_DUAL_CONE (1 << 5) 1730 # define LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) 1731 # define LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) 1732 # define LIGHT_0_SHIFT 0 1733 # define LIGHT_1_ENABLE (1 << 16) 1734 # define LIGHT_1_ENABLE_AMBIENT (1 << 17) 1735 # define LIGHT_1_ENABLE_SPECULAR (1 << 18) 1736 # define LIGHT_1_IS_LOCAL (1 << 19) 1737 # define LIGHT_1_IS_SPOT (1 << 20) 1738 # define LIGHT_1_DUAL_CONE (1 << 21) 1739 # define LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) 1740 # define LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) 1741 # define LIGHT_1_SHIFT 16 1742 #define SE_TCL_PER_LIGHT_CTL_1 0x2274 1743 # define LIGHT_2_SHIFT 0 1744 # define LIGHT_3_SHIFT 16 1745 #define SE_TCL_PER_LIGHT_CTL_2 0x2278 1746 # define LIGHT_4_SHIFT 0 1747 # define LIGHT_5_SHIFT 16 1748 #define SE_TCL_PER_LIGHT_CTL_3 0x227c 1749 # define LIGHT_6_SHIFT 0 1750 # define LIGHT_7_SHIFT 16 1751 1752 #define SE_TCL_SHININESS 0x2250 1753 1754 #define SE_TCL_TEXTURE_PROC_CTL 0x2268 1755 # define TEXGEN_TEXMAT_0_ENABLE (1 << 0) 1756 # define TEXGEN_TEXMAT_1_ENABLE (1 << 1) 1757 # define TEXGEN_TEXMAT_2_ENABLE (1 << 2) 1758 # define TEXGEN_TEXMAT_3_ENABLE (1 << 3) 1759 # define TEXMAT_0_ENABLE (1 << 4) 1760 # define TEXMAT_1_ENABLE (1 << 5) 1761 # define TEXMAT_2_ENABLE (1 << 6) 1762 # define TEXMAT_3_ENABLE (1 << 7) 1763 # define TEXGEN_INPUT_MASK 0xf 1764 # define TEXGEN_INPUT_TEXCOORD_0 0 1765 # define TEXGEN_INPUT_TEXCOORD_1 1 1766 # define TEXGEN_INPUT_TEXCOORD_2 2 1767 # define TEXGEN_INPUT_TEXCOORD_3 3 1768 # define TEXGEN_INPUT_OBJ 4 1769 # define TEXGEN_INPUT_EYE 5 1770 # define TEXGEN_INPUT_EYE_NORMAL 6 1771 # define TEXGEN_INPUT_EYE_REFLECT 7 1772 # define TEXGEN_INPUT_EYE_NORMALIZED 8 1773 # define TEXGEN_0_INPUT_SHIFT 16 1774 # define TEXGEN_1_INPUT_SHIFT 20 1775 # define TEXGEN_2_INPUT_SHIFT 24 1776 # define TEXGEN_3_INPUT_SHIFT 28 1777 1778 #define SE_TCL_UCP_VERT_BLEND_CTL 0x2264 1779 # define UCP_IN_CLIP_SPACE (1 << 0) 1780 # define UCP_IN_MODEL_SPACE (1 << 1) 1781 # define UCP_ENABLE_0 (1 << 2) 1782 # define UCP_ENABLE_1 (1 << 3) 1783 # define UCP_ENABLE_2 (1 << 4) 1784 # define UCP_ENABLE_3 (1 << 5) 1785 # define UCP_ENABLE_4 (1 << 6) 1786 # define UCP_ENABLE_5 (1 << 7) 1787 # define TCL_FOG_MASK (3 << 8) 1788 # define TCL_FOG_DISABLE (0 << 8) 1789 # define TCL_FOG_EXP (1 << 8) 1790 # define TCL_FOG_EXP2 (2 << 8) 1791 # define TCL_FOG_LINEAR (3 << 8) 1792 # define RNG_BASED_FOG (1 << 10) 1793 # define LIGHT_TWOSIDE (1 << 11) 1794 # define BLEND_OP_COUNT_MASK (7 << 12) 1795 # define BLEND_OP_COUNT_SHIFT 12 1796 # define POSITION_BLEND_OP_ENABLE (1 << 16) 1797 # define NORMAL_BLEND_OP_ENABLE (1 << 17) 1798 # define VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) 1799 # define VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) 1800 # define VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) 1801 # define VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) 1802 # define VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) 1803 # define VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) 1804 # define VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) 1805 # define VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) 1806 # define VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) 1807 # define CULL_FRONT_IS_CW (0 << 28) 1808 # define CULL_FRONT_IS_CCW (1 << 28) 1809 # define CULL_FRONT (1 << 29) 1810 # define CULL_BACK (1 << 30) 1811 # define FORCE_W_TO_ONE (1 << 31) 1812 1813 #define SE_VPORT_XSCALE 0x1d98 1814 #define SE_VPORT_XOFFSET 0x1d9c 1815 #define SE_VPORT_YSCALE 0x1da0 1816 #define SE_VPORT_YOFFSET 0x1da4 1817 #define SE_VPORT_ZSCALE 0x1da8 1818 #define SE_VPORT_ZOFFSET 0x1dac 1819 #define SE_ZBIAS_FACTOR 0x1db0 1820 #define SE_ZBIAS_CONSTANT 0x1db4 1821 1822 1823 1824 /* Registers for CP and Microcode Engine */ 1825 #define CP_ME_RAM_ADDR 0x07d4 1826 #define CP_ME_RAM_RADDR 0x07d8 1827 #define CP_ME_RAM_DATAH 0x07dc 1828 #define CP_ME_RAM_DATAL 0x07e0 1829 1830 #define CP_RB_BASE 0x0700 1831 #define CP_RB_CNTL 0x0704 1832 #define CP_RB_RPTR_ADDR 0x070c 1833 #define CP_RB_RPTR 0x0710 1834 #define CP_RB_WPTR 0x0714 1835 1836 #define CP_IB_BASE 0x0738 1837 #define CP_IB_BUFSZ 0x073c 1838 1839 #define CP_CSQ_CNTL 0x0740 1840 # define CSQ_CNT_PRIMARY_MASK (0xff << 0) 1841 # define CSQ_PRIDIS_INDDIS (0 << 28) 1842 # define CSQ_PRIPIO_INDDIS (1 << 28) 1843 # define CSQ_PRIBM_INDDIS (2 << 28) 1844 # define CSQ_PRIPIO_INDBM (3 << 28) 1845 # define CSQ_PRIBM_INDBM (4 << 28) 1846 # define CSQ_PRIPIO_INDPIO (15 << 28) 1847 #define CP_CSQ_STAT 0x07f8 1848 # define CSQ_RPTR_PRIMARY_MASK (0xff << 0) 1849 # define CSQ_WPTR_PRIMARY_MASK (0xff << 8) 1850 # define CSQ_RPTR_INDIRECT_MASK (0xff << 16) 1851 # define CSQ_WPTR_INDIRECT_MASK (0xff << 24) 1852 #define CP_CSQ_ADDR 0x07f0 1853 #define CP_CSQ_DATA 0x07f4 1854 #define CP_CSQ_APER_PRIMARY 0x1000 1855 #define CP_CSQ_APER_INDIRECT 0x1300 1856 1857 #define CP_RB_WPTR_DELAY 0x0718 1858 # define PRE_WRITE_TIMER_SHIFT 0 1859 # define PRE_WRITE_LIMIT_SHIFT 23 1860 1861 #define AIC_CNTL 0x01d0 1862 # define PCIGART_TRANSLATE_EN (1 << 0) 1863 1864 1865 /* Constants */ 1866 #define AGP_TEX_OFFSET 0x02000000 1867 1868 #define LAST_FRAME_REG GUI_SCRATCH_REG0 1869 #define LAST_CLEAR_REG GUI_SCRATCH_REG2 1870 1871 1872 /* CP packet types */ 1873 #define CP_PACKET0 0x00000000 1874 #define CP_PACKET1 0x40000000 1875 #define CP_PACKET2 0x80000000 1876 #define CP_PACKET3 0xC0000000 1877 # define CP_PACKET_MASK 0xC0000000 1878 # define CP_PACKET_COUNT_MASK 0x3fff0000 1879 # define CP_PACKET_MAX_DWORDS (1 << 12) 1880 # define CP_PACKET0_REG_MASK 0x000007ff 1881 # define CP_PACKET1_REG0_MASK 0x000007ff 1882 # define CP_PACKET1_REG1_MASK 0x003ff800 1883 1884 #define CP_PACKET0_ONE_REG_WR 0x00008000 1885 1886 #define CP_PACKET3_NOP 0xC0001000 1887 #define CP_PACKET3_NEXT_CHAR 0xC0001900 1888 #define CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 1889 #define CP_PACKET3_SET_SCISSORS 0xC0001E00 1890 #define CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 1891 #define CP_PACKET3_LOAD_MICROCODE 0xC0002400 1892 #define CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 1893 #define CP_PACKET3_3D_DRAW_VBUF 0xC0002800 1894 #define CP_PACKET3_3D_DRAW_IMMD 0xC0002900 1895 #define CP_PACKET3_3D_DRAW_INDX 0xC0002A00 1896 #define CP_PACKET3_LOAD_PALETTE 0xC0002C00 1897 #define CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 1898 #define CP_PACKET3_CNTL_PAINT 0xC0009100 1899 #define CP_PACKET3_CNTL_BITBLT 0xC0009200 1900 #define CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 1901 #define CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 1902 #define CP_PACKET3_CNTL_POLYLINE 0xC0009500 1903 #define CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 1904 #define CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 1905 #define CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 1906 #define CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 1907 1908 #define CP_VC_FRMT_XY 0x00000000 1909 #define CP_VC_FRMT_W0 0x00000001 1910 #define CP_VC_FRMT_FPCOLOR 0x00000002 1911 #define CP_VC_FRMT_FPALPHA 0x00000004 1912 #define CP_VC_FRMT_PKCOLOR 0x00000008 1913 #define CP_VC_FRMT_FPSPEC 0x00000010 1914 #define CP_VC_FRMT_FPFOG 0x00000020 1915 #define CP_VC_FRMT_PKSPEC 0x00000040 1916 #define CP_VC_FRMT_ST0 0x00000080 1917 #define CP_VC_FRMT_ST1 0x00000100 1918 #define CP_VC_FRMT_Q1 0x00000200 1919 #define CP_VC_FRMT_ST2 0x00000400 1920 #define CP_VC_FRMT_Q2 0x00000800 1921 #define CP_VC_FRMT_ST3 0x00001000 1922 #define CP_VC_FRMT_Q3 0x00002000 1923 #define CP_VC_FRMT_Q0 0x00004000 1924 #define CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 1925 #define CP_VC_FRMT_N0 0x00040000 1926 #define CP_VC_FRMT_XY1 0x08000000 1927 #define CP_VC_FRMT_Z1 0x10000000 1928 #define CP_VC_FRMT_W1 0x20000000 1929 #define CP_VC_FRMT_N1 0x40000000 1930 #define CP_VC_FRMT_Z 0x80000000 1931 1932 #define CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 1933 #define CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 1934 #define CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 1935 #define CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 1936 #define CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 1937 #define CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 1938 #define CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 1939 #define CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 1940 #define CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 1941 #define CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 1942 #define CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a 1943 #define CP_VC_CNTL_PRIM_WALK_IND 0x00000010 1944 #define CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 1945 #define CP_VC_CNTL_PRIM_WALK_RING 0x00000030 1946 #define CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 1947 #define CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 1948 #define CP_VC_CNTL_MAOS_ENABLE 0x00000080 1949 #define CP_VC_CNTL_VTX_FMT_NON_MODE 0x00000000 1950 #define CP_VC_CNTL_VTX_FMT_MODE 0x00000100 1951 #define CP_VC_CNTL_TCL_DISABLE 0x00000000 1952 #define CP_VC_CNTL_TCL_ENABLE 0x00000200 1953 #define CP_VC_CNTL_NUM_SHIFT 16 1954 1955 #define VS_MATRIX_0_ADDR 0 1956 #define VS_MATRIX_1_ADDR 4 1957 #define VS_MATRIX_2_ADDR 8 1958 #define VS_MATRIX_3_ADDR 12 1959 #define VS_MATRIX_4_ADDR 16 1960 #define VS_MATRIX_5_ADDR 20 1961 #define VS_MATRIX_6_ADDR 24 1962 #define VS_MATRIX_7_ADDR 28 1963 #define VS_MATRIX_8_ADDR 32 1964 #define VS_MATRIX_9_ADDR 36 1965 #define VS_MATRIX_10_ADDR 40 1966 #define VS_MATRIX_11_ADDR 44 1967 #define VS_MATRIX_12_ADDR 48 1968 #define VS_MATRIX_13_ADDR 52 1969 #define VS_MATRIX_14_ADDR 56 1970 #define VS_MATRIX_15_ADDR 60 1971 #define VS_LIGHT_AMBIENT_ADDR 64 1972 #define VS_LIGHT_DIFFUSE_ADDR 72 1973 #define VS_LIGHT_SPECULAR_ADDR 80 1974 #define VS_LIGHT_DIRPOS_ADDR 88 1975 #define VS_LIGHT_HWVSPOT_ADDR 96 1976 #define VS_LIGHT_ATTENUATION_ADDR 104 1977 #define VS_MATRIX_EYE2CLIP_ADDR 112 1978 #define VS_UCP_ADDR 116 1979 #define VS_GLOBAL_AMBIENT_ADDR 122 1980 #define VS_FOG_PARAM_ADDR 123 1981 #define VS_EYE_VECTOR_ADDR 124 1982 1983 #define SS_LIGHT_DCD_ADDR 0 1984 #define SS_LIGHT_SPOT_EXPONENT_ADDR 8 1985 #define SS_LIGHT_SPOT_CUTOFF_ADDR 16 1986 #define SS_LIGHT_SPECULAR_THRESH_ADDR 24 1987 #define SS_LIGHT_RANGE_CUTOFF_ADDR 32 1988 #define SS_VERT_GUARD_CLIP_ADJ_ADDR 48 1989 #define SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 1990 #define SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 1991 #define SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 1992 #define SS_SHININESS 60 1993 1994 1995 /* ATI Technologies Inc */ 1996 #define ATI_PCIVID 0x1002 1997 1998 struct pciids { 1999 ushort did; 2000 int type; 2001 char* name; 2002 }; 2003 2004 enum { 2005 ATI_R300, 2006 ATI_RV250, 2007 ATI_R250, 2008 ATI_RV200, 2009 ATI_R200, 2010 ATI_RV100, 2011 ATI_R100, 2012 ATI_M6, 2013 ATI_M7, 2014 ATI_M9, 2015 }; 2016 2017 struct pciids radeon_pciids[] = { 2018 /* ATI_M6, LY */ 2019 /* ATI_M6, LZ */ 2020 2021 0x4c57, ATI_M7, "Radeon Mobility M7 LW [Radeon Mobility 7500]", 2022 0x4c58, ATI_M7, "Radeon RV200 LX [Mobility FireGL 7800 M7]", 2023 2024 0x4c64, ATI_M9, "Radeon R250 Ld [Radeon Mobility 9000 M9]", 2025 0x4c65, ATI_M9, "Radeon R250 Le [Radeon Mobility 9000 M9]", 2026 0x4c66, ATI_M9, "Radeon R250 Lf [Radeon Mobility 9000 M9]", 2027 0x4c67, ATI_M9, "Radeon R250 Lg [Radeon Mobility 9000 M9]", 2028 2029 0x5159, ATI_RV100, "Radeon RV100 QY [Radeon 7000/VE]", 2030 0x515a, ATI_RV100, "Radeon RV100 QZ [Radeon 7000/VE]", 2031 2032 0x5144, ATI_R100, "Radeon R100 QD [Radeon 7200]", 2033 0x5145, ATI_R100, "Radeon R100 QE", 2034 0x5146, ATI_R100, "Radeon R100 QF", 2035 0x5147, ATI_R100, "Radeon R100 QG", 2036 2037 0x5148, ATI_R200, "Radeon R200 QH [Radeon 8500]", 2038 0x5149, ATI_R200, "Radeon R200 QI", 2039 0x514a, ATI_R200, "Radeon R200 QJ", 2040 0x514b, ATI_R200, "Radeon R200 QK", 2041 0x514c, ATI_R200, "Radeon R200 QL [Radeon 8500 LE]", 2042 0x514d, ATI_R200, "Radeon R200 QM [Radeon 9100]", 2043 0x514e, ATI_R200, "Radeon R200 QN [Radeon 8500LE]", 2044 0x514f, ATI_R200, "Radeon R200 QO [Radeon 8500LE]", 2045 0x5168, ATI_R200, "Radeon R200 Qh", 2046 0x5169, ATI_R200, "Radeon R200 Qi", 2047 0x516a, ATI_R200, "Radeon R200 Qj", 2048 0x516b, ATI_R200, "Radeon R200 Qk", 2049 0x516c, ATI_R200, "Radeon R200 Ql", 2050 2051 0x5157, ATI_RV200, "Radeon RV200 QW [Radeon 7500]", 2052 0x5158, ATI_RV200, "Radeon RV200 QX [Radeon 7500]", 2053 2054 0x4964, ATI_RV250, "Radeon R250 Id [Radeon 9000]", 2055 0x4965, ATI_RV250, "Radeon R250 Ie [Radeon 9000]", 2056 0x4966, ATI_RV250, "Radeon R250 If [Radeon 9000]", 2057 0x4967, ATI_RV250, "Radeon R250 Ig [Radeon 9000]", 2058 2059 0x4144, ATI_R300, "Radeon R300 AD [Radeon 9500 Pro]", 2060 0x4145, ATI_R300, "Radeon R300 AE [Radeon 9500 Pro]", 2061 0x4146, ATI_R300, "Radeon R300 AF [Radeon 9500 Pro]", 2062 0x4147, ATI_R300, "Radeon R300 AG [FireGL Z1/X1]", 2063 0x4e44, ATI_R300, "Radeon R300 ND [Radeon 9700]", 2064 0x4e45, ATI_R300, "Radeon R300 NE [Radeon 9700]", 2065 0x4e46, ATI_R300, "Radeon R300 NF [Radeon 9700]", 2066 0x4e47, ATI_R300, "Radeon R300 NG [FireGL X1]", 2067 2068 0x4e64, ATI_R300, "Radeon R300 [Radeon 9700 Pro] (Secondary)", 2069 0x4e65, ATI_R300, "Radeon R300 [Radeon 9700] (Secondary)", 2070 0x4e66, ATI_R300, "Radeon R300 [Radeon 9700] (Secondary)", 2071 0x4e67, ATI_R300, "Radeon R300 [FireGL X1] (Secondary)", 2072 2073 0 2074 }; 2075