1this is a plan 9 port to the Trimslice with tegra2 soc: dual-core, 2dual-issue 1GHz Cortex-A9 system (v7a arch). 3 4dram is 1GB at 0. 5linux believes that u-boot runs in the bottom 4MB. 6the l2 cache is a non-architectural bag nailed on the side. 7mp arm systems have a generic interrupt controller; this one is gic v1(!). 8vfp 3 floating-point is present. 9 10section numbers (§) are in the tegra 2 tech. ref. man. 11for a minimal cpu server, need these devices to work: 12 clock signals §5 (leave to u-boot), 13 pad mux + gpio crap §8, §11 and §18 (leave to u-boot), 14☑ 1 cpu §13, 15☑ uart (16[45]50) §22, 16☑ gic (gic.v1.pdf), 17☑ clock §6—7, 18☑ ether8169 via pcie §31. 19then add these: 20☑ 2nd cpu (cortex.a9.mpcore.pdf), 21☑ l2 cache (l2cache.pl310.pdf, errata), 22☑ fpu (cortex.a9.fp.pdf), 23☑ user profiling, 24 kprof, 25 in-line 64-bit arithmetic, 26eventually might want: 27 usb (e.g., for sata) §26, 28 nor flash §17, 29 video §29, 30and the really horrid ones: 31 nand flash §16, 32 mmc §25. 33 34physical memory map 35 360 1GB ram 37 3840000000 256K iram (audio/video memory) 3950000000 cortex-a9 cpu regs, periphbase, intr distrib, memsel, 40 l2 cache 4154000000 graphics regs 4258000000 gart (graphics window) 4360000000 256MB ppsb bus dev regs, including semas, intr ctlr, dma, 44 arm7 cache, gpio, except. vects 4570000000 256MB apc bus regs, including uarts, nand, nor, spi, rtc 46 4780000000 1GB ahb extern mem, pcie for cpu only 4890000000-97ffffff pcie 0 mem(?) 49a0000000-a7ffffff pcie 0 prefetch mem, includes rtl8111dl ether(?) 50a0020000 ether region 4 51a0024000 ether region 2 52 53c0000000 256MB ahb bus virtual b0000000 54c3000000-c80007ff 81MB ide, usb, sata, mmc 55d0000000 256MB nor flash virtual 40000000 56f000f000 4K mmu tlb 57fff00000 48K irom boot code 58ffff0000 64K high vectors 59 60use 0xc0000000 as KZERO. 61