1see §5.4.40 (p.142) pllx_* (2 regs) 2 3out of u-boot, these are the settings: 4--- 5pllx base 0x4003e80c: 6 enabled, no locked 7 divp == 0 (post divider == 2^0 == 1) 8 divn == 1000 (feedback divider) 9 divm == 12 (input divider) 10 misc 0x100: pllx_cpcon == 1 [ should be 12 ] 11super cclk divider 0x80000000: 12 enabled 13 dividend == 0 (thus 1) 14 divisor == 0 (thus 1) 15super sclk divider 0x0: 16 disabled 17 dividend == 0 (thus 1) 18 divisor == 0 (thus 1) 19--- 20