1/* 2 * 24K Erratum 48: Lost Data on Stores During Refill. 3 4 Problem: The FSB (fetch store buffer) acts as an intermediate buffer 5 for the data cache refills and store data. The following describes 6 the scenario where the store data could be lost. 7 8 * A data cache miss, due to either a load or a store, causing fill 9 data to be supplied by the memory subsystem 10 * The first three doublewords of fill data are returned and written 11 into the cache 12 * A sequence of four stores occurs in consecutive cycles around the 13 final doubleword of the fill: 14 * Store A 15 * Store B 16 * Store C 17 * Zero, One or more instructions 18 * Store D 19 20 The four stores A-D must be to different doublewords of the line that 21 is being filled. The fourth instruction in the sequence above permits 22 the fill of the final doubleword to be transferred from the FSB into 23 the cache. In the sequence above, the stores may be either integer 24 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, 25 swxc1, sdxc1, suxc1) stores, as long as the four stores are to 26 different doublewords on the line. If the floating point unit is 27 running in 1:2 mode, it is not possible to create the sequence above 28 using only floating point store instructions. In this case, the cache 29 line being filled is incorrectly marked invalid, thereby losing the 30 data from any store to the line that occurs between the original miss 31 and the completion of the five cycle sequence shown above. 32 33 * Run the data cache in write-through mode. 34 * Insert a non-store instruction between 35 Store A and Store B or Store B and Store C. 36 */ 37