1 #define STACKTOP 0xFFFFFE00 2 3 #define ARM_FDIV (40 << PLL_FDIV_SH) 4 #define DDR_FDIV (32 << PLL_FDIV_SH) 5 #define IO_FDIV (30 << PLL_FDIV_SH) 6 #define PLL_CFG_VAL(CP, RES, CNT) ((CP)<<8 | (RES)<<4 | (CNT)<<12) 7 #define ARM_PLL_CFG_VAL PLL_CFG_VAL(2, 2, 250) 8 #define DDR_PLL_CFG_VAL PLL_CFG_VAL(2, 2, 300) 9 #define IO_PLL_CFG_VAL PLL_CFG_VAL(2, 12, 325) 10 #define PLL_FDIV_SH 12 11 #define PLL_BYPASS_FORCE 0x10 12 #define PLL_RESET 0x01 13 14 #define CPU_DIV 2 15 #define DDR_DIV3 2 16 #define DDR_DIV2 3 17 #define UART_DIV 40 18 #define DCI_DIV0 20 19 #define DCI_DIV1 5 20 #define ETH_DIV0 8 21 #define ETH_DIV1 1 22 #define QSPI_DIV 5 23 #define SDIO_DIV 10 24 #define PCAP_DIV 5 25 #define MDC_DIV 6 /* this value depends on CPU_1xCLK, see TRM GEM.net_cfg description */ 26 27 #define SLCR_BASE 0xF8000000 28 #define SLCR_LOCK 0x004 29 #define LOCK_KEY 0x767B 30 #define SLCR_UNLOCK 0x008 31 #define UNLOCK_KEY 0xDF0D 32 33 #define ARM_PLL_CTRL 0x100 34 #define DDR_PLL_CTRL 0x104 35 #define IO_PLL_CTRL 0x108 36 #define PLL_STATUS 0x10C 37 #define ARM_PLL_CFG 0x110 38 #define DDR_PLL_CFG 0x114 39 #define IO_PLL_CFG 0x118 40 #define ARM_CLK_CTRL 0x120 41 #define DDR_CLK_CTRL 0x124 42 #define DCI_CLK_CTRL 0x128 43 #define APER_CLK_CTRL 0x12C 44 #define GEM0_RCLK_CTRL 0x138 45 #define GEM1_RCLK_CTRL 0x13C 46 #define GEM0_CLK_CTRL 0x140 47 #define GEM1_CLK_CTRL 0x144 48 #define SMC_CLK_CTRL 0x148 49 #define LQSPI_CLK_CTRL 0x14C 50 #define SDIO_CLK_CTRL 0x150 51 #define UART_CLK_CTRL 0x154 52 #define SPI_CLK_CTRL 0x158 53 #define CAN_CLK_CTRL 0x15C 54 #define PCAP_CLK_CTRL 0x168 55 #define UART_RST_CTRL 0x228 56 #define A9_CPU_RST_CTRL 0x244 57 58 #define LQSPI_CLK_EN (1<<23) 59 #define GPIO_CLK_EN (1<<22) 60 #define UART0_CLK_EN (1<<20) 61 #define UART1_CLK_EN (1<<21) 62 #define I2C0_CLK_EN (1<<18) 63 #define SDIO1_CLK_EN (1<<11) 64 #define GEM0_CLK_EN (1<<6) 65 #define USB1_CLK_EN (1<<3) 66 #define USB0_CLK_EN (1<<2) 67 #define DMA_CLK_EN (1<<0) 68 69 #define MIO_PIN_0 0x00000700 70 #define MIO_MST_TRI0 0x80C 71 #define MIO_MST_TRI1 0x810 72 #define OCM_CFG 0x910 73 #define GPIOB_CTRL 0xB00 74 #define VREF_SW_EN (1<<11) 75 #define DDRIOB_ADDR0 0xB40 76 #define DDRIOB_DCI_CTRL 0xB70 77 #define DDRIOB_DCI_CTRL_MASK 0x1ffc3 78 #define DDRIOB_DCI_STATUS 0xB74 79 #define DCI_RESET 1 80 #define DCI_NREF (1<<11) 81 #define DCI_ENABLE 2 82 83 #define DDR_BASE 0xF8006000 84 #define DDRC_CTRL 0x0 85 #define DDR_MODE_STS 0x54 86 87 #define UART1_BASE 0xE0001000 88 #define UART_CTRL 0x0 89 #define UART_MODE 0x4 90 #define UART_BAUD 0x18 91 #define UART_STAT 0x2C 92 #define UART_DATA 0x30 93 #define UART_SAMP 0x34 94 95 #define QSPI_BASE 0xE000D000 96 #define QSPI_CFG 0x0 97 #define SPI_EN 0x4 98 #define QSPI_TX 0x1c 99 100 #define MP_BASE 0xF8F00000 101 #define FILTER_START 0x40 102 103 #define CpMMU 15 104 105 #define DSB WORD $0xf57ff04f 106 #define ISB WORD $0xf57ff06f 107 #define WFE WORD $0xe320f002 108