1This bootstrap is intended to load a Plan 9 kernel via bootp and tftp 2into a Xilinx Virtex 5 ML510 board. Most of its source is in ../vt4. 3The mkfile generates an elf file which is then fed into the Xilinx CAD 4tool to generate a bitstream for loading into the FPGA on the ML510. 5 6This bootstrap will almost certainly not work for you without some 7changes. In particular, the addresses of the I/O registers in 8physmem.h will have to be changed to match yours and you'll need to 9make sure that they are mapped if you have more than 512K of them. 10 11Because of pecularities of the PowerPC 440, there's a `micro 12bootstrap' in microboot.s that kicks everything off. The bootstrap 13runs with the MMU on, because it's always on on a 440. 14 15This bootstrap does not use dma but in principle it could, by 16replacing calls to fifocpy with calls to dmacpy. dma is one more 17thing that could go wrong, so we ended up using the cpu to copy words 18to and from ethernet fifos. 19 20This code runs in high memory (above 0xfffe0000) and its global data 21is thus in sram. 22