1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 #define KiB 1024u /* Kibi 0x0000000000000400 */ 5 #define MiB 1048576u /* Mebi 0x0000000000100000 */ 6 #define GiB 1073741824u /* Gibi 000000000040000000 */ 7 #define TiB 1099511627776ull /* Tebi 0x0000010000000000 */ 8 #define PiB 1125899906842624ull /* Pebi 0x0004000000000000 */ 9 #define EiB 1152921504606846976ull /* Exbi 0x1000000000000000 */ 10 11 #define HOWMANY(x, y) (((x)+((y)-1))/(y)) 12 #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y)) 13 #define ROUNDDN(x, y) (((x)/(y))*(y)) 14 #define MIN(a, b) ((a) < (b)? (a): (b)) 15 #define MAX(a, b) ((a) > (b)? (a): (b)) 16 17 /* 18 * Sizes 19 */ 20 #define BI2BY 8 /* bits per byte */ 21 #define BY2V 8 /* bytes per vlong */ 22 #define BY2SE 4 /* bytes per stack element */ 23 #define BY2WD 4 /* bytes per int */ 24 #define BY2PG 4096 /* bytes per page */ 25 #define PGSHIFT 12 /* log(BY2PG) */ 26 #define PGROUND(s) ROUNDUP(s, BY2PG) 27 #define UTROUND(t) ROUNDUP((t), 0x100000) 28 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */ 29 30 #define ICACHESIZE 32768 /* 0, 4, 8, 16, or 32 KB */ 31 #define ICACHEWAYSIZE (ICACHESIZE/64) /* 64-way set associative */ 32 #define ICACHELINELOG 5 /* 8 words (4 bytes) per line */ 33 #define ICACHELINESZ (1<<ICACHELINELOG) 34 35 #define DCACHESIZE 32768 /* 0, 4, 8, 16, or 32 KB */ 36 #define DCACHEWAYSIZE (DCACHESIZE/64) /* 64-way set associative */ 37 #define DCACHELINELOG 5 /* 8 words (4 bytes) per line */ 38 #define DCACHELINESZ (1<<DCACHELINELOG) 39 40 #define BLOCKALIGN DCACHELINESZ /* for ../port/allocb.c */ 41 42 #define MAXMACH 2 /* max # cpus system can run */ 43 #define MACHSIZE BY2PG 44 45 /* 46 * Time 47 */ 48 #define HZ 100 /* clock frequency */ 49 #define MHz 1000000 50 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 51 52 /* 53 * IBM bit field order 54 * used only to derive bit mask for interrupt vector numbers 55 */ 56 #define IBIT(n) (1UL<<(31-(n))) 57 58 /* 59 * Bit encodings for Machine State Register (MSR) 60 */ 61 #define MSR_AP 0x02000000 /* auxiliary processor available */ 62 #define MSR_APE 0x00080000 /* APU exception enable */ 63 #define MSR_WE 0x00040000 /* wait state enable */ 64 #define MSR_CE 0x00020000 /* critical interrupt enable */ 65 #define MSR_EE 0x00008000 /* enable external/decrementer interrupts */ 66 #define MSR_PR 0x00004000 /* =1, user mode */ 67 #define MSR_FP 0x00002000 /* floating-point available */ 68 #define MSR_ME 0x00001000 /* enable machine check exceptions */ 69 #define MSR_FE0 0x00000800 /* floating-point exception mode 0 */ 70 #define MSR_DWE 0x00000400 /* debug wait enable */ 71 #define MSR_DE 0x00000200 /* debug interrupts enable */ 72 #define MSR_FE1 0x00000100 /* floating-point exception mode 1 */ 73 #define MSR_IS 0x00000020 /* instruction address space */ 74 #define MSR_DS 0x00000010 /* data address space */ 75 76 /* state in user mode */ 77 #define UMSR (MSR_PR|MSR_CE|MSR_EE|MSR_DE) 78 79 /* 80 * Exception Syndrome Register (ESR) 81 */ 82 #define ESR_MCI 0x80000000 /* instruction machine check */ 83 #define ESR_PIL 0x08000000 /* program interrupt: illegal instruction */ 84 #define ESR_PPR 0x04000000 /* program interrupt: privileged */ 85 #define ESR_PTR 0x02000000 /* program interrupt: trap with successful compare */ 86 #define ESR_PEU 0x01000000 /* program interrupt: unimplemented APU/FPU operation */ 87 #define ESR_DST 0x00800000 /* data storage interrupt: store fault */ 88 #define ESR_DIZ 0x00400000 /* data/instruction storage interrupt: zone fault */ 89 #define ESR_PFP 0x00080000 /* program interrupt: FPU interrupt occurred */ 90 #define ESR_PAP 0x00040000 /* program interrupt: APU interrupt occurred */ 91 #define ESR_U0F 0x00008000 /* data storage interrupt: u0 fault */ 92 93 /* 94 * Interrupt vector offsets 95 */ 96 #define INT_CI 0x0100 /* Critical input interrupt */ 97 #define INT_MCHECK 0x0200 /* Machine check */ 98 #define INT_DSI 0x0300 /* Data storage interrupt */ 99 #define INT_ISI 0x0400 /* Instruction storage interrupt */ 100 #define INT_EI 0x0500 /* External interrupt */ 101 #define INT_ALIGN 0x0600 /* Alignment */ 102 #define INT_PROG 0x0700 /* Program */ 103 #define INT_FPU 0x0800 /* FPU unavailable */ 104 #define INT_DEC 0x0900 /* UNUSED on 405? */ 105 #define INT_SYSCALL 0x0C00 /* System call */ 106 #define INT_TRACE 0x0D00 /* UNUSED on 405? */ 107 #define INT_FPA 0x0E00 /* UNUSED on 405? */ 108 #define INT_APU 0x0F20 /* APU unavailable */ 109 #define INT_PIT 0x1000 /* PIT interrupt */ 110 #define INT_FIT 0x1010 /* FIT interrupt */ 111 #define INT_WDT 0x1020 /* Watchdog timer */ 112 #define INT_DMISS 0x1100 /* Data TLB miss */ 113 #define INT_IMISS 0x1200 /* Instruction TLB miss */ 114 #define INT_DEBUG 0x2000 /* Debug */ 115 116 /* 117 * Magic registers 118 */ 119 #define MACH 30 /* R30 is m-> */ 120 #define USER 29 /* R29 is up-> */ 121 122 /* 123 * Virtual MMU 124 */ 125 #define PTEMAPMEM (1024*1024) 126 #define PTEPERTAB (PTEMAPMEM/BY2PG) 127 #define SEGMAPSIZE 1984 128 #define SSEGMAPSIZE 16 129 #define PPN(x) ((x)&~(BY2PG-1)) 130 131 #define PTEVALID (1<<0) 132 #define PTEWRITE (1<<1) 133 #define PTERONLY (0<<1) 134 #define PTEUNCACHED (1<<2) 135 136 /* 137 * Physical MMU 138 */ 139 #define NTLB 64 /* number of entries */ 140 #define NTLBPID 256 /* number of hardware pids (0 = global) */ 141 142 /* TLBHI */ 143 #define TLBEPN(x) ((x) & ~0x3FF) 144 #define TLB1K (0<<4) 145 #define TLB4K (1<<4) 146 #define TLB16K (2<<4) 147 #define TLB64K (3<<4) 148 #define TLB256K (4<<4) 149 #define TLB1MB (5<<4) 150 /* 4Mbyte not implemented */ 151 #define TLB16MB (7<<4) 152 /* 32Mbyte not implemented */ 153 #define TLB256MB (9<<4) 154 #define TLBVALID (1<<9) 155 #define TLBTS (1<<8) /* Translation address space */ 156 157 /* TLBMID */ 158 #define TLBRPN(x) ((x) & ~0x3FF) 159 #define TLBERPN(uv) (((uv)>>32)&0xF) /* with full address as uvlong */ 160 161 /* TLBLO */ 162 #define TLBU0 (1<<15) /* user definable */ 163 #define TLBU1 (1<<14) /* user definable */ 164 #define TLBU2 (1<<13) /* user definable */ 165 #define TLBU3 (1<<12) /* user definable */ 166 #define TLBW (1<<11) /* write-through? */ 167 #define TLBI (1<<10) /* cache inhibit */ 168 #define TLBM (1<<9) /* memory coherent */ 169 #define TLBG (1<<8) /* guarded */ 170 #define TLBLE (1<<7) /* little endian mode */ 171 #define TLBUX (1<<5) /* user execute enable */ 172 #define TLBUW (1<<4) /* user writable */ 173 #define TLBUR (1<<3) /* user readable */ 174 #define TLBSX (1<<2) /* supervisor execute enable */ 175 #define TLBSW (1<<1) /* supervisor writable */ 176 #define TLBSR (1<<0) /* supervisor readable */ 177 178 #define TLBWR (TLBSW|TLBSR) 179 180 /* 181 * software TLB (for quick reload by [id]tlbmiss) 182 */ 183 #define STLBLOG 10 184 #define STLBSIZE (1<<STLBLOG) 185 186 /* 187 * Address spaces 188 */ 189 #define KSEG0 0x80000000 190 #define KSEG1 0xA0000000 /* uncached alias for KZERO */ 191 #define KSEGM 0xE0000000 /* mask to check segment */ 192 #define KZERO KSEG0 /* base of kernel address space */ 193 #define KTZERO (KZERO+0x4000) /* first address in kernel text */ 194 195 #define TSTKTOP KZERO /* top of temporary stack */ 196 #define TSTKSIZ 100 197 198 #define UZERO 0 /* base of user address space */ 199 #define UTZERO (UZERO+BY2PG) /* first address in user text */ 200 #define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */ 201 202 #define KSTACK 8192 /* Size of kernel stack */ 203 204 #define USTKSIZE (4*1024*1024) /* size of user stack */ 205 #define UREGSIZE ((8+40)*4) 206 207 #include "physmem.h" 208 209 #define getpgcolor(a) 0 /* ../port/page.c */ 210