1 /*
2 * Intel 82557 Fast Ethernet PCI Bus LAN Controller
3 * as found on the Intel EtherExpress PRO/100B. This chip is full
4 * of smarts, unfortunately they're not all in the right place.
5 * To do:
6 * the PCI scanning code could be made common to other adapters;
7 * auto-negotiation, full-duplex;
8 * optionally use memory-mapped registers;
9 * detach for PCI reset problems (also towards loadable drivers).
10 */
11 #include "u.h"
12 #include "../port/lib.h"
13 #include "mem.h"
14 #include "dat.h"
15 #include "fns.h"
16 #include "../port/error.h"
17
18 #include "../port/netif.h"
19
20 #include "etherif.h"
21 #include "io.h"
22
23 enum {
24 Nrfd = 64, /* receive frame area */
25 Ncb = 64, /* maximum control blocks queued */
26
27 NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */
28 };
29
30 enum { /* CSR */
31 Status = 0x00, /* byte or word (word includes Ack) */
32 Ack = 0x01, /* byte */
33 CommandR = 0x02, /* byte or word (word includes Interrupt) */
34 Interrupt = 0x03, /* byte */
35 General = 0x04, /* dword */
36 Port = 0x08, /* dword */
37 Fcr = 0x0C, /* Flash control register */
38 Ecr = 0x0E, /* EEPROM control register */
39 Mcr = 0x10, /* MDI control register */
40 Gstatus = 0x1D, /* General status register */
41 };
42
43 enum { /* Status */
44 RUidle = 0x0000,
45 RUsuspended = 0x0004,
46 RUnoresources = 0x0008,
47 RUready = 0x0010,
48 RUrbd = 0x0020, /* bit */
49 RUstatus = 0x003F, /* mask */
50
51 CUidle = 0x0000,
52 CUsuspended = 0x0040,
53 CUactive = 0x0080,
54 CUstatus = 0x00C0, /* mask */
55
56 StatSWI = 0x0400, /* SoftWare generated Interrupt */
57 StatMDI = 0x0800, /* MDI r/w done */
58 StatRNR = 0x1000, /* Receive unit Not Ready */
59 StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */
60 StatFR = 0x4000, /* Finished Receiving */
61 StatCX = 0x8000, /* Command eXecuted */
62 StatTNO = 0x8000, /* Transmit NOT OK */
63 };
64
65 enum { /* Command (byte) */
66 CUnop = 0x00,
67 CUstart = 0x10,
68 CUresume = 0x20,
69 LoadDCA = 0x40, /* Load Dump Counters Address */
70 DumpSC = 0x50, /* Dump Statistical Counters */
71 LoadCUB = 0x60, /* Load CU Base */
72 ResetSA = 0x70, /* Dump and Reset Statistical Counters */
73
74 RUstart = 0x01,
75 RUresume = 0x02,
76 RUabort = 0x04,
77 LoadHDS = 0x05, /* Load Header Data Size */
78 LoadRUB = 0x06, /* Load RU Base */
79 RBDresume = 0x07, /* Resume frame reception */
80 };
81
82 enum { /* Interrupt (byte) */
83 InterruptM = 0x01, /* interrupt Mask */
84 InterruptSI = 0x02, /* Software generated Interrupt */
85 };
86
87 enum { /* Ecr */
88 EEsk = 0x01, /* serial clock */
89 EEcs = 0x02, /* chip select */
90 EEdi = 0x04, /* serial data in */
91 EEdo = 0x08, /* serial data out */
92
93 EEstart = 0x04, /* start bit */
94 EEread = 0x02, /* read opcode */
95 };
96
97 enum { /* Mcr */
98 MDIread = 0x08000000, /* read opcode */
99 MDIwrite = 0x04000000, /* write opcode */
100 MDIready = 0x10000000, /* ready bit */
101 MDIie = 0x20000000, /* interrupt enable */
102 };
103
104 typedef struct Rfd {
105 int field;
106 ulong link;
107 ulong rbd;
108 ushort count;
109 ushort size;
110
111 uchar data[1700];
112 } Rfd;
113
114 enum { /* field */
115 RfdCollision = 0x00000001,
116 RfdIA = 0x00000002, /* IA match */
117 RfdRxerr = 0x00000010, /* PHY character error */
118 RfdType = 0x00000020, /* Type frame */
119 RfdRunt = 0x00000080,
120 RfdOverrun = 0x00000100,
121 RfdBuffer = 0x00000200,
122 RfdAlignment = 0x00000400,
123 RfdCRC = 0x00000800,
124
125 RfdOK = 0x00002000, /* frame received OK */
126 RfdC = 0x00008000, /* reception Complete */
127 RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */
128 RfdH = 0x00100000, /* Header RFD */
129
130 RfdI = 0x20000000, /* Interrupt after completion */
131 RfdS = 0x40000000, /* Suspend after completion */
132 RfdEL = 0x80000000, /* End of List */
133 };
134
135 enum { /* count */
136 RfdF = 0x4000,
137 RfdEOF = 0x8000,
138 };
139
140 typedef struct Cb Cb;
141 typedef struct Cb {
142 ushort status;
143 ushort command;
144 ulong link;
145 union {
146 uchar data[24]; /* CbIAS + CbConfigure */
147 struct {
148 ulong tbd;
149 ushort count;
150 uchar threshold;
151 uchar number;
152
153 ulong tba;
154 ushort tbasz;
155 ushort pad;
156 };
157 };
158
159 Block* bp;
160 Cb* next;
161 } Cb;
162
163 enum { /* action command */
164 CbU = 0x1000, /* transmit underrun */
165 CbOK = 0x2000, /* DMA completed OK */
166 CbC = 0x8000, /* execution Complete */
167
168 CbNOP = 0x0000,
169 CbIAS = 0x0001, /* Individual Address Setup */
170 CbConfigure = 0x0002,
171 CbMAS = 0x0003, /* Multicast Address Setup */
172 CbTransmit = 0x0004,
173 CbDump = 0x0006,
174 CbDiagnose = 0x0007,
175 CbCommand = 0x0007, /* mask */
176
177 CbSF = 0x0008, /* Flexible-mode CbTransmit */
178
179 CbI = 0x2000, /* Interrupt after completion */
180 CbS = 0x4000, /* Suspend after completion */
181 CbEL = 0x8000, /* End of List */
182 };
183
184 enum { /* CbTransmit count */
185 CbEOF = 0x8000,
186 };
187
188 typedef struct Ctlr Ctlr;
189 typedef struct Ctlr {
190 Lock slock; /* attach */
191 int state;
192
193 int port;
194 Pcidev* pcidev;
195 Ctlr* next;
196 int active;
197
198 int eepromsz; /* address size in bits */
199 ushort* eeprom;
200
201 Lock miilock;
202
203 int tick;
204
205 Lock rlock; /* registers */
206 int command; /* last command issued */
207
208 Block* rfdhead; /* receive side */
209 Block* rfdtail;
210 int nrfd;
211
212 Lock cblock; /* transmit side */
213 int action;
214 int nop;
215 uchar configdata[24];
216 int threshold;
217 int ncb;
218 Cb* cbr;
219 Cb* cbhead;
220 Cb* cbtail;
221 int cbq;
222 int cbqmax;
223 int cbqmaxhw;
224
225 Lock dlock; /* dump statistical counters */
226 ulong dump[17];
227 } Ctlr;
228
229 static Ctlr* ctlrhead;
230 static Ctlr* ctlrtail;
231
232 static uchar configdata[24] = {
233 0x16, /* byte count */
234 0x08, /* Rx/Tx FIFO limit */
235 0x00, /* adaptive IFS */
236 0x00,
237 0x00, /* Rx DMA maximum byte count */
238 // 0x80, /* Tx DMA maximum byte count */
239 0x00, /* Tx DMA maximum byte count */
240 0x32, /* !late SCB, CNA interrupts */
241 0x03, /* discard short Rx frames */
242 0x00, /* 503/MII */
243
244 0x00,
245 0x2E, /* normal operation, NSAI */
246 0x00, /* linear priority */
247 0x60, /* inter-frame spacing */
248 0x00,
249 0xF2,
250 0xC8, /* 503, promiscuous mode off */
251 0x00,
252 0x40,
253 0xF3, /* transmit padding enable */
254 0x80, /* full duplex pin enable */
255 0x3F, /* no Multi IA */
256 0x05, /* no Multi Cast ALL */
257 };
258
259 #define csr8r(c, r) (inb((c)->port+(r)))
260 #define csr16r(c, r) (ins((c)->port+(r)))
261 #define csr32r(c, r) (inl((c)->port+(r)))
262 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
263 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
264 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
265
266 static void
command(Ctlr * ctlr,int c,int v)267 command(Ctlr* ctlr, int c, int v)
268 {
269 int timeo;
270
271 ilock(&ctlr->rlock);
272
273 /*
274 * Only back-to-back CUresume can be done
275 * without waiting for any previous command to complete.
276 * This should be the common case.
277 * Unfortunately there's a chip errata where back-to-back
278 * CUresumes can be lost, the fix is to always wait.
279 if(c == CUresume && ctlr->command == CUresume){
280 csr8w(ctlr, CommandR, c);
281 iunlock(&ctlr->rlock);
282 return;
283 }
284 */
285
286 for(timeo = 0; timeo < 100; timeo++){
287 if(!csr8r(ctlr, CommandR))
288 break;
289 microdelay(1);
290 }
291 if(timeo >= 100){
292 ctlr->command = -1;
293 iunlock(&ctlr->rlock);
294 iprint("i82557: command %#ux %#ux timeout\n", c, v);
295 return;
296 }
297
298 switch(c){
299
300 case CUstart:
301 case LoadDCA:
302 case LoadCUB:
303 case RUstart:
304 case LoadHDS:
305 case LoadRUB:
306 csr32w(ctlr, General, v);
307 break;
308
309 /*
310 case CUnop:
311 case CUresume:
312 case DumpSC:
313 case ResetSA:
314 case RUresume:
315 case RUabort:
316 */
317 default:
318 break;
319 }
320 csr8w(ctlr, CommandR, c);
321 ctlr->command = c;
322
323 iunlock(&ctlr->rlock);
324 }
325
326 static Block*
rfdalloc(ulong link)327 rfdalloc(ulong link)
328 {
329 Block *bp;
330 Rfd *rfd;
331
332 if(bp = iallocb(sizeof(Rfd))){
333 rfd = (Rfd*)bp->rp;
334 rfd->field = 0;
335 rfd->link = link;
336 rfd->rbd = NullPointer;
337 rfd->count = 0;
338 rfd->size = sizeof(Etherpkt);
339 }
340
341 return bp;
342 }
343
344 static void
ethwatchdog(void * arg)345 ethwatchdog(void* arg)
346 {
347 Ether *ether;
348 Ctlr *ctlr;
349 static void txstart(Ether*);
350
351 ether = arg;
352 for(;;){
353 tsleep(&up->sleep, return0, 0, 4000);
354
355 /*
356 * Hmmm. This doesn't seem right. Currently
357 * the device can't be disabled but it may be in
358 * the future.
359 */
360 ctlr = ether->ctlr;
361 if(ctlr == nil || ctlr->state == 0){
362 print("%s: exiting\n", up->text);
363 pexit("disabled", 0);
364 }
365
366 ilock(&ctlr->cblock);
367 if(ctlr->tick++){
368 ctlr->action = CbMAS;
369 txstart(ether);
370 }
371 iunlock(&ctlr->cblock);
372 }
373 }
374
375 static void
attach(Ether * ether)376 attach(Ether* ether)
377 {
378 Ctlr *ctlr;
379 char name[KNAMELEN];
380
381 ctlr = ether->ctlr;
382 lock(&ctlr->slock);
383 if(ctlr->state == 0){
384 ilock(&ctlr->rlock);
385 csr8w(ctlr, Interrupt, 0);
386 iunlock(&ctlr->rlock);
387 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
388 ctlr->state = 1;
389
390 /*
391 * Start the watchdog timer for the receive lockup errata
392 * unless the EEPROM compatibility word indicates it may be
393 * omitted.
394 */
395 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
396 snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
397 kproc(name, ethwatchdog, ether);
398 }
399 }
400 unlock(&ctlr->slock);
401 }
402
403 static long
ifstat(Ether * ether,void * a,long n,ulong offset)404 ifstat(Ether* ether, void* a, long n, ulong offset)
405 {
406 char *alloc, *e, *p;
407 int i, phyaddr;
408 Ctlr *ctlr;
409 ulong dump[17];
410
411 ctlr = ether->ctlr;
412 lock(&ctlr->dlock);
413
414 /*
415 * Start the command then
416 * wait for completion status,
417 * should be 0xA005.
418 */
419 ctlr->dump[16] = 0;
420 command(ctlr, DumpSC, 0);
421 while(ctlr->dump[16] == 0)
422 ;
423
424 ether->oerrs = ctlr->dump[1]+ctlr->dump[2]+ctlr->dump[3];
425 ether->crcs = ctlr->dump[10];
426 ether->frames = ctlr->dump[11];
427 ether->buffs = ctlr->dump[12]+ctlr->dump[15];
428 ether->overflows = ctlr->dump[13];
429
430 if(n == 0){
431 unlock(&ctlr->dlock);
432 return 0;
433 }
434
435 memmove(dump, ctlr->dump, sizeof(dump));
436 unlock(&ctlr->dlock);
437
438 if((alloc = malloc(READSTR)) == nil)
439 error(Enomem);
440 p = alloc;
441 e = p + READSTR;
442
443 p = seprint(p, e, "transmit good frames: %lud\n", dump[0]);
444 p = seprint(p, e, "transmit maximum collisions errors: %lud\n", dump[1]);
445 p = seprint(p, e, "transmit late collisions errors: %lud\n", dump[2]);
446 p = seprint(p, e, "transmit underrun errors: %lud\n", dump[3]);
447 p = seprint(p, e, "transmit lost carrier sense: %lud\n", dump[4]);
448 p = seprint(p, e, "transmit deferred: %lud\n", dump[5]);
449 p = seprint(p, e, "transmit single collisions: %lud\n", dump[6]);
450 p = seprint(p, e, "transmit multiple collisions: %lud\n", dump[7]);
451 p = seprint(p, e, "transmit total collisions: %lud\n", dump[8]);
452 p = seprint(p, e, "receive good frames: %lud\n", dump[9]);
453 p = seprint(p, e, "receive CRC errors: %lud\n", dump[10]);
454 p = seprint(p, e, "receive alignment errors: %lud\n", dump[11]);
455 p = seprint(p, e, "receive resource errors: %lud\n", dump[12]);
456 p = seprint(p, e, "receive overrun errors: %lud\n", dump[13]);
457 p = seprint(p, e, "receive collision detect errors: %lud\n", dump[14]);
458 p = seprint(p, e, "receive short frame errors: %lud\n", dump[15]);
459 p = seprint(p, e, "nop: %d\n", ctlr->nop);
460 if(ctlr->cbqmax > ctlr->cbqmaxhw)
461 ctlr->cbqmaxhw = ctlr->cbqmax;
462 p = seprint(p, e, "cbqmax: %d\n", ctlr->cbqmax);
463 ctlr->cbqmax = 0;
464 p = seprint(p, e, "threshold: %d\n", ctlr->threshold);
465
466 p = seprint(p, e, "eeprom:");
467 for(i = 0; i < (1<<ctlr->eepromsz); i++){
468 if(i && ((i & 0x07) == 0))
469 p = seprint(p, e, "\n ");
470 p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);
471 }
472
473 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
474 phyaddr = ctlr->eeprom[6] & 0x00FF;
475 p = seprint(p, e, "\nphy %2d:", phyaddr);
476 for(i = 0; i < 6; i++){
477 static int miir(Ctlr*, int, int);
478
479 p = seprint(p, e, " %4.4ux", miir(ctlr, phyaddr, i));
480 }
481 }
482 seprint(p, e, "\n");
483
484 n = readstr(offset, a, n, alloc);
485 free(alloc);
486
487 return n;
488 }
489
490 static void
txstart(Ether * ether)491 txstart(Ether* ether)
492 {
493 Ctlr *ctlr;
494 Block *bp;
495 Cb *cb;
496
497 ctlr = ether->ctlr;
498 while(ctlr->cbq < (ctlr->ncb-1)){
499 cb = ctlr->cbhead->next;
500 if(ctlr->action == 0){
501 bp = qget(ether->oq);
502 if(bp == nil)
503 break;
504
505 cb->command = CbS|CbSF|CbTransmit;
506 cb->tbd = PADDR(&cb->tba);
507 cb->count = 0;
508 cb->threshold = ctlr->threshold;
509 cb->number = 1;
510 cb->tba = PADDR(bp->rp);
511 cb->bp = bp;
512 cb->tbasz = BLEN(bp);
513 }
514 else if(ctlr->action == CbConfigure){
515 cb->command = CbS|CbConfigure;
516 memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
517 ctlr->action = 0;
518 }
519 else if(ctlr->action == CbIAS){
520 cb->command = CbS|CbIAS;
521 memmove(cb->data, ether->ea, Eaddrlen);
522 ctlr->action = 0;
523 }
524 else if(ctlr->action == CbMAS){
525 cb->command = CbS|CbMAS;
526 memset(cb->data, 0, sizeof(cb->data));
527 ctlr->action = 0;
528 }
529 else{
530 print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
531 ctlr->action = 0;
532 break;
533 }
534 cb->status = 0;
535
536 coherence();
537 ctlr->cbhead->command &= ~CbS;
538 ctlr->cbhead = cb;
539 ctlr->cbq++;
540 }
541
542 /*
543 * Workaround for some broken HUB chips
544 * when connected at 10Mb/s half-duplex.
545 */
546 if(ctlr->nop){
547 command(ctlr, CUnop, 0);
548 microdelay(1);
549 }
550 command(ctlr, CUresume, 0);
551
552 if(ctlr->cbq > ctlr->cbqmax)
553 ctlr->cbqmax = ctlr->cbq;
554 }
555
556 static void
configure(Ether * ether,int promiscuous)557 configure(Ether* ether, int promiscuous)
558 {
559 Ctlr *ctlr;
560
561 ctlr = ether->ctlr;
562 ilock(&ctlr->cblock);
563 if(promiscuous){
564 ctlr->configdata[6] |= 0x80; /* Save Bad Frames */
565 //ctlr->configdata[6] &= ~0x40; /* !Discard Overrun Rx Frames */
566 ctlr->configdata[7] &= ~0x01; /* !Discard Short Rx Frames */
567 ctlr->configdata[15] |= 0x01; /* Promiscuous mode */
568 ctlr->configdata[18] &= ~0x01; /* (!Padding enable?), !stripping enable */
569 ctlr->configdata[21] |= 0x08; /* Multi Cast ALL */
570 }
571 else{
572 ctlr->configdata[6] &= ~0x80;
573 //ctlr->configdata[6] |= 0x40;
574 ctlr->configdata[7] |= 0x01;
575 ctlr->configdata[15] &= ~0x01;
576 ctlr->configdata[18] |= 0x01; /* 0x03? */
577 ctlr->configdata[21] &= ~0x08;
578 }
579 ctlr->action = CbConfigure;
580 txstart(ether);
581 iunlock(&ctlr->cblock);
582 }
583
584 static void
promiscuous(void * arg,int on)585 promiscuous(void* arg, int on)
586 {
587 configure(arg, on);
588 }
589
590 static void
multicast(void * ether,uchar * addr,int add)591 multicast(void* ether, uchar *addr, int add)
592 {
593 USED(addr);
594 /*
595 * TODO: if (add) add addr to list of mcast addrs in controller
596 * else remove addr from list of mcast addrs in controller
597 * enable multicast input (see CbMAS) instead of promiscuous mode.
598 */
599 if (add)
600 configure(ether, 1);
601 }
602
603 static void
transmit(Ether * ether)604 transmit(Ether* ether)
605 {
606 Ctlr *ctlr;
607
608 ctlr = ether->ctlr;
609 ilock(&ctlr->cblock);
610 txstart(ether);
611 iunlock(&ctlr->cblock);
612 }
613
614 static void
receive(Ether * ether)615 receive(Ether* ether)
616 {
617 Rfd *rfd;
618 Ctlr *ctlr;
619 int count;
620 Block *bp, *pbp, *xbp;
621
622 ctlr = ether->ctlr;
623 bp = ctlr->rfdhead;
624 for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
625 /*
626 * If it's an OK receive frame
627 * 1) save the count
628 * 2) if it's small, try to allocate a block and copy
629 * the data, then adjust the necessary fields for reuse;
630 * 3) if it's big, try to allocate a new Rfd and if
631 * successful
632 * adjust the received buffer pointers for the
633 * actual data received;
634 * initialise the replacement buffer to point to
635 * the next in the ring;
636 * initialise bp to point to the replacement;
637 * 4) if there's a good packet, pass it on for disposal.
638 */
639 if(rfd->field & RfdOK){
640 pbp = nil;
641 count = rfd->count & 0x3FFF;
642 if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
643 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
644 pbp->wp = pbp->rp + count;
645
646 rfd->count = 0;
647 rfd->field = 0;
648 }
649 else if(xbp = rfdalloc(rfd->link)){
650 bp->rp += offsetof(Rfd, data[0]);
651 bp->wp = bp->rp + count;
652
653 xbp->next = bp->next;
654 bp->next = 0;
655
656 pbp = bp;
657 bp = xbp;
658 }
659 if(pbp != nil)
660 etheriq(ether, pbp, 1);
661 }
662 else{
663 rfd->count = 0;
664 rfd->field = 0;
665 }
666
667 /*
668 * The ring tail pointer follows the head with with one
669 * unused buffer in between to defeat hardware prefetch;
670 * once the tail pointer has been bumped on to the next
671 * and the new tail has the Suspend bit set, it can be
672 * removed from the old tail buffer.
673 * As a replacement for the current head buffer may have
674 * been allocated above, ensure that the new tail points
675 * to it (next and link).
676 */
677 rfd = (Rfd*)ctlr->rfdtail->rp;
678 ctlr->rfdtail = ctlr->rfdtail->next;
679 ctlr->rfdtail->next = bp;
680 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
681 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
682 coherence();
683 rfd->field &= ~RfdS;
684
685 /*
686 * Finally done with the current (possibly replaced)
687 * head, move on to the next and maintain the sentinel
688 * between tail and head.
689 */
690 ctlr->rfdhead = bp->next;
691 bp = ctlr->rfdhead;
692 }
693 }
694
695 static void
interrupt(Ureg *,void * arg)696 interrupt(Ureg*, void* arg)
697 {
698 Cb* cb;
699 Ctlr *ctlr;
700 Ether *ether;
701 int status;
702
703 ether = arg;
704 ctlr = ether->ctlr;
705
706 for(;;){
707 ilock(&ctlr->rlock);
708 status = csr16r(ctlr, Status);
709 csr8w(ctlr, Ack, (status>>8) & 0xFF);
710 iunlock(&ctlr->rlock);
711
712 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
713 break;
714
715 /*
716 * If the watchdog timer for the receiver lockup errata is running,
717 * let it know the receiver is active.
718 */
719 if(status & (StatFR|StatRNR)){
720 ilock(&ctlr->cblock);
721 ctlr->tick = 0;
722 iunlock(&ctlr->cblock);
723 }
724
725 if(status & StatFR){
726 receive(ether);
727 status &= ~StatFR;
728 }
729
730 if(status & StatRNR){
731 command(ctlr, RUresume, 0);
732 status &= ~StatRNR;
733 }
734
735 if(status & StatCNA){
736 ilock(&ctlr->cblock);
737
738 cb = ctlr->cbtail;
739 while(ctlr->cbq){
740 if(!(cb->status & CbC))
741 break;
742 if(cb->bp){
743 freeb(cb->bp);
744 cb->bp = nil;
745 }
746 if((cb->status & CbU) && ctlr->threshold < 0xE0)
747 ctlr->threshold++;
748
749 ctlr->cbq--;
750 cb = cb->next;
751 }
752 ctlr->cbtail = cb;
753
754 txstart(ether);
755 iunlock(&ctlr->cblock);
756
757 status &= ~StatCNA;
758 }
759
760 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
761 panic("#l%d: status %#ux\n", ether->ctlrno, status);
762 }
763 }
764
765 static void
ctlrinit(Ctlr * ctlr)766 ctlrinit(Ctlr* ctlr)
767 {
768 int i;
769 Block *bp;
770 Rfd *rfd;
771 ulong link;
772
773 /*
774 * Create the Receive Frame Area (RFA) as a ring of allocated
775 * buffers.
776 * A sentinel buffer is maintained between the last buffer in
777 * the ring (marked with RfdS) and the head buffer to defeat the
778 * hardware prefetch of the next RFD and allow dynamic buffer
779 * allocation.
780 */
781 link = NullPointer;
782 for(i = 0; i < Nrfd; i++){
783 bp = rfdalloc(link);
784 if(ctlr->rfdhead == nil)
785 ctlr->rfdtail = bp;
786 bp->next = ctlr->rfdhead;
787 ctlr->rfdhead = bp;
788 link = PADDR(bp->rp);
789 }
790 ctlr->rfdtail->next = ctlr->rfdhead;
791 rfd = (Rfd*)ctlr->rfdtail->rp;
792 rfd->link = PADDR(ctlr->rfdhead->rp);
793 rfd->field |= RfdS;
794 ctlr->rfdhead = ctlr->rfdhead->next;
795
796 /*
797 * Create a ring of control blocks for the
798 * transmit side.
799 */
800 ilock(&ctlr->cblock);
801 ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
802 if(ctlr->cbr == nil) {
803 iunlock(&ctlr->cblock);
804 error(Enomem);
805 }
806 for(i = 0; i < ctlr->ncb; i++){
807 ctlr->cbr[i].status = CbC|CbOK;
808 ctlr->cbr[i].command = CbS|CbNOP;
809 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
810 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
811 }
812 ctlr->cbhead = ctlr->cbr;
813 ctlr->cbtail = ctlr->cbr;
814 ctlr->cbq = 0;
815
816 memmove(ctlr->configdata, configdata, sizeof(configdata));
817 ctlr->threshold = 80;
818 ctlr->tick = 0;
819
820 iunlock(&ctlr->cblock);
821 }
822
823 static int
miir(Ctlr * ctlr,int phyadd,int regadd)824 miir(Ctlr* ctlr, int phyadd, int regadd)
825 {
826 int mcr, timo;
827
828 lock(&ctlr->miilock);
829 csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
830 mcr = 0;
831 for(timo = 64; timo; timo--){
832 mcr = csr32r(ctlr, Mcr);
833 if(mcr & MDIready)
834 break;
835 microdelay(1);
836 }
837 unlock(&ctlr->miilock);
838
839 if(mcr & MDIready)
840 return mcr & 0xFFFF;
841
842 return -1;
843 }
844
845 static int
miiw(Ctlr * ctlr,int phyadd,int regadd,int data)846 miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
847 {
848 int mcr, timo;
849
850 lock(&ctlr->miilock);
851 csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
852 mcr = 0;
853 for(timo = 64; timo; timo--){
854 mcr = csr32r(ctlr, Mcr);
855 if(mcr & MDIready)
856 break;
857 microdelay(1);
858 }
859 unlock(&ctlr->miilock);
860
861 if(mcr & MDIready)
862 return 0;
863
864 return -1;
865 }
866
867 static int
hy93c46r(Ctlr * ctlr,int r)868 hy93c46r(Ctlr* ctlr, int r)
869 {
870 int data, i, op, size;
871
872 /*
873 * Hyundai HY93C46 or equivalent serial EEPROM.
874 * This sequence for reading a 16-bit register 'r'
875 * in the EEPROM is taken straight from Section
876 * 3.3.4.2 of the Intel 82557 User's Guide.
877 */
878 reread:
879 csr16w(ctlr, Ecr, EEcs);
880 op = EEstart|EEread;
881 for(i = 2; i >= 0; i--){
882 data = (((op>>i) & 0x01)<<2)|EEcs;
883 csr16w(ctlr, Ecr, data);
884 csr16w(ctlr, Ecr, data|EEsk);
885 microdelay(1);
886 csr16w(ctlr, Ecr, data);
887 microdelay(1);
888 }
889
890 /*
891 * First time through must work out the EEPROM size.
892 */
893 if((size = ctlr->eepromsz) == 0)
894 size = 8;
895
896 for(size = size-1; size >= 0; size--){
897 data = (((r>>size) & 0x01)<<2)|EEcs;
898 csr16w(ctlr, Ecr, data);
899 csr16w(ctlr, Ecr, data|EEsk);
900 delay(1);
901 csr16w(ctlr, Ecr, data);
902 microdelay(1);
903 if(!(csr16r(ctlr, Ecr) & EEdo))
904 break;
905 }
906
907 data = 0;
908 for(i = 15; i >= 0; i--){
909 csr16w(ctlr, Ecr, EEcs|EEsk);
910 microdelay(1);
911 if(csr16r(ctlr, Ecr) & EEdo)
912 data |= (1<<i);
913 csr16w(ctlr, Ecr, EEcs);
914 microdelay(1);
915 }
916
917 csr16w(ctlr, Ecr, 0);
918
919 if(ctlr->eepromsz == 0){
920 ctlr->eepromsz = 8-size;
921 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
922 if(ctlr->eeprom == nil)
923 error(Enomem);
924 goto reread;
925 }
926
927 return data;
928 }
929
930 static void
i82557pci(void)931 i82557pci(void)
932 {
933 Pcidev *p;
934 Ctlr *ctlr;
935 int i, nop, port;
936
937 p = nil;
938 nop = 0;
939 while(p = pcimatch(p, 0x8086, 0)){
940 switch(p->did){
941 default:
942 continue;
943 case 0x1031: /* Intel 82562EM */
944 case 0x103B: /* Intel 82562EM */
945 case 0x103C: /* Intel 82562EM */
946 case 0x1050: /* Intel 82562EZ */
947 case 0x1039: /* Intel 82801BD PRO/100 VE */
948 case 0x103A: /* Intel 82562 PRO/100 VE */
949 case 0x103D: /* Intel 82562 PRO/100 VE */
950 case 0x1064: /* Intel 82562 PRO/100 VE */
951 case 0x2449: /* Intel 82562ET */
952 case 0x27DC: /* Intel 82801G PRO/100 VE */
953 nop = 1;
954 /*FALLTHROUGH*/
955 case 0x1209: /* Intel 82559ER */
956 case 0x1229: /* Intel 8255[789] */
957 case 0x1030: /* Intel 82559 InBusiness 10/100 */
958 break;
959 }
960
961 if(pcigetpms(p) > 0){
962 pcisetpms(p, 0);
963
964 for(i = 0; i < 6; i++)
965 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
966 pcicfgw8(p, PciINTL, p->intl);
967 pcicfgw8(p, PciLTR, p->ltr);
968 pcicfgw8(p, PciCLS, p->cls);
969 pcicfgw16(p, PciPCR, p->pcr);
970 }
971
972 /*
973 * bar[0] is the memory-mapped register address (4KB),
974 * bar[1] is the I/O port register address (32 bytes) and
975 * bar[2] is for the flash ROM (1MB).
976 */
977 port = p->mem[1].bar & ~0x01;
978 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
979 print("i82557: port %#ux in use\n", port);
980 continue;
981 }
982
983 ctlr = malloc(sizeof(Ctlr));
984 if(ctlr == nil)
985 error(Enomem);
986 ctlr->port = port;
987 ctlr->pcidev = p;
988 ctlr->nop = nop;
989
990 if(ctlrhead != nil)
991 ctlrtail->next = ctlr;
992 else
993 ctlrhead = ctlr;
994 ctlrtail = ctlr;
995
996 pcisetbme(p);
997 }
998 }
999
1000 static char* mediatable[9] = {
1001 "10BASE-T", /* TP */
1002 "10BASE-2", /* BNC */
1003 "10BASE-5", /* AUI */
1004 "100BASE-TX",
1005 "10BASE-TFD",
1006 "100BASE-TXFD",
1007 "100BASE-T4",
1008 "100BASE-FX",
1009 "100BASE-FXFD",
1010 };
1011
1012 static int
scanphy(Ctlr * ctlr)1013 scanphy(Ctlr* ctlr)
1014 {
1015 int i, oui, x;
1016
1017 for(i = 0; i < 32; i++){
1018 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
1019 continue;
1020 oui <<= 6;
1021 x = miir(ctlr, i, 3);
1022 oui |= x>>10;
1023 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
1024
1025 ctlr->eeprom[6] = i;
1026 if(oui == 0xAA00)
1027 ctlr->eeprom[6] |= 0x07<<8;
1028 else if(oui == 0x80017){
1029 if(x & 0x01)
1030 ctlr->eeprom[6] |= 0x0A<<8;
1031 else
1032 ctlr->eeprom[6] |= 0x04<<8;
1033 }
1034 return i;
1035 }
1036 return -1;
1037 }
1038
1039 static void
shutdown(Ether * ether)1040 shutdown(Ether* ether)
1041 {
1042 Ctlr *ctlr = ether->ctlr;
1043
1044 csr32w(ctlr, Port, 0);
1045 delay(1);
1046 csr8w(ctlr, Interrupt, InterruptM);
1047 }
1048
1049
1050 static int
reset(Ether * ether)1051 reset(Ether* ether)
1052 {
1053 int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
1054 unsigned short sum;
1055 uchar ea[Eaddrlen];
1056 Ctlr *ctlr;
1057
1058 if(ctlrhead == nil)
1059 i82557pci();
1060
1061 /*
1062 * Any adapter matches if no ether->port is supplied,
1063 * otherwise the ports must match.
1064 */
1065 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1066 if(ctlr->active)
1067 continue;
1068 if(ether->port == 0 || ether->port == ctlr->port){
1069 ctlr->active = 1;
1070 break;
1071 }
1072 }
1073 if(ctlr == nil)
1074 return -1;
1075
1076 /*
1077 * Initialise the Ctlr structure.
1078 * Perform a software reset after which should ensure busmastering
1079 * is still enabled. The EtherExpress PRO/100B appears to leave
1080 * the PCI configuration alone (see the 'To do' list above) so punt
1081 * for now.
1082 * Load the RUB and CUB registers for linear addressing (0).
1083 */
1084 ether->ctlr = ctlr;
1085 ether->port = ctlr->port;
1086 ether->irq = ctlr->pcidev->intl;
1087 ether->tbdf = ctlr->pcidev->tbdf;
1088
1089 ilock(&ctlr->rlock);
1090 csr32w(ctlr, Port, 0);
1091 delay(1);
1092 csr8w(ctlr, Interrupt, InterruptM);
1093 iunlock(&ctlr->rlock);
1094
1095 command(ctlr, LoadRUB, 0);
1096 command(ctlr, LoadCUB, 0);
1097 command(ctlr, LoadDCA, PADDR(ctlr->dump));
1098
1099 /*
1100 * Initialise the receive frame, transmit ring and configuration areas.
1101 */
1102 ctlr->ncb = Ncb;
1103 ctlrinit(ctlr);
1104
1105 /*
1106 * Read the EEPROM.
1107 * Do a dummy read first to get the size
1108 * and allocate ctlr->eeprom.
1109 */
1110 hy93c46r(ctlr, 0);
1111 sum = 0;
1112 for(i = 0; i < (1<<ctlr->eepromsz); i++){
1113 x = hy93c46r(ctlr, i);
1114 ctlr->eeprom[i] = x;
1115 sum += x;
1116 }
1117 if(sum != 0xBABA)
1118 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
1119
1120 /*
1121 * Eeprom[6] indicates whether there is a PHY and whether
1122 * it's not 10Mb-only, in which case use the given PHY address
1123 * to set any PHY specific options and determine the speed.
1124 * Unfortunately, sometimes the EEPROM is blank except for
1125 * the ether address and checksum; in this case look at the
1126 * controller type and if it's am 82558 or 82559 it has an
1127 * embedded PHY so scan for that.
1128 * If no PHY, assume 82503 (serial) operation.
1129 */
1130 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
1131 phyaddr = ctlr->eeprom[6] & 0x00FF;
1132 else
1133 switch(ctlr->pcidev->rid){
1134 case 0x01: /* 82557 A-step */
1135 case 0x02: /* 82557 B-step */
1136 case 0x03: /* 82557 C-step */
1137 default:
1138 phyaddr = -1;
1139 break;
1140 case 0x04: /* 82558 A-step */
1141 case 0x05: /* 82558 B-step */
1142 case 0x06: /* 82559 A-step */
1143 case 0x07: /* 82559 B-step */
1144 case 0x08: /* 82559 C-step */
1145 case 0x09: /* 82559ER A-step */
1146 phyaddr = scanphy(ctlr);
1147 break;
1148 }
1149 if(phyaddr >= 0){
1150 /*
1151 * Resolve the highest common ability of the two
1152 * link partners. In descending order:
1153 * 0x0100 100BASE-TX Full Duplex
1154 * 0x0200 100BASE-T4
1155 * 0x0080 100BASE-TX
1156 * 0x0040 10BASE-T Full Duplex
1157 * 0x0020 10BASE-T
1158 */
1159 anar = miir(ctlr, phyaddr, 0x04);
1160 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1161 anar &= anlpar;
1162 bmcr = 0;
1163 if(anar & 0x380)
1164 bmcr = 0x2000;
1165 if(anar & 0x0140)
1166 bmcr |= 0x0100;
1167
1168 switch((ctlr->eeprom[6]>>8) & 0x001F){
1169
1170 case 0x04: /* DP83840 */
1171 case 0x0A: /* DP83840A */
1172 /*
1173 * The DP83840[A] requires some tweaking for
1174 * reliable operation.
1175 * The manual says bit 10 should be unconditionally
1176 * set although it supposedly only affects full-duplex
1177 * operation (an & 0x0140).
1178 */
1179 x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
1180 x |= 0x0420;
1181 for(i = 0; i < ether->nopt; i++){
1182 if(cistrcmp(ether->opt[i], "congestioncontrol"))
1183 continue;
1184 x |= 0x0100;
1185 break;
1186 }
1187 miiw(ctlr, phyaddr, 0x17, x);
1188
1189 /*
1190 * If the link partner can't autonegotiate, determine
1191 * the speed from elsewhere.
1192 */
1193 if(anlpar == 0){
1194 miir(ctlr, phyaddr, 0x01);
1195 bmsr = miir(ctlr, phyaddr, 0x01);
1196 x = miir(ctlr, phyaddr, 0x19);
1197 if((bmsr & 0x0004) && !(x & 0x0040))
1198 bmcr = 0x2000;
1199 }
1200 break;
1201
1202 case 0x07: /* Intel 82555 */
1203 /*
1204 * Auto-negotiation may fail if the other end is
1205 * a DP83840A and the cable is short.
1206 */
1207 miir(ctlr, phyaddr, 0x01);
1208 bmsr = miir(ctlr, phyaddr, 0x01);
1209 if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
1210 miiw(ctlr, phyaddr, 0x1A, 0x2010);
1211 x = miir(ctlr, phyaddr, 0);
1212 miiw(ctlr, phyaddr, 0, 0x0200|x);
1213 for(i = 0; i < 3000; i++){
1214 delay(1);
1215 if(miir(ctlr, phyaddr, 0x01) & 0x0020)
1216 break;
1217 }
1218 miiw(ctlr, phyaddr, 0x1A, 0x2000);
1219
1220 anar = miir(ctlr, phyaddr, 0x04);
1221 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1222 anar &= anlpar;
1223 bmcr = 0;
1224 if(anar & 0x380)
1225 bmcr = 0x2000;
1226 if(anar & 0x0140)
1227 bmcr |= 0x0100;
1228 }
1229 break;
1230 }
1231
1232 /*
1233 * Force speed and duplex if no auto-negotiation.
1234 */
1235 if(anlpar == 0){
1236 medium = -1;
1237 for(i = 0; i < ether->nopt; i++){
1238 for(k = 0; k < nelem(mediatable); k++){
1239 if(cistrcmp(mediatable[k], ether->opt[i]))
1240 continue;
1241 medium = k;
1242 break;
1243 }
1244
1245 switch(medium){
1246 default:
1247 break;
1248
1249 case 0x00: /* 10BASE-T */
1250 case 0x01: /* 10BASE-2 */
1251 case 0x02: /* 10BASE-5 */
1252 bmcr &= ~(0x2000|0x0100);
1253 ctlr->configdata[19] &= ~0x40;
1254 break;
1255
1256 case 0x03: /* 100BASE-TX */
1257 case 0x06: /* 100BASE-T4 */
1258 case 0x07: /* 100BASE-FX */
1259 ctlr->configdata[19] &= ~0x40;
1260 bmcr |= 0x2000;
1261 break;
1262
1263 case 0x04: /* 10BASE-TFD */
1264 bmcr = (bmcr & ~0x2000)|0x0100;
1265 ctlr->configdata[19] |= 0x40;
1266 break;
1267
1268 case 0x05: /* 100BASE-TXFD */
1269 case 0x08: /* 100BASE-FXFD */
1270 bmcr |= 0x2000|0x0100;
1271 ctlr->configdata[19] |= 0x40;
1272 break;
1273 }
1274 }
1275 if(medium != -1)
1276 miiw(ctlr, phyaddr, 0x00, bmcr);
1277 }
1278
1279 if(bmcr & 0x2000)
1280 ether->mbps = 100;
1281
1282 ctlr->configdata[8] = 1;
1283 ctlr->configdata[15] &= ~0x80;
1284 }
1285 else{
1286 ctlr->configdata[8] = 0;
1287 ctlr->configdata[15] |= 0x80;
1288 }
1289
1290 /*
1291 * Workaround for some broken HUB chips when connected at 10Mb/s
1292 * half-duplex.
1293 * This is a band-aid, but as there's no dynamic auto-negotiation
1294 * code at the moment, only deactivate the workaround code in txstart
1295 * if the link is 100Mb/s.
1296 */
1297 if(ether->mbps != 10)
1298 ctlr->nop = 0;
1299
1300 /*
1301 * Load the chip configuration and start it off.
1302 */
1303 if(ether->oq == 0)
1304 ether->oq = qopen(64*1024, Qmsg, 0, 0);
1305 configure(ether, 0);
1306 command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
1307
1308 /*
1309 * Check if the adapter's station address is to be overridden.
1310 * If not, read it from the EEPROM and set in ether->ea prior to loading
1311 * the station address with the Individual Address Setup command.
1312 */
1313 memset(ea, 0, Eaddrlen);
1314 if(memcmp(ea, ether->ea, Eaddrlen) == 0){
1315 for(i = 0; i < Eaddrlen/2; i++){
1316 x = ctlr->eeprom[i];
1317 ether->ea[2*i] = x;
1318 ether->ea[2*i+1] = x>>8;
1319 }
1320 }
1321
1322 ilock(&ctlr->cblock);
1323 ctlr->action = CbIAS;
1324 txstart(ether);
1325 iunlock(&ctlr->cblock);
1326
1327 /*
1328 * Linkage to the generic ethernet driver.
1329 */
1330 ether->attach = attach;
1331 ether->transmit = transmit;
1332 ether->interrupt = interrupt;
1333 ether->ifstat = ifstat;
1334 ether->shutdown = shutdown;
1335
1336 ether->promiscuous = promiscuous;
1337 ether->multicast = multicast;
1338 ether->arg = ether;
1339
1340 return 0;
1341 }
1342
1343 void
ether82557link(void)1344 ether82557link(void)
1345 {
1346 addethercard("i82557", reset);
1347 }
1348