1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 #define KiB 1024u /* Kibi 0x0000000000000400 */ 5 #define MiB 1048576u /* Mebi 0x0000000000100000 */ 6 #define GiB 1073741824u /* Gibi 000000000040000000 */ 7 #define TiB 1099511627776ull /* Tebi 0x0000010000000000 */ 8 #define PiB 1125899906842624ull /* Pebi 0x0004000000000000 */ 9 #define EiB 1152921504606846976ull /* Exbi 0x1000000000000000 */ 10 11 /* 12 * Sizes 13 */ 14 #define BI2BY 8 /* bits per byte */ 15 #define BI2WD 32 /* bits per word */ 16 #define BY2WD 4 /* bytes per word */ 17 #define BY2V 8 /* bytes per vlong */ 18 #define BY2SE 4 /* bytes per stack element */ 19 #define BY2PG 4096 /* bytes per page */ 20 #define PGSHIFT 12 /* log(BY2PG) */ 21 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */ 22 23 #define BY2PTE 8 /* bytes per pte entry */ 24 #define BY2PTEG 64 /* bytes per pte group */ 25 26 #define ICACHESIZE 16384 /* 0, 4, 8, 16, or 32 KB */ 27 #define ICACHEWAYSIZE (ICACHESIZE/2) /* 2-way set associative */ 28 #define ICACHELINELOG 5 /* 8 words (4 bytes) per line */ 29 #define ICACHELINESZ (1<<ICACHELINELOG) 30 31 #define DCACHESIZE 16384 /* 0, 4, 8, 16, or 32 KB */ 32 #define DCACHEWAYSIZE (DCACHESIZE/2) /* 2-way set associative */ 33 #define DCACHELINELOG 5 /* 8 words (4 bytes) per line */ 34 #define DCACHELINESZ (1<<DCACHELINELOG) 35 36 #define BLOCKALIGN DCACHELINESZ /* for ../port/allocb.c */ 37 38 #define MAXMACH 2 /* max # cpus system can run */ 39 #define MACHSIZE BY2PG 40 41 /* 42 * Time 43 */ 44 #define HZ 100 /* clock frequency */ 45 #define MHz 1000000 46 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 47 48 /* 49 * IBM bit field order 50 * used only to derive bit mask for interrupt vector numbers 51 */ 52 #define IBIT(n) (1UL<<(31-(n))) 53 54 /* 55 * Bit encodings for Machine State Register (MSR) 56 */ 57 #define MSR_AP 0x02000000 /* auxiliary processor available */ 58 #define MSR_APE 0x00080000 /* APU exception enable */ 59 #define MSR_WE 0x00040000 /* wait state enable */ 60 #define MSR_CE 0x00020000 /* critical interrupt enable */ 61 #define MSR_EE 0x00008000 /* enable external/decrementer interrupts */ 62 #define MSR_PR 0x00004000 /* =1, user mode */ 63 #define MSR_FP 0x00002000 /* floating-point available */ 64 #define MSR_ME 0x00001000 /* enable machine check exceptions */ 65 #define MSR_FE0 0x00000800 /* floating-point exception mode 0 */ 66 #define MSR_DWE 0x00000400 /* debug wait enable */ 67 #define MSR_DE 0x00000200 /* debug interrupts enable */ 68 #define MSR_FE1 0x00000100 /* floating-point exception mode 1 */ 69 #define MSR_IR 0x00000020 /* enable instruction address translation */ 70 #define MSR_DR 0x00000010 /* enable data address translation */ 71 72 /* state in user mode */ 73 #define UMSR (MSR_PR|MSR_DE|MSR_CE|MSR_EE|MSR_IR|MSR_DR) 74 75 /* 76 * Exception Syndrome Register (ESR) 77 */ 78 #define ESR_MCI 0x80000000 /* instruction machine check */ 79 #define ESR_PIL 0x08000000 /* program interrupt: illegal instruction */ 80 #define ESR_PPR 0x04000000 /* program interrupt: privileged */ 81 #define ESR_PTR 0x02000000 /* program interrupt: trap with successful compare */ 82 #define ESR_PEU 0x01000000 /* program interrupt: unimplemented APU/FPU operation */ 83 #define ESR_DST 0x00800000 /* data storage interrupt: store fault */ 84 #define ESR_DIZ 0x00400000 /* data/instruction storage interrupt: zone fault */ 85 #define ESR_PFP 0x00080000 /* program interrupt: FPU interrupt occurred */ 86 #define ESR_PAP 0x00040000 /* program interrupt: APU interrupt occurred */ 87 #define ESR_U0F 0x00008000 /* data storage interrupt: u0 fault */ 88 89 /* 90 * Interrupt vector offsets 91 */ 92 #define INT_RESET 0x0100 /* Critical input interrupt */ 93 #define INT_MCHECK 0x0200 /* Machine check */ 94 #define INT_DSI 0x0300 /* Data storage interrupt */ 95 #define INT_ISI 0x0400 /* Instruction storage interrupt */ 96 #define INT_EI 0x0500 /* External interrupt */ 97 #define INT_ALIGN 0x0600 /* Alignment */ 98 #define INT_PROG 0x0700 /* Program */ 99 #define INT_FPU 0x0800 /* FPU unavailable */ 100 #define INT_DEC 0x0900 /* UNUSED on 405? */ 101 #define INT_SYSCALL 0x0C00 /* System call */ 102 #define INT_TRACE 0x0D00 /* UNUSED on 405? */ 103 #define INT_FPA 0x0E00 /* UNUSED on 405? */ 104 #define INT_APU 0x0F20 /* APU unavailable */ 105 #define INT_PIT 0x1000 /* PIT interrupt */ 106 #define INT_FIT 0x1010 /* FIT interrupt */ 107 #define INT_WDT 0x1020 /* Watchdog timer */ 108 #define INT_DMISS 0x1100 /* Data TLB miss */ 109 #define INT_IMISS 0x1200 /* Instruction TLB miss */ 110 #define INT_DEBUG 0x2000 /* Debug */ 111 112 /* 113 * Magic registers 114 */ 115 #define MACH 30 /* R30 is m-> */ 116 #define USER 29 /* R29 is up-> */ 117 118 /* 119 * Virtual MMU 120 */ 121 #define PTEMAPMEM (1024*1024) 122 #define PTEPERTAB (PTEMAPMEM/BY2PG) 123 #define SEGMAPSIZE 1984 124 #define SSEGMAPSIZE 16 125 #define PPN(x) ((x)&~(BY2PG-1)) 126 127 #define PTEVALID (1<<0) 128 #define PTEWRITE (1<<1) 129 #define PTERONLY (0<<1) 130 #define PTEUNCACHED (1<<2) 131 132 /* 133 * Physical MMU 134 */ 135 #define NTLB 64 /* number of entries */ 136 #define NTLBPID 256 /* number of hardware pids (0 = global) */ 137 138 /* TLBHI */ 139 #define TLBEPN(x) ((x) & ~0x3FF) 140 #define TLB1K (0<<7) 141 #define TLB4K (1<<7) 142 #define TLB16K (2<<7) 143 #define TLB64K (3<<7) 144 #define TLB256K (4<<7) 145 #define TLB1MB (5<<7) 146 #define TLB4MB (6<<7) 147 #define TLB16MB (7<<7) 148 #define TLBVALID (1<<6) 149 #define TLBLE (1<<5) /* little-endian */ 150 #define TLBU0 (1<<4) /* user-defined attribute */ 151 152 /* TLBLO */ 153 #define TLBRPN(x) ((x) & ~0x3FF) 154 #define TLBEX (1<<9) /* execute enable */ 155 #define TLBWR (1<<8) /* write enable */ 156 #define TLBZONE(x) ((x)<<4) 157 #define TLBW (1<<3) /* write-through */ 158 #define TLBI (1<<2) /* cache inhibit */ 159 #define TLBM (1<<1) /* memory coherent */ 160 /* 161 * WARNING: applying TLBG to instruction pages will cause ISI traps 162 * on Xilinx 405s, despite the words of the Xilinx manual (p. 155). 163 */ 164 #define TLBG (1<<0) /* guarded */ 165 166 /* 167 * software TLB (for quick reload by [id]tlbmiss) 168 */ 169 #define STLBLOG 10 170 #define STLBSIZE (1<<STLBLOG) 171 172 /* 173 * Address spaces 174 */ 175 #define KSEG0 0x80000000 176 #define KSEG1 0xA0000000 /* uncached alias for KZERO */ 177 #define KSEGM 0xE0000000 /* mask to check segment */ 178 #define KZERO KSEG0 /* base of kernel address space */ 179 #define KTZERO (KZERO+0x100000) /* first address in kernel text */ 180 181 #define TSTKTOP KZERO /* top of temporary stack */ 182 #define TSTKSIZ 256 /* pages in new stack; limits exec args */ 183 184 #define UZERO 0 /* base of user address space */ 185 #define UTZERO (UZERO+0x100000) /* first address in user text */ 186 #define UTROUND(t) ROUNDUP((t), 0x100000) 187 #define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */ 188 189 #define CONFADDR (KZERO+0x2200) /* info passed from boot loader */ 190 #define REBOOTADDR (CONFADDR+BOOTLINELEN+BOOTARGSLEN) /* reboot code - physical address */ 191 192 /* 193 * Where configuration info is left for the loaded programme. 194 * This will turn into a structure as more is done by the boot loader 195 * (e.g. why parse the .ini file twice?). 196 * On the power pc, we can use 0x2000+ε through 0x4000. 197 */ 198 #define BOOTLINE ((char*)CONFADDR) 199 #define BOOTLINELEN 64 200 #define BOOTARGS ((char*)(CONFADDR+BOOTLINELEN)) 201 #define BOOTARGSLEN 1024 202 203 #define KSTACK 8192 /* Size of kernel stack (not proc 0's in Mach) */ 204 205 #define OCMZERO 0x40000000 /* on-chip memory (virtual and physical--see 405EP p 5-1) */ 206 #define USTKSIZE (4*1024*1024) /* size of user stack */ 207 #define UREGSIZE ((8+40)*4) 208 209 #include "physmem.h" 210 211 #define getpgcolor(a) 0 /* ../port/page.c */ 212