1 /*
2 * Intel 8254[340]NN Gigabit Ethernet PCI Controllers
3 * as found on the Intel PRO/1000 series of adapters:
4 * 82543GC Intel PRO/1000 T
5 * 82544EI Intel PRO/1000 XT
6 * 82540EM Intel PRO/1000 MT
7 * 82541[GP]I
8 * 82547GI
9 * 82546GB
10 * 82546EB
11 * To Do:
12 * finish autonegotiation code;
13 * integrate fiber stuff back in (this ONLY handles
14 * the CAT5 cards at the moment);
15 * add tuning control via ctl file;
16 * this driver is little-endian specific.
17 */
18 #include "u.h"
19 #include "../port/lib.h"
20 #include "mem.h"
21 #include "dat.h"
22 #include "fns.h"
23 #include "io.h"
24 #include "../port/error.h"
25 #include "../port/netif.h"
26
27 #include "etherif.h"
28 #include "ethermii.h"
29
30 enum {
31 i82542 = (0x1000<<16)|0x8086,
32 i82543gc = (0x1004<<16)|0x8086,
33 i82544ei = (0x1008<<16)|0x8086,
34 i82544eif = (0x1009<<16)|0x8086,
35 i82544gc = (0x100d<<16)|0x8086,
36 i82540em = (0x100E<<16)|0x8086,
37 i82540eplp = (0x101E<<16)|0x8086,
38 i82545em = (0x100F<<16)|0x8086,
39 i82545gmc = (0x1026<<16)|0x8086,
40 i82547ei = (0x1019<<16)|0x8086,
41 i82547gi = (0x1075<<16)|0x8086,
42 i82541ei = (0x1013<<16)|0x8086,
43 i82541gi = (0x1076<<16)|0x8086,
44 i82541gi2 = (0x1077<<16)|0x8086,
45 i82541pi = (0x107c<<16)|0x8086,
46 i82546gb = (0x1079<<16)|0x8086,
47 i82546eb = (0x1010<<16)|0x8086,
48 };
49
50 enum {
51 Ctrl = 0x00000000, /* Device Control */
52 Ctrldup = 0x00000004, /* Device Control Duplicate */
53 Status = 0x00000008, /* Device Status */
54 Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
55 Ctrlext = 0x00000018, /* Extended Device Control */
56 Mdic = 0x00000020, /* MDI Control */
57 Fcal = 0x00000028, /* Flow Control Address Low */
58 Fcah = 0x0000002C, /* Flow Control Address High */
59 Fct = 0x00000030, /* Flow Control Type */
60 Icr = 0x000000C0, /* Interrupt Cause Read */
61 Ics = 0x000000C8, /* Interrupt Cause Set */
62 Ims = 0x000000D0, /* Interrupt Mask Set/Read */
63 Imc = 0x000000D8, /* Interrupt mask Clear */
64 Rctl = 0x00000100, /* Receive Control */
65 Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
66 Txcw = 0x00000178, /* Transmit Configuration Word */
67 Rxcw = 0x00000180, /* Receive Configuration Word */
68 /* on the oldest cards (8254[23]), the Mta register is at 0x200 */
69 Tctl = 0x00000400, /* Transmit Control */
70 Tipg = 0x00000410, /* Transmit IPG */
71 Tbt = 0x00000448, /* Transmit Burst Timer */
72 Ait = 0x00000458, /* Adaptive IFS Throttle */
73 Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
74 Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
75 Rdfh = 0x00002410, /* Receive data fifo head */
76 Rdft = 0x00002418, /* Receive data fifo tail */
77 Rdfhs = 0x00002420, /* Receive data fifo head saved */
78 Rdfts = 0x00002428, /* Receive data fifo tail saved */
79 Rdfpc = 0x00002430, /* Receive data fifo packet count */
80 Rdbal = 0x00002800, /* Rd Base Address Low */
81 Rdbah = 0x00002804, /* Rd Base Address High */
82 Rdlen = 0x00002808, /* Receive Descriptor Length */
83 Rdh = 0x00002810, /* Receive Descriptor Head */
84 Rdt = 0x00002818, /* Receive Descriptor Tail */
85 Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
86 Rxdctl = 0x00002828, /* Receive Descriptor Control */
87 Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
88 Txdmac = 0x00003000, /* Transfer DMA Control */
89 Ett = 0x00003008, /* Early Transmit Control */
90 Tdfh = 0x00003410, /* Transmit data fifo head */
91 Tdft = 0x00003418, /* Transmit data fifo tail */
92 Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */
93 Tdfts = 0x00003428, /* Transmit data fifo tail saved */
94 Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */
95 Tdbal = 0x00003800, /* Td Base Address Low */
96 Tdbah = 0x00003804, /* Td Base Address High */
97 Tdlen = 0x00003808, /* Transmit Descriptor Length */
98 Tdh = 0x00003810, /* Transmit Descriptor Head */
99 Tdt = 0x00003818, /* Transmit Descriptor Tail */
100 Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
101 Txdctl = 0x00003828, /* Transmit Descriptor Control */
102 Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
103
104 Statistics = 0x00004000, /* Start of Statistics Area */
105 Gorcl = 0x88/4, /* Good Octets Received Count */
106 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
107 Torl = 0xC0/4, /* Total Octets Received */
108 Totl = 0xC8/4, /* Total Octets Transmitted */
109 Nstatistics = 64,
110
111 Rxcsum = 0x00005000, /* Receive Checksum Control */
112 Mta = 0x00005200, /* Multicast Table Array */
113 Ral = 0x00005400, /* Receive Address Low */
114 Rah = 0x00005404, /* Receive Address High */
115 Manc = 0x00005820, /* Management Control */
116 };
117
118 enum { /* Ctrl */
119 Bem = 0x00000002, /* Big Endian Mode */
120 Prior = 0x00000004, /* Priority on the PCI bus */
121 Lrst = 0x00000008, /* Link Reset */
122 Asde = 0x00000020, /* Auto-Speed Detection Enable */
123 Slu = 0x00000040, /* Set Link Up */
124 Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
125 SspeedMASK = 0x00000300, /* Speed Selection */
126 SspeedSHIFT = 8,
127 Sspeed10 = 0x00000000, /* 10Mb/s */
128 Sspeed100 = 0x00000100, /* 100Mb/s */
129 Sspeed1000 = 0x00000200, /* 1000Mb/s */
130 Frcspd = 0x00000800, /* Force Speed */
131 Frcdplx = 0x00001000, /* Force Duplex */
132 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
133 SwdpinsloSHIFT = 18,
134 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
135 SwdpioloSHIFT = 22,
136 Devrst = 0x04000000, /* Device Reset */
137 Rfce = 0x08000000, /* Receive Flow Control Enable */
138 Tfce = 0x10000000, /* Transmit Flow Control Enable */
139 Vme = 0x40000000, /* VLAN Mode Enable */
140 };
141
142 /*
143 * can't find Tckok nor Rbcok in any Intel docs,
144 * but even 82543gc docs define Lanid.
145 */
146 enum { /* Status */
147 Lu = 0x00000002, /* Link Up */
148 Lanid = 0x0000000C, /* mask for Lan ID. (function id) */
149 // Tckok = 0x00000004, /* Transmit clock is running */
150 // Rbcok = 0x00000008, /* Receive clock is running */
151 Txoff = 0x00000010, /* Transmission Paused */
152 Tbimode = 0x00000020, /* TBI Mode Indication */
153 LspeedMASK = 0x000000C0, /* Link Speed Setting */
154 LspeedSHIFT = 6,
155 Lspeed10 = 0x00000000, /* 10Mb/s */
156 Lspeed100 = 0x00000040, /* 100Mb/s */
157 Lspeed1000 = 0x00000080, /* 1000Mb/s */
158 Mtxckok = 0x00000400, /* MTX clock is running */
159 Pci66 = 0x00000800, /* PCI Bus speed indication */
160 Bus64 = 0x00001000, /* PCI Bus width indication */
161 Pcixmode = 0x00002000, /* PCI-X mode */
162 PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */
163 PcixspeedSHIFT = 14,
164 Pcix66 = 0x00000000, /* 50-66MHz */
165 Pcix100 = 0x00004000, /* 66-100MHz */
166 Pcix133 = 0x00008000, /* 100-133MHz */
167 };
168
169 enum { /* Ctrl and Status */
170 Fd = 0x00000001, /* Full-Duplex */
171 AsdvMASK = 0x00000300,
172 AsdvSHIFT = 8,
173 Asdv10 = 0x00000000, /* 10Mb/s */
174 Asdv100 = 0x00000100, /* 100Mb/s */
175 Asdv1000 = 0x00000200, /* 1000Mb/s */
176 };
177
178 enum { /* Eecd */
179 Sk = 0x00000001, /* Clock input to the EEPROM */
180 Cs = 0x00000002, /* Chip Select */
181 Di = 0x00000004, /* Data Input to the EEPROM */
182 Do = 0x00000008, /* Data Output from the EEPROM */
183 Areq = 0x00000040, /* EEPROM Access Request */
184 Agnt = 0x00000080, /* EEPROM Access Grant */
185 Eepresent = 0x00000100, /* EEPROM Present */
186 Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
187 Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
188 Spi = 0x00002000, /* EEPROM is SPI not Microwire */
189 };
190
191 enum { /* Ctrlext */
192 Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
193 SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
194 SwdpinshiSHIFT = 4,
195 SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
196 SwdpiohiSHIFT = 8,
197 Asdchk = 0x00001000, /* ASD Check */
198 Eerst = 0x00002000, /* EEPROM Reset */
199 Ips = 0x00004000, /* Invert Power State */
200 Spdbyps = 0x00008000, /* Speed Select Bypass */
201 };
202
203 enum { /* EEPROM content offsets */
204 Ea = 0x00, /* Ethernet Address */
205 Cf = 0x03, /* Compatibility Field */
206 Pba = 0x08, /* Printed Board Assembly number */
207 Icw1 = 0x0A, /* Initialization Control Word 1 */
208 Sid = 0x0B, /* Subsystem ID */
209 Svid = 0x0C, /* Subsystem Vendor ID */
210 Did = 0x0D, /* Device ID */
211 Vid = 0x0E, /* Vendor ID */
212 Icw2 = 0x0F, /* Initialization Control Word 2 */
213 };
214
215 enum { /* Mdic */
216 MDIdMASK = 0x0000FFFF, /* Data */
217 MDIdSHIFT = 0,
218 MDIrMASK = 0x001F0000, /* PHY Register Address */
219 MDIrSHIFT = 16,
220 MDIpMASK = 0x03E00000, /* PHY Address */
221 MDIpSHIFT = 21,
222 MDIwop = 0x04000000, /* Write Operation */
223 MDIrop = 0x08000000, /* Read Operation */
224 MDIready = 0x10000000, /* End of Transaction */
225 MDIie = 0x20000000, /* Interrupt Enable */
226 MDIe = 0x40000000, /* Error */
227 };
228
229 enum { /* Icr, Ics, Ims, Imc */
230 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
231 Txqe = 0x00000002, /* Transmit Queue Empty */
232 Lsc = 0x00000004, /* Link Status Change */
233 Rxseq = 0x00000008, /* Receive Sequence Error */
234 Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */
235 Rxo = 0x00000040, /* Receiver Overrun */
236 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
237 Mdac = 0x00000200, /* MDIO Access Completed */
238 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
239 Gpi0 = 0x00000800, /* General Purpose Interrupts */
240 Gpi1 = 0x00001000,
241 Gpi2 = 0x00002000,
242 Gpi3 = 0x00004000,
243 };
244
245 /*
246 * The Mdic register isn't implemented on the 82543GC,
247 * the software defined pins are used instead.
248 * These definitions work for the Intel PRO/1000 T Server Adapter.
249 * The direction pin bits are read from the EEPROM.
250 */
251 enum {
252 Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
253 Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
254 Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
255 Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
256 Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
257 Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
258 };
259
260 enum { /* Txcw */
261 TxcwFd = 0x00000020, /* Full Duplex */
262 TxcwHd = 0x00000040, /* Half Duplex */
263 TxcwPauseMASK = 0x00000180, /* Pause */
264 TxcwPauseSHIFT = 7,
265 TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
266 TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
267 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
268 TxcwRfiSHIFT = 12,
269 TxcwNpr = 0x00008000, /* Next Page Request */
270 TxcwConfig = 0x40000000, /* Transmit COnfig Control */
271 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
272 };
273
274 enum { /* Rxcw */
275 Rxword = 0x0000FFFF, /* Data from auto-negotiation process */
276 Rxnocarrier = 0x04000000, /* Carrier Sense indication */
277 Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */
278 Rxchange = 0x10000000, /* Change to the Rxword indication */
279 Rxconfig = 0x20000000, /* /C/ order set reception indication */
280 Rxsync = 0x40000000, /* Lost bit synchronization indication */
281 Anc = 0x80000000, /* Auto Negotiation Complete */
282 };
283
284 enum { /* Rctl */
285 Rrst = 0x00000001, /* Receiver Software Reset */
286 Ren = 0x00000002, /* Receiver Enable */
287 Sbp = 0x00000004, /* Store Bad Packets */
288 Upe = 0x00000008, /* Unicast Promiscuous Enable */
289 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
290 Lpe = 0x00000020, /* Long Packet Reception Enable */
291 LbmMASK = 0x000000C0, /* Loopback Mode */
292 LbmOFF = 0x00000000, /* No Loopback */
293 LbmTBI = 0x00000040, /* TBI Loopback */
294 LbmMII = 0x00000080, /* GMII/MII Loopback */
295 LbmXCVR = 0x000000C0, /* Transceiver Loopback */
296 RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */
297 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
298 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
299 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
300 MoMASK = 0x00003000, /* Multicast Offset */
301 Mo47b36 = 0x00000000, /* bits [47:36] of received address */
302 Mo46b35 = 0x00001000, /* bits [46:35] of received address */
303 Mo45b34 = 0x00002000, /* bits [45:34] of received address */
304 Mo43b32 = 0x00003000, /* bits [43:32] of received address */
305 Bam = 0x00008000, /* Broadcast Accept Mode */
306 BsizeMASK = 0x00030000, /* Receive Buffer Size */
307 Bsize2048 = 0x00000000, /* Bsex = 0 */
308 Bsize1024 = 0x00010000, /* Bsex = 0 */
309 Bsize512 = 0x00020000, /* Bsex = 0 */
310 Bsize256 = 0x00030000, /* Bsex = 0 */
311 Bsize16384 = 0x00010000, /* Bsex = 1 */
312 Vfe = 0x00040000, /* VLAN Filter Enable */
313 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
314 Cfi = 0x00100000, /* Canonical Form Indicator value */
315 Dpf = 0x00400000, /* Discard Pause Frames */
316 Pmcf = 0x00800000, /* Pass MAC Control Frames */
317 Bsex = 0x02000000, /* Buffer Size Extension */
318 Secrc = 0x04000000, /* Strip CRC from incoming packet */
319 };
320
321 enum { /* Tctl */
322 Trst = 0x00000001, /* Transmitter Software Reset */
323 Ten = 0x00000002, /* Transmit Enable */
324 Psp = 0x00000008, /* Pad Short Packets */
325 CtMASK = 0x00000FF0, /* Collision Threshold */
326 CtSHIFT = 4,
327 ColdMASK = 0x003FF000, /* Collision Distance */
328 ColdSHIFT = 12,
329 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
330 Pbe = 0x00800000, /* Packet Burst Enable */
331 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
332 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
333 };
334
335 enum { /* [RT]xdctl */
336 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
337 PthreshSHIFT = 0,
338 HthreshMASK = 0x00003F00, /* Host Threshold */
339 HthreshSHIFT = 8,
340 WthreshMASK = 0x003F0000, /* Writeback Threshold */
341 WthreshSHIFT = 16,
342 Gran = 0x01000000, /* Granularity */
343 LthreshMASK = 0xFE000000, /* Low Threshold */
344 LthreshSHIFT = 25,
345 };
346
347 enum { /* Rxcsum */
348 PcssMASK = 0x000000FF, /* Packet Checksum Start */
349 PcssSHIFT = 0,
350 Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
351 Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
352 };
353
354 enum { /* Manc */
355 Arpen = 0x00002000, /* Enable ARP Request Filtering */
356 };
357
358 enum { /* Receive Delay Timer Ring */
359 DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */
360 DelaySHIFT = 0,
361 Fpd = 0x80000000, /* Flush partial Descriptor Block */
362 };
363
364 typedef struct Rd { /* Receive Descriptor */
365 uint addr[2];
366 ushort length;
367 ushort checksum;
368 uchar status;
369 uchar errors;
370 ushort special;
371 } Rd;
372
373 enum { /* Rd status */
374 Rdd = 0x01, /* Descriptor Done */
375 Reop = 0x02, /* End of Packet */
376 Ixsm = 0x04, /* Ignore Checksum Indication */
377 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
378 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
379 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
380 Pif = 0x80, /* Passed in-exact filter */
381 };
382
383 enum { /* Rd errors */
384 Ce = 0x01, /* CRC Error or Alignment Error */
385 Se = 0x02, /* Symbol Error */
386 Seq = 0x04, /* Sequence Error */
387 Cxe = 0x10, /* Carrier Extension Error */
388 Tcpe = 0x20, /* TCP/UDP Checksum Error */
389 Ipe = 0x40, /* IP Checksum Error */
390 Rxe = 0x80, /* RX Data Error */
391 };
392
393 typedef struct Td Td;
394 struct Td { /* Transmit Descriptor */
395 union {
396 uint addr[2]; /* Data */
397 struct { /* Context */
398 uchar ipcss;
399 uchar ipcso;
400 ushort ipcse;
401 uchar tucss;
402 uchar tucso;
403 ushort tucse;
404 };
405 };
406 uint control;
407 uint status;
408 };
409
410 enum { /* Td control */
411 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
412 LenSHIFT = 0,
413 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
414 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
415 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
416 Teop = 0x01000000, /* End of Packet (DD) */
417 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
418 Ifcs = 0x02000000, /* Insert FCS (DD) */
419 Tse = 0x04000000, /* TCP Segmentation Enable */
420 Rs = 0x08000000, /* Report Status */
421 Rps = 0x10000000, /* Report Status Sent */
422 Dext = 0x20000000, /* Descriptor Extension */
423 Vle = 0x40000000, /* VLAN Packet Enable */
424 Ide = 0x80000000, /* Interrupt Delay Enable */
425 };
426
427 enum { /* Td status */
428 Tdd = 0x00000001, /* Descriptor Done */
429 Ec = 0x00000002, /* Excess Collisions */
430 Lc = 0x00000004, /* Late Collision */
431 Tu = 0x00000008, /* Transmit Underrun */
432 Iixsm = 0x00000100, /* Insert IP Checksum */
433 Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */
434 HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */
435 HdrlenSHIFT = 8,
436 VlanMASK = 0x0FFF0000, /* VLAN Identifier */
437 VlanSHIFT = 16,
438 Tcfi = 0x10000000, /* Canonical Form Indicator */
439 PriMASK = 0xE0000000, /* User Priority */
440 PriSHIFT = 29,
441 MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */
442 MssSHIFT = 16,
443 };
444
445 enum {
446 Rbsz = 2048,
447 /*
448 * these were 256, 1024 & 64, but 52, 253 & 9 are usually ample;
449 * however cpu servers and terminals can need more receive buffers
450 * due to bursts of traffic.
451 */
452 Nrd = 128, /* multiple of 8 */
453 Nrb = 1024, /* private receive buffers per Ctlr */
454 Ntd = 32, /* multiple of 8 */
455 };
456
457 typedef struct Ctlr Ctlr;
458 struct Ctlr {
459 int port;
460 Pcidev* pcidev;
461 Ctlr* next;
462 Ether* edev;
463 int active;
464 int started;
465 int id;
466 int cls;
467 ushort eeprom[0x40];
468
469 QLock alock; /* attach */
470 void* alloc; /* receive/transmit descriptors */
471 int nrd;
472 int ntd;
473 int nrb; /* # bufs this Ctlr has in the pool */
474
475 int* nic;
476 Lock imlock;
477 int im; /* interrupt mask */
478
479 Mii* mii;
480 Rendez lrendez;
481 int lim;
482
483 int link;
484
485 Watermark wmrb;
486 Watermark wmrd;
487 Watermark wmtd;
488
489 QLock slock;
490 uint statistics[Nstatistics];
491 uint lsleep;
492 uint lintr;
493 uint rsleep;
494 uint rintr;
495 uint txdw;
496 uint tintr;
497 uint ixsm;
498 uint ipcs;
499 uint tcpcs;
500
501 uchar ra[Eaddrlen]; /* receive address */
502 ulong mta[128]; /* multicast table array */
503
504 Rendez rrendez;
505 int rim;
506 int rdfree; /* rx descriptors awaiting packets */
507 Rd* rdba; /* receive descriptor base address */
508 Block** rb; /* receive buffers */
509 int rdh; /* receive descriptor head */
510 int rdt; /* receive descriptor tail */
511 int rdtr; /* receive delay timer ring value */
512
513 Lock tlock;
514 int tdfree;
515 Td* tdba; /* transmit descriptor base address */
516 Block** tb; /* transmit buffers */
517 int tdh; /* transmit descriptor head */
518 int tdt; /* transmit descriptor tail */
519
520 int txcw;
521 int fcrtl;
522 int fcrth;
523 };
524
525 #define csr32r(c, r) (*((c)->nic+((r)/4)))
526 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
527
528 static Ctlr* igbectlrhead;
529 static Ctlr* igbectlrtail;
530
531 static Lock igberblock; /* free receive Blocks */
532 static Block* igberbpool; /* receive Blocks for all igbe controllers */
533 static int nrbfull; /* # of rcv Blocks with data awaiting processing */
534
535 static char* statistics[Nstatistics] = {
536 "CRC Error",
537 "Alignment Error",
538 "Symbol Error",
539 "RX Error",
540 "Missed Packets",
541 "Single Collision",
542 "Excessive Collisions",
543 "Multiple Collision",
544 "Late Collisions",
545 nil,
546 "Collision",
547 "Transmit Underrun",
548 "Defer",
549 "Transmit - No CRS",
550 "Sequence Error",
551 "Carrier Extension Error",
552 "Receive Error Length",
553 nil,
554 "XON Received",
555 "XON Transmitted",
556 "XOFF Received",
557 "XOFF Transmitted",
558 "FC Received Unsupported",
559 "Packets Received (64 Bytes)",
560 "Packets Received (65-127 Bytes)",
561 "Packets Received (128-255 Bytes)",
562 "Packets Received (256-511 Bytes)",
563 "Packets Received (512-1023 Bytes)",
564 "Packets Received (1024-1522 Bytes)",
565 "Good Packets Received",
566 "Broadcast Packets Received",
567 "Multicast Packets Received",
568 "Good Packets Transmitted",
569 nil,
570 "Good Octets Received",
571 nil,
572 "Good Octets Transmitted",
573 nil,
574 nil,
575 nil,
576 "Receive No Buffers",
577 "Receive Undersize",
578 "Receive Fragment",
579 "Receive Oversize",
580 "Receive Jabber",
581 nil,
582 nil,
583 nil,
584 "Total Octets Received",
585 nil,
586 "Total Octets Transmitted",
587 nil,
588 "Total Packets Received",
589 "Total Packets Transmitted",
590 "Packets Transmitted (64 Bytes)",
591 "Packets Transmitted (65-127 Bytes)",
592 "Packets Transmitted (128-255 Bytes)",
593 "Packets Transmitted (256-511 Bytes)",
594 "Packets Transmitted (512-1023 Bytes)",
595 "Packets Transmitted (1024-1522 Bytes)",
596 "Multicast Packets Transmitted",
597 "Broadcast Packets Transmitted",
598 "TCP Segmentation Context Transmitted",
599 "TCP Segmentation Context Fail",
600 };
601
602 static long
igbeifstat(Ether * edev,void * a,long n,ulong offset)603 igbeifstat(Ether* edev, void* a, long n, ulong offset)
604 {
605 Ctlr *ctlr;
606 char *p, *s, *e;
607 int i, l, r;
608 uvlong tuvl, ruvl;
609
610 ctlr = edev->ctlr;
611 qlock(&ctlr->slock);
612 p = malloc(READSTR);
613 if(p == nil) {
614 qunlock(&ctlr->slock);
615 error(Enomem);
616 }
617 l = 0;
618 for(i = 0; i < Nstatistics; i++){
619 r = csr32r(ctlr, Statistics+i*4);
620 if((s = statistics[i]) == nil)
621 continue;
622 switch(i){
623 case Gorcl:
624 case Gotcl:
625 case Torl:
626 case Totl:
627 ruvl = r;
628 ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
629 tuvl = ruvl;
630 tuvl += ctlr->statistics[i];
631 tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
632 if(tuvl == 0)
633 continue;
634 ctlr->statistics[i] = tuvl;
635 ctlr->statistics[i+1] = tuvl>>32;
636 l += snprint(p+l, READSTR-l, "%s: %llud %llud\n",
637 s, tuvl, ruvl);
638 i++;
639 break;
640
641 default:
642 ctlr->statistics[i] += r;
643 if(ctlr->statistics[i] == 0)
644 continue;
645 l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
646 s, ctlr->statistics[i], r);
647 break;
648 }
649 }
650
651 l += snprint(p+l, READSTR-l, "lintr: %ud %ud\n",
652 ctlr->lintr, ctlr->lsleep);
653 l += snprint(p+l, READSTR-l, "rintr: %ud %ud\n",
654 ctlr->rintr, ctlr->rsleep);
655 l += snprint(p+l, READSTR-l, "tintr: %ud %ud\n",
656 ctlr->tintr, ctlr->txdw);
657 l += snprint(p+l, READSTR-l, "ixcs: %ud %ud %ud\n",
658 ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
659 l += snprint(p+l, READSTR-l, "rdtr: %ud\n", ctlr->rdtr);
660 l += snprint(p+l, READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext));
661
662 l += snprint(p+l, READSTR-l, "eeprom:");
663 for(i = 0; i < 0x40; i++){
664 if(i && ((i & 0x07) == 0))
665 l += snprint(p+l, READSTR-l, "\n ");
666 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
667 }
668 l += snprint(p+l, READSTR-l, "\n");
669
670 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
671 l += snprint(p+l, READSTR-l, "phy: ");
672 for(i = 0; i < NMiiPhyr; i++){
673 if(i && ((i & 0x07) == 0))
674 l += snprint(p+l, READSTR-l, "\n ");
675 r = miimir(ctlr->mii, i);
676 l += snprint(p+l, READSTR-l, " %4.4uX", r);
677 }
678 snprint(p+l, READSTR-l, "\n");
679 }
680 e = p + READSTR;
681 s = p + l + 1;
682 s = seprintmark(s, e, &ctlr->wmrb);
683 s = seprintmark(s, e, &ctlr->wmrd);
684 s = seprintmark(s, e, &ctlr->wmtd);
685 USED(s);
686
687 n = readstr(offset, a, n, p);
688 free(p);
689 qunlock(&ctlr->slock);
690
691 return n;
692 }
693
694 enum {
695 CMrdtr,
696 };
697
698 static Cmdtab igbectlmsg[] = {
699 CMrdtr, "rdtr", 2,
700 };
701
702 static long
igbectl(Ether * edev,void * buf,long n)703 igbectl(Ether* edev, void* buf, long n)
704 {
705 int v;
706 char *p;
707 Ctlr *ctlr;
708 Cmdbuf *cb;
709 Cmdtab *ct;
710
711 if((ctlr = edev->ctlr) == nil)
712 error(Enonexist);
713
714 cb = parsecmd(buf, n);
715 if(waserror()){
716 free(cb);
717 nexterror();
718 }
719
720 ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg));
721 switch(ct->index){
722 case CMrdtr:
723 v = strtol(cb->f[1], &p, 0);
724 if(v < 0 || p == cb->f[1] || v > 0xFFFF)
725 error(Ebadarg);
726 ctlr->rdtr = v;
727 csr32w(ctlr, Rdtr, Fpd|v);
728 break;
729 }
730 free(cb);
731 poperror();
732
733 return n;
734 }
735
736 static void
igbepromiscuous(void * arg,int on)737 igbepromiscuous(void* arg, int on)
738 {
739 int rctl;
740 Ctlr *ctlr;
741 Ether *edev;
742
743 edev = arg;
744 ctlr = edev->ctlr;
745
746 rctl = csr32r(ctlr, Rctl);
747 rctl &= ~MoMASK;
748 rctl |= Mo47b36;
749 if(on)
750 rctl |= Upe|Mpe;
751 else
752 rctl &= ~(Upe|Mpe);
753 csr32w(ctlr, Rctl, rctl|Mpe); /* temporarily keep Mpe on */
754 }
755
756 static void
igbemulticast(void * arg,uchar * addr,int add)757 igbemulticast(void* arg, uchar* addr, int add)
758 {
759 int bit, x;
760 Ctlr *ctlr;
761 Ether *edev;
762
763 edev = arg;
764 ctlr = edev->ctlr;
765
766 x = addr[5]>>1;
767 bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
768 /*
769 * multiple ether addresses can hash to the same filter bit,
770 * so it's never safe to clear a filter bit.
771 * if we want to clear filter bits, we need to keep track of
772 * all the multicast addresses in use, clear all the filter bits,
773 * then set the ones corresponding to in-use addresses.
774 */
775 if(add)
776 ctlr->mta[x] |= 1<<bit;
777 // else
778 // ctlr->mta[x] &= ~(1<<bit);
779
780 csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
781 }
782
783 static Block*
igberballoc(void)784 igberballoc(void)
785 {
786 Block *bp;
787
788 ilock(&igberblock);
789 if((bp = igberbpool) != nil){
790 igberbpool = bp->next;
791 bp->next = nil;
792 ainc(&bp->ref); /* prevent bp from being freed */
793 }
794 iunlock(&igberblock);
795
796 return bp;
797 }
798
799 static void
igberbfree(Block * bp)800 igberbfree(Block* bp)
801 {
802 bp->rp = bp->lim - Rbsz;
803 bp->wp = bp->rp;
804 bp->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
805
806 ilock(&igberblock);
807 bp->next = igberbpool;
808 igberbpool = bp;
809 nrbfull--;
810 iunlock(&igberblock);
811 }
812
813 static void
igbeim(Ctlr * ctlr,int im)814 igbeim(Ctlr* ctlr, int im)
815 {
816 ilock(&ctlr->imlock);
817 ctlr->im |= im;
818 csr32w(ctlr, Ims, ctlr->im);
819 iunlock(&ctlr->imlock);
820 }
821
822 static int
igbelim(void * ctlr)823 igbelim(void* ctlr)
824 {
825 return ((Ctlr*)ctlr)->lim != 0;
826 }
827
828 static void
igbelproc(void * arg)829 igbelproc(void* arg)
830 {
831 Ctlr *ctlr;
832 Ether *edev;
833 MiiPhy *phy;
834 int ctrl, r;
835
836 edev = arg;
837 ctlr = edev->ctlr;
838 for(;;){
839 if(ctlr->mii == nil || ctlr->mii->curphy == nil) {
840 sched();
841 continue;
842 }
843
844 /*
845 * To do:
846 * logic to manage status change,
847 * this is incomplete but should work
848 * one time to set up the hardware.
849 *
850 * MiiPhy.speed, etc. should be in Mii.
851 */
852 if(miistatus(ctlr->mii) < 0)
853 //continue;
854 goto enable;
855
856 phy = ctlr->mii->curphy;
857 ctrl = csr32r(ctlr, Ctrl);
858
859 switch(ctlr->id){
860 case i82543gc:
861 case i82544ei:
862 case i82544eif:
863 default:
864 if(!(ctrl & Asde)){
865 ctrl &= ~(SspeedMASK|Ilos|Fd);
866 ctrl |= Frcdplx|Frcspd;
867 if(phy->speed == 1000)
868 ctrl |= Sspeed1000;
869 else if(phy->speed == 100)
870 ctrl |= Sspeed100;
871 if(phy->fd)
872 ctrl |= Fd;
873 }
874 break;
875
876 case i82540em:
877 case i82540eplp:
878 case i82547gi:
879 case i82541gi:
880 case i82541gi2:
881 case i82541pi:
882 break;
883 }
884
885 /*
886 * Collision Distance.
887 */
888 r = csr32r(ctlr, Tctl);
889 r &= ~ColdMASK;
890 if(phy->fd)
891 r |= 64<<ColdSHIFT;
892 else
893 r |= 512<<ColdSHIFT;
894 csr32w(ctlr, Tctl, r);
895
896 /*
897 * Flow control.
898 */
899 if(phy->rfc)
900 ctrl |= Rfce;
901 if(phy->tfc)
902 ctrl |= Tfce;
903 csr32w(ctlr, Ctrl, ctrl);
904
905 enable:
906 ctlr->lim = 0;
907 igbeim(ctlr, Lsc);
908
909 ctlr->lsleep++;
910 sleep(&ctlr->lrendez, igbelim, ctlr);
911 }
912 }
913
914 static void
igbetxinit(Ctlr * ctlr)915 igbetxinit(Ctlr* ctlr)
916 {
917 int i, r;
918 Block *bp;
919
920 csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));
921 switch(ctlr->id){
922 default:
923 r = 6;
924 break;
925 case i82543gc:
926 case i82544ei:
927 case i82544eif:
928 case i82544gc:
929 case i82540em:
930 case i82540eplp:
931 case i82541ei:
932 case i82541gi:
933 case i82541gi2:
934 case i82541pi:
935 case i82545em:
936 case i82545gmc:
937 case i82546gb:
938 case i82546eb:
939 case i82547ei:
940 case i82547gi:
941 r = 8;
942 break;
943 }
944 csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
945 csr32w(ctlr, Ait, 0);
946 csr32w(ctlr, Txdmac, 0);
947
948 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
949 csr32w(ctlr, Tdbah, 0);
950 csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td));
951 ctlr->tdh = PREV(0, ctlr->ntd);
952 csr32w(ctlr, Tdh, 0);
953 ctlr->tdt = 0;
954 csr32w(ctlr, Tdt, 0);
955
956 for(i = 0; i < ctlr->ntd; i++){
957 if((bp = ctlr->tb[i]) != nil){
958 ctlr->tb[i] = nil;
959 freeb(bp);
960 }
961 memset(&ctlr->tdba[i], 0, sizeof(Td));
962 }
963 ctlr->tdfree = ctlr->ntd;
964
965 csr32w(ctlr, Tidv, 128);
966 r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
967
968 switch(ctlr->id){
969 default:
970 break;
971 case i82540em:
972 case i82540eplp:
973 case i82547gi:
974 case i82545em:
975 case i82545gmc:
976 case i82546gb:
977 case i82546eb:
978 case i82541gi:
979 case i82541gi2:
980 case i82541pi:
981 r = csr32r(ctlr, Txdctl);
982 r &= ~WthreshMASK;
983 r |= Gran|(4<<WthreshSHIFT);
984
985 csr32w(ctlr, Tadv, 64);
986 break;
987 }
988
989 csr32w(ctlr, Txdctl, r);
990
991 r = csr32r(ctlr, Tctl);
992 r |= Ten;
993 csr32w(ctlr, Tctl, r);
994 }
995
996 static void
igbetransmit(Ether * edev)997 igbetransmit(Ether* edev)
998 {
999 Td *td;
1000 Block *bp;
1001 Ctlr *ctlr;
1002 int tdh, tdt;
1003
1004 ctlr = edev->ctlr;
1005
1006 ilock(&ctlr->tlock);
1007
1008 /*
1009 * Free any completed packets
1010 */
1011 tdh = ctlr->tdh;
1012 while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){
1013 if((bp = ctlr->tb[tdh]) != nil){
1014 ctlr->tb[tdh] = nil;
1015 freeb(bp);
1016 }
1017 memset(&ctlr->tdba[tdh], 0, sizeof(Td));
1018 tdh = NEXT(tdh, ctlr->ntd);
1019 }
1020 ctlr->tdh = tdh;
1021
1022 /*
1023 * Try to fill the ring back up.
1024 */
1025 tdt = ctlr->tdt;
1026 while(NEXT(tdt, ctlr->ntd) != tdh){
1027 if((bp = qget(edev->oq)) == nil)
1028 break;
1029 td = &ctlr->tdba[tdt];
1030 td->addr[0] = PCIWADDR(bp->rp);
1031 td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT);
1032 td->control |= Dext|Ifcs|Teop|DtypeDD;
1033 ctlr->tb[tdt] = bp;
1034 /* note size of queue of tds awaiting transmission */
1035 notemark(&ctlr->wmtd, (tdt + Ntd - tdh) % Ntd);
1036 tdt = NEXT(tdt, ctlr->ntd);
1037 if(NEXT(tdt, ctlr->ntd) == tdh){
1038 td->control |= Rs;
1039 ctlr->txdw++;
1040 ctlr->tdt = tdt;
1041 csr32w(ctlr, Tdt, tdt);
1042 igbeim(ctlr, Txdw);
1043 break;
1044 }
1045 ctlr->tdt = tdt;
1046 csr32w(ctlr, Tdt, tdt);
1047 }
1048
1049 iunlock(&ctlr->tlock);
1050 }
1051
1052 static void
igbereplenish(Ctlr * ctlr)1053 igbereplenish(Ctlr* ctlr)
1054 {
1055 Rd *rd;
1056 int rdt;
1057 Block *bp;
1058
1059 rdt = ctlr->rdt;
1060 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
1061 rd = &ctlr->rdba[rdt];
1062 if(ctlr->rb[rdt] == nil){
1063 bp = igberballoc();
1064 if(bp == nil){
1065 iprint("#l%d: igbereplenish: no available buffers\n",
1066 ctlr->edev->ctlrno);
1067 break;
1068 }
1069 ctlr->rb[rdt] = bp;
1070 rd->addr[0] = PCIWADDR(bp->rp);
1071 rd->addr[1] = 0;
1072 }
1073 coherence();
1074 rd->status = 0;
1075 rdt = NEXT(rdt, ctlr->nrd);
1076 ctlr->rdfree++;
1077 }
1078 ctlr->rdt = rdt;
1079 csr32w(ctlr, Rdt, rdt);
1080 }
1081
1082 static void
igberxinit(Ctlr * ctlr)1083 igberxinit(Ctlr* ctlr)
1084 {
1085 int i;
1086 Block *bp;
1087
1088 /* temporarily keep Mpe on */
1089 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF|Mpe);
1090
1091 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
1092 csr32w(ctlr, Rdbah, 0);
1093 csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd));
1094 ctlr->rdh = 0;
1095 csr32w(ctlr, Rdh, 0);
1096 ctlr->rdt = 0;
1097 csr32w(ctlr, Rdt, 0);
1098 ctlr->rdtr = 0;
1099 csr32w(ctlr, Rdtr, Fpd|0);
1100
1101 for(i = 0; i < ctlr->nrd; i++){
1102 if((bp = ctlr->rb[i]) != nil){
1103 ctlr->rb[i] = nil;
1104 freeb(bp);
1105 }
1106 }
1107 igbereplenish(ctlr);
1108 nrbfull = 0;
1109
1110 switch(ctlr->id){
1111 case i82540em:
1112 case i82540eplp:
1113 case i82541gi:
1114 case i82541gi2:
1115 case i82541pi:
1116 case i82545em:
1117 case i82545gmc:
1118 case i82546gb:
1119 case i82546eb:
1120 case i82547gi:
1121 csr32w(ctlr, Radv, 64);
1122 break;
1123 }
1124 csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
1125
1126 /*
1127 * Disable checksum offload as it has known bugs.
1128 */
1129 csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
1130 }
1131
1132 static int
igberim(void * ctlr)1133 igberim(void* ctlr)
1134 {
1135 return ((Ctlr*)ctlr)->rim != 0;
1136 }
1137
1138 static void
igberproc(void * arg)1139 igberproc(void* arg)
1140 {
1141 Rd *rd;
1142 Block *bp;
1143 Ctlr *ctlr;
1144 int r, rdh, passed;
1145 Ether *edev;
1146
1147 edev = arg;
1148 ctlr = edev->ctlr;
1149
1150 igberxinit(ctlr);
1151 r = csr32r(ctlr, Rctl);
1152 r |= Ren;
1153 csr32w(ctlr, Rctl, r);
1154 for(;;){
1155 ctlr->rim = 0;
1156 igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
1157 ctlr->rsleep++;
1158 sleep(&ctlr->rrendez, igberim, ctlr);
1159
1160 rdh = ctlr->rdh;
1161 passed = 0;
1162 for(;;){
1163 rd = &ctlr->rdba[rdh];
1164
1165 if(!(rd->status & Rdd))
1166 break;
1167
1168 /*
1169 * Accept eop packets with no errors.
1170 * With no errors and the Ixsm bit set,
1171 * the descriptor status Tpcs and Ipcs bits give
1172 * an indication of whether the checksums were
1173 * calculated and valid.
1174 */
1175 /* ignore checksum offload as it has known bugs. */
1176 rd->errors &= ~(Ipe | Tcpe);
1177 if((rd->status & Reop) && rd->errors == 0){
1178 bp = ctlr->rb[rdh];
1179 ctlr->rb[rdh] = nil;
1180 bp->wp += rd->length;
1181 bp->next = nil;
1182 /* ignore checksum offload as it has known bugs. */
1183 if(0 && !(rd->status & Ixsm)){
1184 ctlr->ixsm++;
1185 if(rd->status & Ipcs){
1186 /*
1187 * IP checksum calculated
1188 * (and valid as errors == 0).
1189 */
1190 ctlr->ipcs++;
1191 bp->flag |= Bipck;
1192 }
1193 if(rd->status & Tcpcs){
1194 /*
1195 * TCP/UDP checksum calculated
1196 * (and valid as errors == 0).
1197 */
1198 ctlr->tcpcs++;
1199 bp->flag |= Btcpck|Budpck;
1200 }
1201 bp->checksum = rd->checksum;
1202 bp->flag |= Bpktck;
1203 }
1204 ilock(&igberblock);
1205 nrbfull++;
1206 iunlock(&igberblock);
1207 notemark(&ctlr->wmrb, nrbfull);
1208 etheriq(edev, bp, 1);
1209 passed++;
1210 }
1211 else if(ctlr->rb[rdh] != nil){
1212 freeb(ctlr->rb[rdh]);
1213 ctlr->rb[rdh] = nil;
1214 }
1215
1216 memset(rd, 0, sizeof(Rd));
1217 coherence();
1218 ctlr->rdfree--;
1219 rdh = NEXT(rdh, ctlr->nrd);
1220 }
1221 ctlr->rdh = rdh;
1222
1223 if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
1224 igbereplenish(ctlr);
1225 /* note how many rds had full buffers */
1226 notemark(&ctlr->wmrd, passed);
1227 }
1228 }
1229
1230 static void
igbeattach(Ether * edev)1231 igbeattach(Ether* edev)
1232 {
1233 Block *bp;
1234 Ctlr *ctlr;
1235 char name[KNAMELEN];
1236
1237 ctlr = edev->ctlr;
1238 ctlr->edev = edev; /* point back to Ether* */
1239 qlock(&ctlr->alock);
1240 if(ctlr->alloc != nil){ /* already allocated? */
1241 qunlock(&ctlr->alock);
1242 return;
1243 }
1244
1245 ctlr->tb = nil;
1246 ctlr->rb = nil;
1247 ctlr->alloc = nil;
1248 ctlr->nrb = 0;
1249 if(waserror()){
1250 while(ctlr->nrb > 0){
1251 bp = igberballoc();
1252 bp->free = nil;
1253 freeb(bp);
1254 ctlr->nrb--;
1255 }
1256 free(ctlr->tb);
1257 ctlr->tb = nil;
1258 free(ctlr->rb);
1259 ctlr->rb = nil;
1260 free(ctlr->alloc);
1261 ctlr->alloc = nil;
1262 qunlock(&ctlr->alock);
1263 nexterror();
1264 }
1265
1266 ctlr->nrd = ROUND(Nrd, 8);
1267 ctlr->ntd = ROUND(Ntd, 8);
1268 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127);
1269 if(ctlr->alloc == nil) {
1270 print("igbe: can't allocate ctlr->alloc\n");
1271 error(Enomem);
1272 }
1273 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 128);
1274 ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd);
1275
1276 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
1277 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
1278 if (ctlr->rb == nil || ctlr->tb == nil) {
1279 print("igbe: can't allocate ctlr->rb or ctlr->tb\n");
1280 error(Enomem);
1281 }
1282
1283 for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){
1284 if((bp = allocb(Rbsz)) == nil)
1285 break;
1286 bp->free = igberbfree;
1287 freeb(bp);
1288 }
1289 initmark(&ctlr->wmrb, Nrb, "rcv bufs unprocessed");
1290 initmark(&ctlr->wmrd, Nrd-1, "rcv descrs processed at once");
1291 initmark(&ctlr->wmtd, Ntd-1, "xmit descr queue len");
1292
1293 snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
1294 kproc(name, igbelproc, edev);
1295
1296 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1297 kproc(name, igberproc, edev);
1298
1299 igbetxinit(ctlr);
1300
1301 qunlock(&ctlr->alock);
1302 poperror();
1303 }
1304
1305 static void
igbeinterrupt(Ureg *,void * arg)1306 igbeinterrupt(Ureg*, void* arg)
1307 {
1308 Ctlr *ctlr;
1309 Ether *edev;
1310 int icr, im, txdw;
1311
1312 edev = arg;
1313 ctlr = edev->ctlr;
1314
1315 ilock(&ctlr->imlock);
1316 csr32w(ctlr, Imc, ~0);
1317 im = ctlr->im;
1318 txdw = 0;
1319
1320 while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
1321 if(icr & Lsc){
1322 im &= ~Lsc;
1323 ctlr->lim = icr & Lsc;
1324 wakeup(&ctlr->lrendez);
1325 ctlr->lintr++;
1326 }
1327 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){
1328 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq);
1329 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq);
1330 wakeup(&ctlr->rrendez);
1331 ctlr->rintr++;
1332 }
1333 if(icr & Txdw){
1334 im &= ~Txdw;
1335 txdw++;
1336 ctlr->tintr++;
1337 }
1338 }
1339
1340 ctlr->im = im;
1341 csr32w(ctlr, Ims, im);
1342 iunlock(&ctlr->imlock);
1343
1344 if(txdw)
1345 igbetransmit(edev);
1346 }
1347
1348 static int
i82543mdior(Ctlr * ctlr,int n)1349 i82543mdior(Ctlr* ctlr, int n)
1350 {
1351 int ctrl, data, i, r;
1352
1353 /*
1354 * Read n bits from the Management Data I/O Interface.
1355 */
1356 ctrl = csr32r(ctlr, Ctrl);
1357 r = (ctrl & ~Mddo)|Mdco;
1358 data = 0;
1359 for(i = n-1; i >= 0; i--){
1360 if(csr32r(ctlr, Ctrl) & Mdd)
1361 data |= (1<<i);
1362 csr32w(ctlr, Ctrl, Mdc|r);
1363 csr32w(ctlr, Ctrl, r);
1364 }
1365 csr32w(ctlr, Ctrl, ctrl);
1366
1367 return data;
1368 }
1369
1370 static int
i82543mdiow(Ctlr * ctlr,int bits,int n)1371 i82543mdiow(Ctlr* ctlr, int bits, int n)
1372 {
1373 int ctrl, i, r;
1374
1375 /*
1376 * Write n bits to the Management Data I/O Interface.
1377 */
1378 ctrl = csr32r(ctlr, Ctrl);
1379 r = Mdco|Mddo|ctrl;
1380 for(i = n-1; i >= 0; i--){
1381 if(bits & (1<<i))
1382 r |= Mdd;
1383 else
1384 r &= ~Mdd;
1385 csr32w(ctlr, Ctrl, Mdc|r);
1386 csr32w(ctlr, Ctrl, r);
1387 }
1388 csr32w(ctlr, Ctrl, ctrl);
1389
1390 return 0;
1391 }
1392
1393 static int
i82543miimir(Mii * mii,int pa,int ra)1394 i82543miimir(Mii* mii, int pa, int ra)
1395 {
1396 int data;
1397 Ctlr *ctlr;
1398
1399 ctlr = mii->ctlr;
1400
1401 /*
1402 * MII Management Interface Read.
1403 *
1404 * Preamble;
1405 * ST+OP+PHYAD+REGAD;
1406 * TA + 16 data bits.
1407 */
1408 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1409 i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
1410 data = i82543mdior(ctlr, 18);
1411
1412 if(data & 0x10000)
1413 return -1;
1414
1415 return data & 0xFFFF;
1416 }
1417
1418 static int
i82543miimiw(Mii * mii,int pa,int ra,int data)1419 i82543miimiw(Mii* mii, int pa, int ra, int data)
1420 {
1421 Ctlr *ctlr;
1422
1423 ctlr = mii->ctlr;
1424
1425 /*
1426 * MII Management Interface Write.
1427 *
1428 * Preamble;
1429 * ST+OP+PHYAD+REGAD+TA + 16 data bits;
1430 * Z.
1431 */
1432 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1433 data &= 0xFFFF;
1434 data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
1435 i82543mdiow(ctlr, data, 32);
1436
1437 return 0;
1438 }
1439
1440 static int
igbemiimir(Mii * mii,int pa,int ra)1441 igbemiimir(Mii* mii, int pa, int ra)
1442 {
1443 Ctlr *ctlr;
1444 int mdic, timo;
1445
1446 ctlr = mii->ctlr;
1447
1448 csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
1449 mdic = 0;
1450 for(timo = 64; timo; timo--){
1451 mdic = csr32r(ctlr, Mdic);
1452 if(mdic & (MDIe|MDIready))
1453 break;
1454 microdelay(1);
1455 }
1456
1457 if((mdic & (MDIe|MDIready)) == MDIready)
1458 return mdic & 0xFFFF;
1459 return -1;
1460 }
1461
1462 static int
igbemiimiw(Mii * mii,int pa,int ra,int data)1463 igbemiimiw(Mii* mii, int pa, int ra, int data)
1464 {
1465 Ctlr *ctlr;
1466 int mdic, timo;
1467
1468 ctlr = mii->ctlr;
1469
1470 data &= MDIdMASK;
1471 csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
1472 mdic = 0;
1473 for(timo = 64; timo; timo--){
1474 mdic = csr32r(ctlr, Mdic);
1475 if(mdic & (MDIe|MDIready))
1476 break;
1477 microdelay(1);
1478 }
1479 if((mdic & (MDIe|MDIready)) == MDIready)
1480 return 0;
1481 return -1;
1482 }
1483
1484 static int
igbemii(Ctlr * ctlr)1485 igbemii(Ctlr* ctlr)
1486 {
1487 MiiPhy *phy;
1488 int ctrl, p, r;
1489
1490 r = csr32r(ctlr, Status);
1491 if(r & Tbimode)
1492 return -1;
1493 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
1494 return -1;
1495 ctlr->mii->ctlr = ctlr;
1496
1497 ctrl = csr32r(ctlr, Ctrl);
1498 ctrl |= Slu;
1499
1500 switch(ctlr->id){
1501 case i82543gc:
1502 ctrl |= Frcdplx|Frcspd;
1503 csr32w(ctlr, Ctrl, ctrl);
1504
1505 /*
1506 * The reset pin direction (Mdro) should already
1507 * be set from the EEPROM load.
1508 * If it's not set this configuration is unexpected
1509 * so bail.
1510 */
1511 r = csr32r(ctlr, Ctrlext);
1512 if(!(r & Mdro)) {
1513 print("igbe: 82543gc Mdro not set\n");
1514 return -1;
1515 }
1516 csr32w(ctlr, Ctrlext, r);
1517 delay(20);
1518 r = csr32r(ctlr, Ctrlext);
1519 r &= ~Mdr;
1520 csr32w(ctlr, Ctrlext, r);
1521 delay(20);
1522 r = csr32r(ctlr, Ctrlext);
1523 r |= Mdr;
1524 csr32w(ctlr, Ctrlext, r);
1525 delay(20);
1526
1527 ctlr->mii->mir = i82543miimir;
1528 ctlr->mii->miw = i82543miimiw;
1529 break;
1530 case i82544ei:
1531 case i82544eif:
1532 case i82544gc:
1533 case i82540em:
1534 case i82540eplp:
1535 case i82547ei:
1536 case i82547gi:
1537 case i82541ei:
1538 case i82541gi:
1539 case i82541gi2:
1540 case i82541pi:
1541 case i82545em:
1542 case i82545gmc:
1543 case i82546gb:
1544 case i82546eb:
1545 ctrl &= ~(Frcdplx|Frcspd);
1546 csr32w(ctlr, Ctrl, ctrl);
1547 ctlr->mii->mir = igbemiimir;
1548 ctlr->mii->miw = igbemiimiw;
1549 break;
1550 default:
1551 free(ctlr->mii);
1552 ctlr->mii = nil;
1553 return -1;
1554 }
1555
1556 if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
1557 free(ctlr->mii);
1558 ctlr->mii = nil;
1559 return -1;
1560 }
1561 USED(phy);
1562 // print("oui %X phyno %d\n", phy->oui, phy->phyno);
1563
1564 /*
1565 * 8254X-specific PHY registers not in 802.3:
1566 * 0x10 PHY specific control
1567 * 0x14 extended PHY specific control
1568 * Set appropriate values then reset the PHY to have
1569 * changes noted.
1570 */
1571 switch(ctlr->id){
1572 case i82547gi:
1573 case i82541gi:
1574 case i82541gi2:
1575 case i82541pi:
1576 case i82545em:
1577 case i82545gmc:
1578 case i82546gb:
1579 case i82546eb:
1580 break;
1581 default:
1582 r = miimir(ctlr->mii, 16);
1583 r |= 0x0800; /* assert CRS on Tx */
1584 r |= 0x0060; /* auto-crossover all speeds */
1585 r |= 0x0002; /* polarity reversal enabled */
1586 miimiw(ctlr->mii, 16, r);
1587
1588 r = miimir(ctlr->mii, 20);
1589 r |= 0x0070; /* +25MHz clock */
1590 r &= ~0x0F00;
1591 r |= 0x0100; /* 1x downshift */
1592 miimiw(ctlr->mii, 20, r);
1593
1594 miireset(ctlr->mii);
1595 p = 0;
1596 if(ctlr->txcw & TxcwPs)
1597 p |= AnaP;
1598 if(ctlr->txcw & TxcwAs)
1599 p |= AnaAP;
1600 miiane(ctlr->mii, ~0, p, ~0);
1601 break;
1602 }
1603 return 0;
1604 }
1605
1606 static int
at93c46io(Ctlr * ctlr,char * op,int data)1607 at93c46io(Ctlr* ctlr, char* op, int data)
1608 {
1609 char *lp, *p;
1610 int i, loop, eecd, r;
1611
1612 eecd = csr32r(ctlr, Eecd);
1613
1614 r = 0;
1615 loop = -1;
1616 lp = nil;
1617 for(p = op; *p != '\0'; p++){
1618 switch(*p){
1619 default:
1620 return -1;
1621 case ' ':
1622 continue;
1623 case ':': /* start of loop */
1624 loop = strtol(p+1, &lp, 0)-1;
1625 lp--;
1626 if(p == lp)
1627 loop = 7;
1628 p = lp;
1629 continue;
1630 case ';': /* end of loop */
1631 if(lp == nil)
1632 return -1;
1633 loop--;
1634 if(loop >= 0)
1635 p = lp;
1636 else
1637 lp = nil;
1638 continue;
1639 case 'C': /* assert clock */
1640 eecd |= Sk;
1641 break;
1642 case 'c': /* deassert clock */
1643 eecd &= ~Sk;
1644 break;
1645 case 'D': /* next bit in 'data' byte */
1646 if(loop < 0)
1647 return -1;
1648 if(data & (1<<loop))
1649 eecd |= Di;
1650 else
1651 eecd &= ~Di;
1652 break;
1653 case 'O': /* collect data output */
1654 i = (csr32r(ctlr, Eecd) & Do) != 0;
1655 if(loop >= 0)
1656 r |= (i<<loop);
1657 else
1658 r = i;
1659 continue;
1660 case 'I': /* assert data input */
1661 eecd |= Di;
1662 break;
1663 case 'i': /* deassert data input */
1664 eecd &= ~Di;
1665 break;
1666 case 'S': /* enable chip select */
1667 eecd |= Cs;
1668 break;
1669 case 's': /* disable chip select */
1670 eecd &= ~Cs;
1671 break;
1672 }
1673 csr32w(ctlr, Eecd, eecd);
1674 microdelay(50);
1675 }
1676 if(loop >= 0)
1677 return -1;
1678 return r;
1679 }
1680
1681 static int
at93c46r(Ctlr * ctlr)1682 at93c46r(Ctlr* ctlr)
1683 {
1684 ushort sum;
1685 char rop[20];
1686 int addr, areq, bits, data, eecd, i;
1687
1688 eecd = csr32r(ctlr, Eecd);
1689 if(eecd & Spi){
1690 print("igbe: SPI EEPROM access not implemented\n");
1691 return 0;
1692 }
1693 if(eecd & (Eeszaddr|Eesz256))
1694 bits = 8;
1695 else
1696 bits = 6;
1697
1698 sum = 0;
1699
1700 switch(ctlr->id){
1701 default:
1702 areq = 0;
1703 break;
1704 case i82540em:
1705 case i82540eplp:
1706 case i82541ei:
1707 case i82541gi:
1708 case i82541gi2:
1709 case i82541pi:
1710 case i82545em:
1711 case i82545gmc:
1712 case i82546gb:
1713 case i82546eb:
1714 case i82547ei:
1715 case i82547gi:
1716 areq = 1;
1717 csr32w(ctlr, Eecd, eecd|Areq);
1718 for(i = 0; i < 1000; i++){
1719 if((eecd = csr32r(ctlr, Eecd)) & Agnt)
1720 break;
1721 microdelay(5);
1722 }
1723 if(!(eecd & Agnt)){
1724 print("igbe: not granted EEPROM access\n");
1725 goto release;
1726 }
1727 break;
1728 }
1729 snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
1730
1731 for(addr = 0; addr < 0x40; addr++){
1732 /*
1733 * Read a word at address 'addr' from the Atmel AT93C46
1734 * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1735 * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1736 * for protocol details.
1737 */
1738 if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
1739 print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
1740 goto release;
1741 }
1742 data = at93c46io(ctlr, ":16COc;", 0);
1743 at93c46io(ctlr, "sic", 0);
1744 ctlr->eeprom[addr] = data;
1745 sum += data;
1746 }
1747
1748 release:
1749 if(areq)
1750 csr32w(ctlr, Eecd, eecd & ~Areq);
1751 return sum;
1752 }
1753
1754 static int
igbedetach(Ctlr * ctlr)1755 igbedetach(Ctlr* ctlr)
1756 {
1757 int r, timeo;
1758
1759 /*
1760 * Perform a device reset to get the chip back to the
1761 * power-on state, followed by an EEPROM reset to read
1762 * the defaults for some internal registers.
1763 */
1764 csr32w(ctlr, Imc, ~0);
1765 csr32w(ctlr, Rctl, 0);
1766 csr32w(ctlr, Tctl, 0);
1767
1768 delay(10);
1769
1770 csr32w(ctlr, Ctrl, Devrst);
1771 delay(1);
1772 for(timeo = 0; timeo < 1000; timeo++){
1773 if(!(csr32r(ctlr, Ctrl) & Devrst))
1774 break;
1775 delay(1);
1776 }
1777 if(csr32r(ctlr, Ctrl) & Devrst)
1778 return -1;
1779 r = csr32r(ctlr, Ctrlext);
1780 csr32w(ctlr, Ctrlext, r|Eerst);
1781 delay(1);
1782 for(timeo = 0; timeo < 1000; timeo++){
1783 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1784 break;
1785 delay(1);
1786 }
1787 if(csr32r(ctlr, Ctrlext) & Eerst)
1788 return -1;
1789
1790 switch(ctlr->id){
1791 default:
1792 break;
1793 case i82540em:
1794 case i82540eplp:
1795 case i82541gi:
1796 case i82541gi2:
1797 case i82541pi:
1798 case i82545em:
1799 case i82545gmc:
1800 case i82547gi:
1801 case i82546gb:
1802 case i82546eb:
1803 r = csr32r(ctlr, Manc);
1804 r &= ~Arpen;
1805 csr32w(ctlr, Manc, r);
1806 break;
1807 }
1808
1809 csr32w(ctlr, Imc, ~0);
1810 delay(1);
1811 for(timeo = 0; timeo < 1000; timeo++){
1812 if(!csr32r(ctlr, Icr))
1813 break;
1814 delay(1);
1815 }
1816 if(csr32r(ctlr, Icr))
1817 return -1;
1818
1819 return 0;
1820 }
1821
1822 static void
igbeshutdown(Ether * ether)1823 igbeshutdown(Ether* ether)
1824 {
1825 igbedetach(ether->ctlr);
1826 }
1827
1828 static int
igbereset(Ctlr * ctlr)1829 igbereset(Ctlr* ctlr)
1830 {
1831 int ctrl, i, pause, r, swdpio, txcw;
1832
1833 if(igbedetach(ctlr))
1834 return -1;
1835
1836 /*
1837 * Read the EEPROM, validate the checksum
1838 * then get the device back to a power-on state.
1839 */
1840 if((r = at93c46r(ctlr)) != 0xBABA){
1841 print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
1842 return -1;
1843 }
1844
1845 /*
1846 * Snarf and set up the receive addresses.
1847 * There are 16 addresses. The first should be the MAC address.
1848 * The others are cleared and not marked valid (MS bit of Rah).
1849 */
1850 if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
1851 BUSFNO(ctlr->pcidev->tbdf) == 1)
1852 ctlr->eeprom[Ea+2] += 0x100; /* second interface */
1853 if(ctlr->id == i82541gi && ctlr->eeprom[Ea] == 0xFFFF)
1854 ctlr->eeprom[Ea] = 0xD000;
1855 for(i = Ea; i < Eaddrlen/2; i++){
1856 ctlr->ra[2*i] = ctlr->eeprom[i];
1857 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
1858 }
1859 /* lan id seems to vary on 82543gc; don't use it */
1860 if (ctlr->id != i82543gc) {
1861 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1862 ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */
1863 }
1864
1865 r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
1866 csr32w(ctlr, Ral, r);
1867 r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
1868 csr32w(ctlr, Rah, r);
1869 for(i = 1; i < 16; i++){
1870 csr32w(ctlr, Ral+i*8, 0);
1871 csr32w(ctlr, Rah+i*8, 0);
1872 }
1873
1874 /*
1875 * Clear the Multicast Table Array.
1876 * It's a 4096 bit vector accessed as 128 32-bit registers.
1877 */
1878 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1879 for(i = 0; i < 128; i++)
1880 csr32w(ctlr, Mta+i*4, 0);
1881
1882 /*
1883 * Just in case the Eerst didn't load the defaults
1884 * (doesn't appear to fully on the 82543GC), do it manually.
1885 */
1886 if (ctlr->id == i82543gc) {
1887 txcw = csr32r(ctlr, Txcw);
1888 txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
1889 ctrl = csr32r(ctlr, Ctrl);
1890 ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
1891
1892 if(ctlr->eeprom[Icw1] & 0x0400){
1893 ctrl |= Fd;
1894 txcw |= TxcwFd;
1895 }
1896 if(ctlr->eeprom[Icw1] & 0x0200)
1897 ctrl |= Lrst;
1898 if(ctlr->eeprom[Icw1] & 0x0010)
1899 ctrl |= Ilos;
1900 if(ctlr->eeprom[Icw1] & 0x0800)
1901 ctrl |= Frcspd;
1902 swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
1903 ctrl |= swdpio<<SwdpioloSHIFT;
1904 csr32w(ctlr, Ctrl, ctrl);
1905
1906 ctrl = csr32r(ctlr, Ctrlext);
1907 ctrl &= ~(Ips|SwdpiohiMASK);
1908 swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
1909 if(ctlr->eeprom[Icw1] & 0x1000)
1910 ctrl |= Ips;
1911 ctrl |= swdpio<<SwdpiohiSHIFT;
1912 csr32w(ctlr, Ctrlext, ctrl);
1913
1914 if(ctlr->eeprom[Icw2] & 0x0800)
1915 txcw |= TxcwAne;
1916 pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
1917 txcw |= pause<<TxcwPauseSHIFT;
1918 switch(pause){
1919 default:
1920 ctlr->fcrtl = 0x00002000;
1921 ctlr->fcrth = 0x00004000;
1922 txcw |= TxcwAs|TxcwPs;
1923 break;
1924 case 0:
1925 ctlr->fcrtl = 0x00002000;
1926 ctlr->fcrth = 0x00004000;
1927 break;
1928 case 2:
1929 ctlr->fcrtl = 0;
1930 ctlr->fcrth = 0;
1931 txcw |= TxcwAs;
1932 break;
1933 }
1934 ctlr->txcw = txcw;
1935 csr32w(ctlr, Txcw, txcw);
1936 }
1937
1938
1939 /*
1940 * Flow control - values from the datasheet.
1941 */
1942 csr32w(ctlr, Fcal, 0x00C28001);
1943 csr32w(ctlr, Fcah, 0x00000100);
1944 csr32w(ctlr, Fct, 0x00008808);
1945 csr32w(ctlr, Fcttv, 0x00000100);
1946
1947 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1948 csr32w(ctlr, Fcrth, ctlr->fcrth);
1949
1950 if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
1951 return -1;
1952
1953 return 0;
1954 }
1955
1956 static void
igbepci(void)1957 igbepci(void)
1958 {
1959 int cls;
1960 Pcidev *p;
1961 Ctlr *ctlr;
1962 void *mem;
1963
1964 p = nil;
1965 while(p = pcimatch(p, 0, 0)){
1966 if(p->ccrb != 0x02 || p->ccru != 0)
1967 continue;
1968
1969 switch((p->did<<16)|p->vid){
1970 default:
1971 continue;
1972 case i82543gc:
1973 case i82544ei:
1974 case i82544eif:
1975 case i82544gc:
1976 case i82547ei:
1977 case i82547gi:
1978 case i82540em:
1979 case i82540eplp:
1980 case i82541ei:
1981 case i82541gi:
1982 case i82541gi2:
1983 case i82541pi:
1984 case i82545em:
1985 case i82545gmc:
1986 case i82546gb:
1987 case i82546eb:
1988 break;
1989 }
1990
1991 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1992 if(mem == nil){
1993 print("igbe: can't map %8.8luX\n", p->mem[0].bar);
1994 continue;
1995 }
1996 cls = pcicfgr8(p, PciCLS);
1997 switch(cls){
1998 default:
1999 print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
2000 p->cls = 0x10;
2001 pcicfgw8(p, PciCLS, p->cls);
2002 break;
2003 case 0x08:
2004 case 0x10:
2005 break;
2006 }
2007 ctlr = malloc(sizeof(Ctlr));
2008 if(ctlr == nil) {
2009 vunmap(mem, p->mem[0].size);
2010 error(Enomem);
2011 }
2012 ctlr->port = p->mem[0].bar & ~0x0F;
2013 ctlr->pcidev = p;
2014 ctlr->id = (p->did<<16)|p->vid;
2015 ctlr->cls = cls*4;
2016 ctlr->nic = mem;
2017
2018 if(igbereset(ctlr)){
2019 free(ctlr);
2020 vunmap(mem, p->mem[0].size);
2021 continue;
2022 }
2023 pcisetbme(p);
2024
2025 if(igbectlrhead != nil)
2026 igbectlrtail->next = ctlr;
2027 else
2028 igbectlrhead = ctlr;
2029 igbectlrtail = ctlr;
2030 }
2031 }
2032
2033 static int
igbepnp(Ether * edev)2034 igbepnp(Ether* edev)
2035 {
2036 Ctlr *ctlr;
2037
2038 if(igbectlrhead == nil)
2039 igbepci();
2040
2041 /*
2042 * Any adapter matches if no edev->port is supplied,
2043 * otherwise the ports must match.
2044 */
2045 for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){
2046 if(ctlr->active)
2047 continue;
2048 if(edev->port == 0 || edev->port == ctlr->port){
2049 ctlr->active = 1;
2050 break;
2051 }
2052 }
2053 if(ctlr == nil)
2054 return -1;
2055
2056 edev->ctlr = ctlr;
2057 edev->port = ctlr->port;
2058 edev->irq = ctlr->pcidev->intl;
2059 edev->tbdf = ctlr->pcidev->tbdf;
2060 edev->mbps = 1000;
2061 memmove(edev->ea, ctlr->ra, Eaddrlen);
2062
2063 /*
2064 * Linkage to the generic ethernet driver.
2065 */
2066 edev->attach = igbeattach;
2067 edev->transmit = igbetransmit;
2068 edev->interrupt = igbeinterrupt;
2069 edev->ifstat = igbeifstat;
2070 edev->ctl = igbectl;
2071
2072 edev->arg = edev;
2073 edev->promiscuous = igbepromiscuous;
2074 edev->shutdown = igbeshutdown;
2075 edev->multicast = igbemulticast;
2076
2077 return 0;
2078 }
2079
2080 void
etherigbelink(void)2081 etherigbelink(void)
2082 {
2083 addethercard("i82543", igbepnp);
2084 addethercard("igbe", igbepnp);
2085 }
2086
2087