1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) 2004-2016 Synopsys, Inc.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The names of the above-listed copyright holders may not be used
15 * to endorse or promote products derived from this software without
16 * specific prior written permission.
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation; either version 2 of the License, or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/signal.h>
39 #include <sys/proc.h>
40 #include <sys/timeout.h>
41 #include <sys/mutex.h>
42 #include <sys/pool.h>
43 #include <sys/task.h>
44
45 #include <machine/bus.h>
46
47 #include <dev/usb/usb.h>
48 #include <dev/usb/usbdi.h>
49 #include <dev/usb/usbdivar.h>
50 #include <dev/usb/usb_mem.h>
51
52 #include <dev/usb/dwc2/dwc2.h>
53 #include <dev/usb/dwc2/dwc2var.h>
54
55 #include <dev/usb/dwc2/dwc2_core.h>
56 #include <dev/usb/dwc2/dwc2_hcd.h>
57
dwc2_set_dwctwo_params(struct dwc2_hsotg * hsotg)58 STATIC void dwc2_set_dwctwo_params(struct dwc2_hsotg *hsotg)
59 {
60 struct dwc2_core_params *p = &hsotg->params;
61 struct dwc2_softc *sc = hsotg->hsotg_sc;
62
63 p->otg_caps.hnp_support = sc->sc_params->otg_caps.hnp_support;
64 p->otg_caps.srp_support = sc->sc_params->otg_caps.srp_support;
65 p->host_dma = sc->sc_params->host_dma;
66 p->dma_desc_enable = sc->sc_params->dma_desc_enable;
67 p->speed = sc->sc_params->speed;
68 p->enable_dynamic_fifo = sc->sc_params->enable_dynamic_fifo;
69 p->en_multiple_tx_fifo = sc->sc_params->en_multiple_tx_fifo;
70 p->host_rx_fifo_size = sc->sc_params->host_rx_fifo_size;
71 p->host_nperio_tx_fifo_size = sc->sc_params->host_nperio_tx_fifo_size;
72 p->host_perio_tx_fifo_size = sc->sc_params->host_perio_tx_fifo_size;
73 p->max_transfer_size = sc->sc_params->max_transfer_size;
74 p->max_packet_count = sc->sc_params->max_packet_count;
75 p->host_channels = sc->sc_params->host_channels;
76 p->phy_type = sc->sc_params->phy_type;
77 p->phy_utmi_width = sc->sc_params->phy_utmi_width;
78 p->phy_ulpi_ddr = sc->sc_params->phy_ulpi_ddr;
79 p->phy_ulpi_ext_vbus = sc->sc_params->phy_ulpi_ext_vbus;
80 p->i2c_enable = sc->sc_params->i2c_enable;
81 p->ulpi_fs_ls = sc->sc_params->ulpi_fs_ls;
82 p->host_support_fs_ls_low_power = sc->sc_params->host_support_fs_ls_low_power;
83 p->host_ls_low_power_phy_clk = sc->sc_params->host_ls_low_power_phy_clk;
84 p->ts_dline = sc->sc_params->ts_dline;
85 p->reload_ctl = sc->sc_params->reload_ctl;
86 p->ahbcfg = sc->sc_params->ahbcfg;
87 p->uframe_sched = sc->sc_params->uframe_sched;
88 p->external_id_pin_ctl = sc->sc_params->external_id_pin_ctl;
89 }
90
91 #if 0
92 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
93 {
94 struct dwc2_core_params *p = &hsotg->params;
95
96 p->host_rx_fifo_size = 774;
97 p->max_transfer_size = 65535;
98 p->max_packet_count = 511;
99 p->ahbcfg = 0x10;
100 }
101
102 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
103 {
104 struct dwc2_core_params *p = &hsotg->params;
105
106 p->otg_caps.hnp_support = false;
107 p->otg_caps.srp_support = false;
108 p->speed = DWC2_SPEED_PARAM_HIGH;
109 p->host_rx_fifo_size = 512;
110 p->host_nperio_tx_fifo_size = 512;
111 p->host_perio_tx_fifo_size = 512;
112 p->max_transfer_size = 65535;
113 p->max_packet_count = 511;
114 p->host_channels = 16;
115 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
116 p->phy_utmi_width = 8;
117 p->i2c_enable = false;
118 p->reload_ctl = false;
119 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
120 GAHBCFG_HBSTLEN_SHIFT;
121 p->change_speed_quirk = true;
122 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
123 }
124
125 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
126 {
127 struct dwc2_core_params *p = &hsotg->params;
128
129 p->otg_caps.hnp_support = false;
130 p->speed = DWC2_SPEED_PARAM_HIGH;
131 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
132 p->phy_utmi_width = 16;
133 p->activate_ingenic_overcurrent_detection =
134 !device_property_read_bool(hsotg->dev, "disable-over-current");
135 }
136
137 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
138 {
139 struct dwc2_core_params *p = &hsotg->params;
140
141 p->otg_caps.hnp_support = false;
142 p->speed = DWC2_SPEED_PARAM_HIGH;
143 p->host_channels = 16;
144 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
145 p->phy_utmi_width = 16;
146 p->activate_ingenic_overcurrent_detection =
147 !device_property_read_bool(hsotg->dev, "disable-over-current");
148 }
149
150 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
151 {
152 struct dwc2_core_params *p = &hsotg->params;
153
154 p->otg_caps.hnp_support = false;
155 p->speed = DWC2_SPEED_PARAM_HIGH;
156 p->host_rx_fifo_size = 1024;
157 p->host_nperio_tx_fifo_size = 1024;
158 p->host_perio_tx_fifo_size = 1024;
159 p->host_channels = 16;
160 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
161 p->phy_utmi_width = 16;
162 p->activate_ingenic_overcurrent_detection =
163 !device_property_read_bool(hsotg->dev, "disable-over-current");
164 }
165
166 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
167 {
168 struct dwc2_core_params *p = &hsotg->params;
169
170 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
171 p->no_clock_gating = true;
172 p->phy_utmi_width = 8;
173 }
174
175 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
176 {
177 struct dwc2_core_params *p = &hsotg->params;
178
179 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
180 p->no_clock_gating = true;
181 }
182
183 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
184 {
185 struct dwc2_core_params *p = &hsotg->params;
186
187 p->otg_caps.hnp_support = false;
188 p->otg_caps.srp_support = false;
189 p->host_rx_fifo_size = 525;
190 p->host_nperio_tx_fifo_size = 128;
191 p->host_perio_tx_fifo_size = 256;
192 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
193 GAHBCFG_HBSTLEN_SHIFT;
194 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
195 }
196
197 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
198 {
199 struct dwc2_core_params *p = &hsotg->params;
200
201 p->otg_caps.hnp_support = false;
202 p->otg_caps.srp_support = false;
203 p->host_rx_fifo_size = 288;
204 p->host_nperio_tx_fifo_size = 128;
205 p->host_perio_tx_fifo_size = 96;
206 p->max_transfer_size = 65535;
207 p->max_packet_count = 511;
208 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
209 GAHBCFG_HBSTLEN_SHIFT;
210 }
211
212 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
213 {
214 struct dwc2_core_params *p = &hsotg->params;
215
216 p->otg_caps.hnp_support = false;
217 p->otg_caps.srp_support = false;
218 p->speed = DWC2_SPEED_PARAM_HIGH;
219 p->host_rx_fifo_size = 512;
220 p->host_nperio_tx_fifo_size = 500;
221 p->host_perio_tx_fifo_size = 500;
222 p->host_channels = 16;
223 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
224 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
225 GAHBCFG_HBSTLEN_SHIFT;
226 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
227 }
228
229 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
230 {
231 struct dwc2_core_params *p = &hsotg->params;
232
233 p->lpm = false;
234 p->lpm_clock_gating = false;
235 p->besl = false;
236 p->hird_threshold_en = false;
237 }
238
239 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
240 {
241 struct dwc2_core_params *p = &hsotg->params;
242
243 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
244 }
245
246 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
247 {
248 struct dwc2_core_params *p = &hsotg->params;
249
250 p->otg_caps.hnp_support = false;
251 p->otg_caps.srp_support = false;
252 p->speed = DWC2_SPEED_PARAM_FULL;
253 p->host_rx_fifo_size = 128;
254 p->host_nperio_tx_fifo_size = 96;
255 p->host_perio_tx_fifo_size = 96;
256 p->max_packet_count = 256;
257 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
258 p->i2c_enable = false;
259 p->activate_stm_fs_transceiver = true;
260 }
261
262 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
263 {
264 struct dwc2_core_params *p = &hsotg->params;
265
266 p->host_rx_fifo_size = 622;
267 p->host_nperio_tx_fifo_size = 128;
268 p->host_perio_tx_fifo_size = 256;
269 }
270
271 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
272 {
273 struct dwc2_core_params *p = &hsotg->params;
274
275 p->otg_caps.hnp_support = false;
276 p->otg_caps.srp_support = false;
277 p->otg_caps.otg_rev = 0x200;
278 p->speed = DWC2_SPEED_PARAM_FULL;
279 p->host_rx_fifo_size = 128;
280 p->host_nperio_tx_fifo_size = 96;
281 p->host_perio_tx_fifo_size = 96;
282 p->max_packet_count = 256;
283 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
284 p->i2c_enable = false;
285 p->activate_stm_fs_transceiver = true;
286 p->activate_stm_id_vb_detection = true;
287 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
288 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
289 p->host_support_fs_ls_low_power = true;
290 p->host_ls_low_power_phy_clk = true;
291 }
292
293 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
294 {
295 struct dwc2_core_params *p = &hsotg->params;
296
297 p->otg_caps.hnp_support = false;
298 p->otg_caps.srp_support = false;
299 p->otg_caps.otg_rev = 0x200;
300 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
301 p->host_rx_fifo_size = 440;
302 p->host_nperio_tx_fifo_size = 256;
303 p->host_perio_tx_fifo_size = 256;
304 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
305 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
306 p->lpm = false;
307 p->lpm_clock_gating = false;
308 p->besl = false;
309 p->hird_threshold_en = false;
310 }
311
312 const struct of_device_id dwc2_of_match_table[] = {
313 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
314 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
315 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
316 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
317 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
318 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
319 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
320 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
321 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
322 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
323 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
324 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
325 { .compatible = "snps,dwc2" },
326 { .compatible = "samsung,s3c6400-hsotg",
327 .data = dwc2_set_s3c6400_params },
328 { .compatible = "amlogic,meson8-usb",
329 .data = dwc2_set_amlogic_params },
330 { .compatible = "amlogic,meson8b-usb",
331 .data = dwc2_set_amlogic_params },
332 { .compatible = "amlogic,meson-gxbb-usb",
333 .data = dwc2_set_amlogic_params },
334 { .compatible = "amlogic,meson-g12a-usb",
335 .data = dwc2_set_amlogic_g12a_params },
336 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
337 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
338 { .compatible = "st,stm32f4x9-fsotg",
339 .data = dwc2_set_stm32f4x9_fsotg_params },
340 { .compatible = "st,stm32f4x9-hsotg" },
341 { .compatible = "st,stm32f7-hsotg",
342 .data = dwc2_set_stm32f7_hsotg_params },
343 { .compatible = "st,stm32mp15-fsotg",
344 .data = dwc2_set_stm32mp15_fsotg_params },
345 { .compatible = "st,stm32mp15-hsotg",
346 .data = dwc2_set_stm32mp15_hsotg_params },
347 { .compatible = "intel,socfpga-agilex-hsotg",
348 .data = dwc2_set_socfpga_agilex_params },
349 {},
350 };
351 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
352
353 const struct acpi_device_id dwc2_acpi_match[] = {
354 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
355 { },
356 };
357 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
358 #endif
359
dwc2_set_param_otg_cap(struct dwc2_hsotg * hsotg)360 STATIC void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
361 {
362 switch (hsotg->hw_params.op_mode) {
363 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
364 hsotg->params.otg_caps.hnp_support = true;
365 hsotg->params.otg_caps.srp_support = true;
366 break;
367 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
368 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
369 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
370 hsotg->params.otg_caps.hnp_support = false;
371 hsotg->params.otg_caps.srp_support = true;
372 break;
373 default:
374 hsotg->params.otg_caps.hnp_support = false;
375 hsotg->params.otg_caps.srp_support = false;
376 break;
377 }
378 }
379
dwc2_set_param_phy_type(struct dwc2_hsotg * hsotg)380 STATIC void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
381 {
382 int val;
383 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
384
385 val = DWC2_PHY_TYPE_PARAM_FS;
386 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
387 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
388 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
389 val = DWC2_PHY_TYPE_PARAM_UTMI;
390 else
391 val = DWC2_PHY_TYPE_PARAM_ULPI;
392 }
393
394 if (dwc2_is_fs_iot(hsotg))
395 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
396
397 hsotg->params.phy_type = val;
398 }
399
dwc2_set_param_speed(struct dwc2_hsotg * hsotg)400 STATIC void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
401 {
402 int val;
403
404 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
405 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
406
407 if (dwc2_is_fs_iot(hsotg))
408 val = DWC2_SPEED_PARAM_FULL;
409
410 if (dwc2_is_hs_iot(hsotg))
411 val = DWC2_SPEED_PARAM_HIGH;
412
413 hsotg->params.speed = val;
414 }
415
dwc2_set_param_phy_utmi_width(struct dwc2_hsotg * hsotg)416 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
417 {
418 #if 0
419 int val;
420
421 val = (hsotg->hw_params.utmi_phy_data_width ==
422 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
423
424 if (hsotg->phy) {
425 /*
426 * If using the generic PHY framework, check if the PHY bus
427 * width is 8-bit and set the phyif appropriately.
428 */
429 if (phy_get_bus_width(hsotg->phy) == 8)
430 val = 8;
431 }
432
433 hsotg->params.phy_utmi_width = val;
434 #endif
435 hsotg->params.phy_utmi_width = 8;
436 }
437
dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg * hsotg)438 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
439 {
440 struct dwc2_core_params *p = &hsotg->params;
441 int depth_average;
442 int fifo_count;
443 int i;
444
445 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
446
447 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
448 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
449 for (i = 1; i <= fifo_count; i++)
450 p->g_tx_fifo_size[i] = depth_average;
451 }
452
dwc2_set_param_power_down(struct dwc2_hsotg * hsotg)453 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
454 {
455 int val;
456
457 if (hsotg->hw_params.hibernation)
458 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
459 else if (hsotg->hw_params.power_optimized)
460 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
461 else
462 val = DWC2_POWER_DOWN_PARAM_NONE;
463
464 hsotg->params.power_down = val;
465 }
466
dwc2_set_param_lpm(struct dwc2_hsotg * hsotg)467 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
468 {
469 struct dwc2_core_params *p = &hsotg->params;
470
471 p->lpm = hsotg->hw_params.lpm_mode;
472 if (p->lpm) {
473 p->lpm_clock_gating = true;
474 p->besl = true;
475 p->hird_threshold_en = true;
476 p->hird_threshold = 4;
477 } else {
478 p->lpm_clock_gating = false;
479 p->besl = false;
480 p->hird_threshold_en = false;
481 }
482 }
483
484 /**
485 * dwc2_set_default_params() - Set all core parameters to their
486 * auto-detected default values.
487 *
488 * @hsotg: Programming view of the DWC_otg controller
489 *
490 */
dwc2_set_default_params(struct dwc2_hsotg * hsotg)491 STATIC void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
492 {
493 struct dwc2_hw_params *hw = &hsotg->hw_params;
494 struct dwc2_core_params *p = &hsotg->params;
495 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
496
497 dwc2_set_param_otg_cap(hsotg);
498 dwc2_set_param_phy_type(hsotg);
499 dwc2_set_param_speed(hsotg);
500 dwc2_set_param_phy_utmi_width(hsotg);
501 dwc2_set_param_power_down(hsotg);
502 dwc2_set_param_lpm(hsotg);
503 p->phy_ulpi_ddr = false;
504 p->phy_ulpi_ext_vbus = false;
505
506 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
507 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
508 p->i2c_enable = hw->i2c_enable;
509 p->acg_enable = hw->acg_enable;
510 p->ulpi_fs_ls = false;
511 p->ts_dline = false;
512 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
513 p->uframe_sched = true;
514 p->external_id_pin_ctl = false;
515 p->ipg_isoc_en = false;
516 p->service_interval = false;
517 p->max_packet_count = hw->max_packet_count;
518 p->max_transfer_size = hw->max_transfer_size;
519 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
520 p->ref_clk_per = 33333;
521 p->sof_cnt_wkup_alert = 100;
522
523 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
524 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
525 p->host_dma = dma_capable;
526 p->dma_desc_enable = false;
527 p->dma_desc_fs_enable = false;
528 p->host_support_fs_ls_low_power = false;
529 p->host_ls_low_power_phy_clk = false;
530 p->host_channels = hw->host_channels;
531 p->host_rx_fifo_size = hw->rx_fifo_size;
532 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
533 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
534 }
535
536 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
537 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
538 p->g_dma = dma_capable;
539 p->g_dma_desc = hw->dma_desc_enable;
540
541 /*
542 * The values for g_rx_fifo_size (2048) and
543 * g_np_tx_fifo_size (1024) come from the legacy s3c
544 * gadget driver. These defaults have been hard-coded
545 * for some time so many platforms depend on these
546 * values. Leave them as defaults for now and only
547 * auto-detect if the hardware does not support the
548 * default.
549 */
550 p->g_rx_fifo_size = 2048;
551 p->g_np_tx_fifo_size = 1024;
552 dwc2_set_param_tx_fifo_sizes(hsotg);
553 }
554 }
555
556 #if 0
557 /**
558 * dwc2_get_device_properties() - Read in device properties.
559 *
560 * @hsotg: Programming view of the DWC_otg controller
561 *
562 * Read in the device properties and adjust core parameters if needed.
563 */
564 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
565 {
566 struct dwc2_core_params *p = &hsotg->params;
567 int num;
568
569 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
570 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
571 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
572 &p->g_rx_fifo_size);
573
574 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
575 &p->g_np_tx_fifo_size);
576
577 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
578 if (num > 0) {
579 num = min(num, 15);
580 memset(p->g_tx_fifo_size, 0,
581 sizeof(p->g_tx_fifo_size));
582 device_property_read_u32_array(hsotg->dev,
583 "g-tx-fifo-size",
584 &p->g_tx_fifo_size[1],
585 num);
586 }
587
588 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
589 }
590
591 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
592 p->oc_disable = true;
593 }
594 #endif
595
dwc2_check_param_otg_cap(struct dwc2_hsotg * hsotg)596 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
597 {
598 int valid = 1;
599
600 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
601 /* check HNP && SRP capable */
602 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
603 valid = 0;
604 } else if (!hsotg->params.otg_caps.hnp_support) {
605 /* check SRP only capable */
606 if (hsotg->params.otg_caps.srp_support) {
607 switch (hsotg->hw_params.op_mode) {
608 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
609 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
610 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
611 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
612 break;
613 default:
614 valid = 0;
615 break;
616 }
617 }
618 /* else: NO HNP && NO SRP capable: always valid */
619 } else {
620 valid = 0;
621 }
622
623 if (!valid)
624 dwc2_set_param_otg_cap(hsotg);
625 }
626
dwc2_check_param_phy_type(struct dwc2_hsotg * hsotg)627 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
628 {
629 int valid = 0;
630 u32 hs_phy_type;
631 u32 fs_phy_type;
632
633 hs_phy_type = hsotg->hw_params.hs_phy_type;
634 fs_phy_type = hsotg->hw_params.fs_phy_type;
635
636 switch (hsotg->params.phy_type) {
637 case DWC2_PHY_TYPE_PARAM_FS:
638 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
639 valid = 1;
640 break;
641 case DWC2_PHY_TYPE_PARAM_UTMI:
642 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
643 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
644 valid = 1;
645 break;
646 case DWC2_PHY_TYPE_PARAM_ULPI:
647 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
648 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
649 valid = 1;
650 break;
651 default:
652 break;
653 }
654
655 if (!valid)
656 dwc2_set_param_phy_type(hsotg);
657 }
658
dwc2_check_param_speed(struct dwc2_hsotg * hsotg)659 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
660 {
661 int valid = 1;
662 int phy_type = hsotg->params.phy_type;
663 int speed = hsotg->params.speed;
664
665 switch (speed) {
666 case DWC2_SPEED_PARAM_HIGH:
667 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
668 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
669 valid = 0;
670 break;
671 case DWC2_SPEED_PARAM_FULL:
672 case DWC2_SPEED_PARAM_LOW:
673 break;
674 default:
675 valid = 0;
676 break;
677 }
678
679 if (!valid)
680 dwc2_set_param_speed(hsotg);
681 }
682
dwc2_check_param_phy_utmi_width(struct dwc2_hsotg * hsotg)683 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
684 {
685 int valid = 0;
686 int param = hsotg->params.phy_utmi_width;
687 int width = hsotg->hw_params.utmi_phy_data_width;
688
689 switch (width) {
690 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
691 valid = (param == 8);
692 break;
693 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
694 valid = (param == 16);
695 break;
696 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
697 valid = (param == 8 || param == 16);
698 break;
699 }
700
701 if (!valid)
702 dwc2_set_param_phy_utmi_width(hsotg);
703 }
704
dwc2_check_param_power_down(struct dwc2_hsotg * hsotg)705 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
706 {
707 int param = hsotg->params.power_down;
708
709 switch (param) {
710 case DWC2_POWER_DOWN_PARAM_NONE:
711 break;
712 case DWC2_POWER_DOWN_PARAM_PARTIAL:
713 if (hsotg->hw_params.power_optimized)
714 break;
715 dev_dbg(hsotg->dev,
716 "Partial power down isn't supported by HW\n");
717 param = DWC2_POWER_DOWN_PARAM_NONE;
718 break;
719 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
720 if (hsotg->hw_params.hibernation)
721 break;
722 dev_dbg(hsotg->dev,
723 "Hibernation isn't supported by HW\n");
724 param = DWC2_POWER_DOWN_PARAM_NONE;
725 break;
726 default:
727 dev_err(hsotg->dev,
728 "%s: Invalid parameter power_down=%d\n",
729 __func__, param);
730 param = DWC2_POWER_DOWN_PARAM_NONE;
731 break;
732 }
733
734 hsotg->params.power_down = param;
735 }
736
dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg * hsotg)737 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
738 {
739 int fifo_count;
740 int fifo;
741 int min;
742 u32 total = 0;
743 u32 dptxfszn;
744
745 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
746 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
747
748 for (fifo = 1; fifo <= fifo_count; fifo++)
749 total += hsotg->params.g_tx_fifo_size[fifo];
750
751 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
752 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
753 __func__);
754 dwc2_set_param_tx_fifo_sizes(hsotg);
755 }
756
757 for (fifo = 1; fifo <= fifo_count; fifo++) {
758 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
759
760 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
761 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
762 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
763 __func__, fifo,
764 hsotg->params.g_tx_fifo_size[fifo]);
765 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
766 }
767 }
768 }
769
770 #define CHECK_RANGE(_param, _min, _max, _def) do { \
771 if ((int)(hsotg->params._param) < (_min) || \
772 (hsotg->params._param) > (_max)) { \
773 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
774 __func__, #_param, hsotg->params._param); \
775 hsotg->params._param = (_def); \
776 } \
777 } while (0)
778
779 #define CHECK_BOOL(_param, _check) do { \
780 if (hsotg->params._param && !(_check)) { \
781 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
782 __func__, #_param, hsotg->params._param); \
783 hsotg->params._param = false; \
784 } \
785 } while (0)
786
dwc2_check_params(struct dwc2_hsotg * hsotg)787 STATIC void dwc2_check_params(struct dwc2_hsotg *hsotg)
788 {
789 struct dwc2_hw_params *hw = &hsotg->hw_params;
790 struct dwc2_core_params *p = &hsotg->params;
791 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
792
793 dwc2_check_param_otg_cap(hsotg);
794 dwc2_check_param_phy_type(hsotg);
795 dwc2_check_param_speed(hsotg);
796 dwc2_check_param_phy_utmi_width(hsotg);
797 dwc2_check_param_power_down(hsotg);
798 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
799 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
800 CHECK_BOOL(i2c_enable, hw->i2c_enable);
801 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
802 CHECK_BOOL(acg_enable, hw->acg_enable);
803 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
804 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
805 CHECK_BOOL(lpm, hw->lpm_mode);
806 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
807 CHECK_BOOL(besl, hsotg->params.lpm);
808 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
809 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
810 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
811 CHECK_BOOL(service_interval, hw->service_interval_mode);
812 CHECK_RANGE(max_packet_count,
813 15, hw->max_packet_count,
814 hw->max_packet_count);
815 CHECK_RANGE(max_transfer_size,
816 2047, hw->max_transfer_size,
817 hw->max_transfer_size);
818
819 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
820 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
821 CHECK_BOOL(host_dma, dma_capable);
822 CHECK_BOOL(dma_desc_enable, p->host_dma);
823 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
824 CHECK_BOOL(host_ls_low_power_phy_clk,
825 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
826 CHECK_RANGE(host_channels,
827 1, hw->host_channels,
828 hw->host_channels);
829 CHECK_RANGE(host_rx_fifo_size,
830 16, hw->rx_fifo_size,
831 hw->rx_fifo_size);
832 CHECK_RANGE(host_nperio_tx_fifo_size,
833 16, hw->host_nperio_tx_fifo_size,
834 hw->host_nperio_tx_fifo_size);
835 CHECK_RANGE(host_perio_tx_fifo_size,
836 16, hw->host_perio_tx_fifo_size,
837 hw->host_perio_tx_fifo_size);
838 }
839
840 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
841 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
842 CHECK_BOOL(g_dma, dma_capable);
843 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
844 CHECK_RANGE(g_rx_fifo_size,
845 16, hw->rx_fifo_size,
846 hw->rx_fifo_size);
847 CHECK_RANGE(g_np_tx_fifo_size,
848 16, hw->dev_nperio_tx_fifo_size,
849 hw->dev_nperio_tx_fifo_size);
850 dwc2_check_param_tx_fifo_sizes(hsotg);
851 }
852 }
853
854 /*
855 * Gets host hardware parameters. Forces host mode if not currently in
856 * host mode. Should be called immediately after a core soft reset in
857 * order to get the reset values.
858 */
dwc2_get_host_hwparams(struct dwc2_hsotg * hsotg)859 STATIC void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
860 {
861 struct dwc2_hw_params *hw = &hsotg->hw_params;
862 u32 gnptxfsiz;
863 u32 hptxfsiz;
864
865 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
866 return;
867
868 dwc2_force_mode(hsotg, true);
869
870 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
871 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
872
873 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
874 FIFOSIZE_DEPTH_SHIFT;
875 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
876 FIFOSIZE_DEPTH_SHIFT;
877 }
878
879 /*
880 * Gets device hardware parameters. Forces device mode if not
881 * currently in device mode. Should be called immediately after a core
882 * soft reset in order to get the reset values.
883 */
dwc2_get_dev_hwparams(struct dwc2_hsotg * hsotg)884 STATIC void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
885 {
886 struct dwc2_hw_params *hw = &hsotg->hw_params;
887 u32 gnptxfsiz;
888 int fifo, fifo_count;
889
890 if (hsotg->dr_mode == USB_DR_MODE_HOST)
891 return;
892
893 dwc2_force_mode(hsotg, false);
894
895 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
896
897 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
898
899 for (fifo = 1; fifo <= fifo_count; fifo++) {
900 hw->g_tx_fifo_size[fifo] =
901 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
902 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
903 }
904
905 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
906 FIFOSIZE_DEPTH_SHIFT;
907 }
908
909 /**
910 * dwc2_get_hwparams() - During device initialization, read various hardware
911 * configuration registers and interpret the contents.
912 *
913 * @hsotg: Programming view of the DWC_otg controller
914 *
915 */
dwc2_get_hwparams(struct dwc2_hsotg * hsotg)916 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
917 {
918 struct dwc2_hw_params *hw = &hsotg->hw_params;
919 unsigned int width;
920 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
921 u32 grxfsiz;
922
923 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
924 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
925 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
926 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
927 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
928
929 /* hwcfg1 */
930 hw->dev_ep_dirs = hwcfg1;
931
932 /* hwcfg2 */
933 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
934 GHWCFG2_OP_MODE_SHIFT;
935 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
936 GHWCFG2_ARCHITECTURE_SHIFT;
937 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
938 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
939 GHWCFG2_NUM_HOST_CHAN_SHIFT);
940 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
941 GHWCFG2_HS_PHY_TYPE_SHIFT;
942 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
943 GHWCFG2_FS_PHY_TYPE_SHIFT;
944 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
945 GHWCFG2_NUM_DEV_EP_SHIFT;
946 hw->nperio_tx_q_depth =
947 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
948 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
949 hw->host_perio_tx_q_depth =
950 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
951 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
952 hw->dev_token_q_depth =
953 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
954 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
955
956 /* hwcfg3 */
957 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
958 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
959 hw->max_transfer_size = (1 << (width + 11)) - 1;
960 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
961 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
962 hw->max_packet_count = (1 << (width + 4)) - 1;
963 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
964 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
965 GHWCFG3_DFIFO_DEPTH_SHIFT;
966 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
967
968 /* hwcfg4 */
969 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
970 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
971 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
972 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
973 GHWCFG4_NUM_IN_EPS_SHIFT;
974 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
975 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
976 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
977 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
978 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
979 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
980 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
981 hw->service_interval_mode = !!(hwcfg4 &
982 GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
983
984 /* fifo sizes */
985 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
986 GRXFSIZ_DEPTH_SHIFT;
987 /*
988 * Host specific hardware parameters. Reading these parameters
989 * requires the controller to be in host mode. The mode will
990 * be forced, if necessary, to read these values.
991 */
992 dwc2_get_host_hwparams(hsotg);
993 dwc2_get_dev_hwparams(hsotg);
994
995 return 0;
996 }
997
998 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
999
dwc2_init_params(struct dwc2_hsotg * hsotg)1000 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1001 {
1002 #if 0
1003 const struct of_device_id *match;
1004 set_params_cb set_params;
1005 #endif
1006
1007 dwc2_set_default_params(hsotg);
1008 dwc2_set_dwctwo_params(hsotg);
1009 #if 0
1010 dwc2_get_device_properties(hsotg);
1011
1012 match = of_match_device(dwc2_of_match_table, hsotg->dev);
1013 if (match && match->data) {
1014 set_params = match->data;
1015 set_params(hsotg);
1016 } else {
1017 const struct acpi_device_id *amatch;
1018
1019 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev);
1020 if (amatch && amatch->driver_data) {
1021 set_params = (set_params_cb)amatch->driver_data;
1022 set_params(hsotg);
1023 }
1024 }
1025 #endif
1026
1027 dwc2_check_params(hsotg);
1028
1029 return 0;
1030 }
1031