1 /* $OpenBSD: gdt_pci.c,v 1.29 2024/09/01 03:08:56 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver would not have written if it was not for the hardware donations 29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/queue.h> 36 37 #include <machine/bus.h> 38 39 #include <scsi/scsi_all.h> 40 #include <scsi/scsiconf.h> 41 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/ic/gdtreg.h> 47 #include <dev/ic/gdtvar.h> 48 49 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 50 #define GDT_PCI_PRODUCT_FC 0x200 51 52 #define GDT_DEVICE_ID_MIN 0x100 53 #define GDT_DEVICE_ID_MAX 0x2ff 54 #define GDT_DEVICE_ID_NEWRX 0x300 55 #define GDT_DEVICE_ID_NEWRX2 0x301 56 57 /* Mapping registers for various areas */ 58 #define GDT_PCI_DPMEM 0x10 59 #define GDT_PCINEW_IOMEM 0x10 60 #define GDT_PCINEW_IO 0x14 61 #define GDT_PCINEW_DPMEM 0x18 62 63 /* PCI SRAM structure */ 64 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 65 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 66 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 67 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 68 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 69 #define GDT_SRAM_SZ 0x40 70 71 /* DPRAM PCI controllers */ 72 #define GDT_DPR_IF 0x00 /* interface area */ 73 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 74 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 75 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 76 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 77 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 78 #define GDT_DPRAM_SZ 0x1000 79 80 /* PLX register structure (new PCI controllers) */ 81 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 82 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 83 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 84 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 85 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 86 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 87 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 88 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 89 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 90 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 91 #define GDT_PLX_SZ 0x80 92 93 /* DPRAM new PCI controllers */ 94 #define GDT_IC 0x00 /* interface */ 95 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 96 /* SRAM structure */ 97 #define GDT_PCINEW_SZ 0x4000 98 99 /* i960 register structure (PCI MPR controllers) */ 100 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 101 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 102 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 103 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 104 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 105 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 106 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 107 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 108 #define GDT_I960_SZ 0x1000 109 110 /* DPRAM PCI MPR controllers */ 111 #define GDT_I960R 0x00 /* 4KB i960 registers */ 112 #define GDT_MPR_IC GDT_I960_SZ 113 /* interface area */ 114 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 115 /* SRAM structure */ 116 #define GDT_MPR_SZ 0x4000 117 118 int gdt_pci_probe(struct device *, void *, void *); 119 void gdt_pci_attach(struct device *, struct device *, void *); 120 void gdt_pci_enable_intr(struct gdt_softc *); 121 122 void gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 123 u_int8_t gdt_pci_get_status(struct gdt_softc *); 124 void gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *); 125 void gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *); 126 void gdt_pci_set_sema0(struct gdt_softc *); 127 int gdt_pci_test_busy(struct gdt_softc *); 128 129 void gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 130 u_int8_t gdt_pcinew_get_status(struct gdt_softc *); 131 void gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *); 132 void gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *); 133 void gdt_pcinew_set_sema0(struct gdt_softc *); 134 int gdt_pcinew_test_busy(struct gdt_softc *); 135 136 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 137 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 138 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 139 void gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *); 140 void gdt_mpr_set_sema0(struct gdt_softc *); 141 int gdt_mpr_test_busy(struct gdt_softc *); 142 143 const struct cfattach gdt_pci_ca = { 144 sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach 145 }; 146 147 int 148 gdt_pci_probe(struct device *parent, void *match, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 152 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 153 ((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN && 154 PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) || 155 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX || 156 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2)) 157 return (1); 158 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 159 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 || 160 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2)) 161 return (1); 162 return (0); 163 } 164 165 void 166 gdt_pci_attach(struct device *parent, struct device *self, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 struct gdt_softc *sc = (void *)self; 170 bus_space_tag_t dpmemt, iomemt, iot; 171 bus_space_handle_t dpmemh, iomemh, ioh; 172 bus_addr_t dpmembase, iomembase, iobase; 173 bus_size_t dpmemsize, iomemsize, iosize; 174 u_int16_t prod; 175 u_int32_t status = 0; 176 #define DPMEM_MAPPED 1 177 #define IOMEM_MAPPED 2 178 #define IO_MAPPED 4 179 #define INTR_ESTABLISHED 8 180 int retries; 181 u_int8_t protocol; 182 pci_intr_handle_t ih; 183 const char *intrstr; 184 185 printf(": "); 186 187 sc->sc_class = 0; 188 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) { 189 prod = PCI_PRODUCT(pa->pa_id); 190 switch (prod) { 191 case PCI_PRODUCT_VORTEX_GDT_60X0: 192 case PCI_PRODUCT_VORTEX_GDT_6000B: 193 sc->sc_class = GDT_PCI; 194 break; 195 196 case PCI_PRODUCT_VORTEX_GDT_6X10: 197 case PCI_PRODUCT_VORTEX_GDT_6X20: 198 case PCI_PRODUCT_VORTEX_GDT_6530: 199 case PCI_PRODUCT_VORTEX_GDT_6550: 200 case PCI_PRODUCT_VORTEX_GDT_6X17: 201 case PCI_PRODUCT_VORTEX_GDT_6X27: 202 case PCI_PRODUCT_VORTEX_GDT_6537: 203 case PCI_PRODUCT_VORTEX_GDT_6557: 204 case PCI_PRODUCT_VORTEX_GDT_6X15: 205 case PCI_PRODUCT_VORTEX_GDT_6X25: 206 case PCI_PRODUCT_VORTEX_GDT_6535: 207 case PCI_PRODUCT_VORTEX_GDT_6555: 208 sc->sc_class = GDT_PCINEW; 209 break; 210 211 case PCI_PRODUCT_VORTEX_GDT_6X17RP: 212 case PCI_PRODUCT_VORTEX_GDT_6X27RP: 213 case PCI_PRODUCT_VORTEX_GDT_6537RP: 214 case PCI_PRODUCT_VORTEX_GDT_6557RP: 215 case PCI_PRODUCT_VORTEX_GDT_6X11RP: 216 case PCI_PRODUCT_VORTEX_GDT_6X21RP: 217 case PCI_PRODUCT_VORTEX_GDT_6X17RD: 218 case PCI_PRODUCT_VORTEX_GDT_6X27RD: 219 case PCI_PRODUCT_VORTEX_GDT_6537RD: 220 case PCI_PRODUCT_VORTEX_GDT_6557RD: 221 case PCI_PRODUCT_VORTEX_GDT_6X11RD: 222 case PCI_PRODUCT_VORTEX_GDT_6X21RD: 223 case PCI_PRODUCT_VORTEX_GDT_6X18RD: 224 case PCI_PRODUCT_VORTEX_GDT_6X28RD: 225 case PCI_PRODUCT_VORTEX_GDT_6X38RD: 226 case PCI_PRODUCT_VORTEX_GDT_6X58RD: 227 case PCI_PRODUCT_VORTEX_GDT_6518RS: 228 case PCI_PRODUCT_VORTEX_GDT_7X18RN: 229 case PCI_PRODUCT_VORTEX_GDT_7X28RN: 230 case PCI_PRODUCT_VORTEX_GDT_7X38RN: 231 case PCI_PRODUCT_VORTEX_GDT_7X58RN: 232 case PCI_PRODUCT_VORTEX_GDT_6X19RD: 233 case PCI_PRODUCT_VORTEX_GDT_6X29RD: 234 case PCI_PRODUCT_VORTEX_GDT_7X19RN: 235 case PCI_PRODUCT_VORTEX_GDT_7X29RN: 236 case PCI_PRODUCT_VORTEX_GDT_7X43RN: 237 sc->sc_class = GDT_MPR; 238 } 239 240 /* If we don't recognize it, determine class heuristically. */ 241 if (sc->sc_class == 0) 242 sc->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR; 243 244 if (prod >= GDT_PCI_PRODUCT_FC) 245 sc->sc_class |= GDT_FC; 246 247 } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 248 sc->sc_class = GDT_MPR; 249 } 250 251 if (pci_mapreg_map(pa, 252 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM, 253 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 254 &dpmemh, &dpmembase, &dpmemsize, 0)) { 255 if (pci_mapreg_map(pa, 256 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : 257 GDT_PCI_DPMEM, 258 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 259 &dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) { 260 printf("cannot map DPMEM\n"); 261 goto bail_out; 262 } 263 } 264 status |= DPMEM_MAPPED; 265 sc->sc_dpmemt = dpmemt; 266 sc->sc_dpmemh = dpmemh; 267 sc->sc_dpmembase = dpmembase; 268 sc->sc_dmat = pa->pa_dmat; 269 270 /* 271 * The GDT_PCINEW series also has two other regions to map. 272 */ 273 if (GDT_CLASS(sc) == GDT_PCINEW) { 274 if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 275 0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) { 276 printf("can't map memory mapped i/o ports\n"); 277 goto bail_out; 278 } 279 status |= IOMEM_MAPPED; 280 281 if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 282 &iot, &ioh, &iobase, &iosize, 0)) { 283 printf("can't map i/o space\n"); 284 goto bail_out; 285 } 286 status |= IO_MAPPED; 287 sc->sc_iot = iot; 288 sc->sc_ioh = ioh; 289 sc->sc_iobase = iobase; 290 } 291 292 switch (GDT_CLASS(sc)) { 293 case GDT_PCI: 294 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 295 GDT_DPR_IF_SZ >> 2); 296 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 297 printf("can't write to DPMEM\n"); 298 goto bail_out; 299 } 300 301 #if 0 302 /* disable board interrupts, deinit services */ 303 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 304 gdth_writeb(0x00, &dp6_ptr->io.irqen); 305 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status); 306 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 307 308 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 309 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 310 gdth_writeb(0, &dp6_ptr->io.event); 311 retries = INIT_RETRIES; 312 gdth_delay(20); 313 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 314 if (--retries == 0) { 315 printk("initialization error (DEINIT failed)\n"); 316 gdth_munmap(ha->brd); 317 return 0; 318 } 319 gdth_delay(1); 320 } 321 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]); 322 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 323 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 324 if (prot_ver != PROTOCOL_VERSION) { 325 printk("illegal protocol version\n"); 326 gdth_munmap(ha->brd); 327 return 0; 328 } 329 330 ha->type = GDT_PCI; 331 ha->ic_all_size = sizeof(dp6_ptr->u); 332 333 /* special command to controller BIOS */ 334 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 335 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 336 gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 337 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 338 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 339 gdth_writeb(0, &dp6_ptr->io.event); 340 retries = INIT_RETRIES; 341 gdth_delay(20); 342 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 343 if (--retries == 0) { 344 printk("initialization error\n"); 345 gdth_munmap(ha->brd); 346 return 0; 347 } 348 gdth_delay(1); 349 } 350 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 351 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 352 #endif 353 354 sc->sc_ic_all_size = GDT_DPRAM_SZ; 355 356 sc->sc_copy_cmd = gdt_pci_copy_cmd; 357 sc->sc_get_status = gdt_pci_get_status; 358 sc->sc_intr = gdt_pci_intr; 359 sc->sc_release_event = gdt_pci_release_event; 360 sc->sc_set_sema0 = gdt_pci_set_sema0; 361 sc->sc_test_busy = gdt_pci_test_busy; 362 363 break; 364 365 case GDT_PCINEW: 366 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 367 GDT_DPR_IF_SZ >> 2); 368 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 369 printf("cannot write to DPMEM\n"); 370 goto bail_out; 371 } 372 373 #if 0 374 /* disable board interrupts, deinit services */ 375 outb(0x00,PTR2USHORT(&ha->plx->control1)); 376 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 377 378 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 379 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 380 381 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 382 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 383 384 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 385 386 retries = INIT_RETRIES; 387 gdth_delay(20); 388 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 389 if (--retries == 0) { 390 printk("initialization error (DEINIT failed)\n"); 391 gdth_munmap(ha->brd); 392 return 0; 393 } 394 gdth_delay(1); 395 } 396 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]); 397 gdth_writeb(0, &dp6c_ptr->u.ic.Status); 398 if (prot_ver != PROTOCOL_VERSION) { 399 printk("illegal protocol version\n"); 400 gdth_munmap(ha->brd); 401 return 0; 402 } 403 404 ha->type = GDT_PCINEW; 405 ha->ic_all_size = sizeof(dp6c_ptr->u); 406 407 /* special command to controller BIOS */ 408 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 409 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 410 gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 411 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 412 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 413 414 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 415 416 retries = INIT_RETRIES; 417 gdth_delay(20); 418 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 419 if (--retries == 0) { 420 printk("initialization error\n"); 421 gdth_munmap(ha->brd); 422 return 0; 423 } 424 gdth_delay(1); 425 } 426 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status); 427 #endif 428 429 sc->sc_ic_all_size = GDT_PCINEW_SZ; 430 431 sc->sc_copy_cmd = gdt_pcinew_copy_cmd; 432 sc->sc_get_status = gdt_pcinew_get_status; 433 sc->sc_intr = gdt_pcinew_intr; 434 sc->sc_release_event = gdt_pcinew_release_event; 435 sc->sc_set_sema0 = gdt_pcinew_set_sema0; 436 sc->sc_test_busy = gdt_pcinew_test_busy; 437 438 break; 439 440 case GDT_MPR: 441 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC); 442 if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) != 443 GDT_MPR_MAGIC) { 444 printf("cannot access DPMEM at 0x%lx (shadowed?)\n", 445 dpmembase); 446 goto bail_out; 447 } 448 449 /* 450 * XXX Here the Linux driver has a weird remapping logic I 451 * don't understand. My controller does not need it, and I 452 * cannot see what purpose it serves, therefore I did not 453 * do anything similar. 454 */ 455 456 bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0, 457 GDT_DPR_IF_SZ >> 2); 458 459 /* Disable everything */ 460 bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN, 461 bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4); 462 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff); 463 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 464 0); 465 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 466 0); 467 468 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 469 dpmembase); 470 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 471 0xff); 472 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 473 474 DELAY(20); 475 retries = GDT_RETRIES; 476 while (bus_space_read_1(dpmemt, dpmemh, 477 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 478 if (--retries == 0) { 479 printf("DEINIT failed (status 0x%x)\n", 480 bus_space_read_1(dpmemt, dpmemh, 481 GDT_MPR_IC + GDT_S_STATUS)); 482 goto bail_out; 483 } 484 DELAY(1); 485 } 486 487 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 488 GDT_MPR_IC + GDT_S_INFO); 489 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 490 0); 491 if (protocol != GDT_PROTOCOL_VERSION) { 492 printf("unsupported protocol %d\n", protocol); 493 goto bail_out; 494 } 495 496 /* special command to controller BIOS */ 497 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0); 498 bus_space_write_4(dpmemt, dpmemh, 499 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0); 500 bus_space_write_4(dpmemt, dpmemh, 501 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1); 502 bus_space_write_4(dpmemt, dpmemh, 503 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0); 504 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 505 0xfe); 506 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 507 508 DELAY(20); 509 retries = GDT_RETRIES; 510 while (bus_space_read_1(dpmemt, dpmemh, 511 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 512 if (--retries == 0) { 513 printf("initialization error\n"); 514 goto bail_out; 515 } 516 DELAY(1); 517 } 518 519 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 520 0); 521 522 sc->sc_ic_all_size = GDT_MPR_SZ; 523 524 sc->sc_copy_cmd = gdt_mpr_copy_cmd; 525 sc->sc_get_status = gdt_mpr_get_status; 526 sc->sc_intr = gdt_mpr_intr; 527 sc->sc_release_event = gdt_mpr_release_event; 528 sc->sc_set_sema0 = gdt_mpr_set_sema0; 529 sc->sc_test_busy = gdt_mpr_test_busy; 530 } 531 532 if (pci_intr_map(pa, &ih)) { 533 printf("couldn't map interrupt\n"); 534 goto bail_out; 535 } 536 intrstr = pci_intr_string(pa->pa_pc, ih); 537 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, sc, 538 sc->sc_dev.dv_xname); 539 if (sc->sc_ih == NULL) { 540 printf("couldn't establish interrupt"); 541 if (intrstr != NULL) 542 printf(" at %s", intrstr); 543 printf("\n"); 544 goto bail_out; 545 } 546 status |= INTR_ESTABLISHED; 547 if (intrstr != NULL) 548 printf("%s ", intrstr); 549 550 if (gdt_attach(sc)) 551 goto bail_out; 552 553 gdt_pci_enable_intr(sc); 554 555 return; 556 557 bail_out: 558 if (status & DPMEM_MAPPED) 559 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 560 if (status & IOMEM_MAPPED) 561 bus_space_unmap(iomemt, iomemh, iomembase); 562 if (status & IO_MAPPED) 563 bus_space_unmap(iot, ioh, iosize); 564 if (status & INTR_ESTABLISHED) 565 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 566 return; 567 } 568 569 /* Enable interrupts */ 570 void 571 gdt_pci_enable_intr(struct gdt_softc *sc) 572 { 573 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", sc)); 574 575 switch(GDT_CLASS(sc)) { 576 case GDT_PCI: 577 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQDEL, 578 1); 579 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 580 GDT_CMD_INDEX, 0); 581 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQEN, 582 1); 583 break; 584 585 case GDT_PCINEW: 586 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_EDOOR_REG, 587 0xff); 588 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_CONTROL1, 3); 589 break; 590 591 case GDT_MPR: 592 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 593 GDT_MPR_EDOOR, 0xff); 594 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_EDOOR_EN, 595 bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 596 GDT_EDOOR_EN) & ~4); 597 break; 598 } 599 } 600 601 /* 602 * "old" PCI controller-specific functions 603 */ 604 605 void 606 gdt_pci_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 607 { 608 /* XXX Not yet implemented */ 609 } 610 611 u_int8_t 612 gdt_pci_get_status(struct gdt_softc *sc) 613 { 614 /* XXX Not yet implemented */ 615 return (0); 616 } 617 618 void 619 gdt_pci_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 620 { 621 /* XXX Not yet implemented */ 622 } 623 624 void 625 gdt_pci_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 626 { 627 /* XXX Not yet implemented */ 628 } 629 630 void 631 gdt_pci_set_sema0(struct gdt_softc *sc) 632 { 633 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_SEMA0, 1); 634 } 635 636 int 637 gdt_pci_test_busy(struct gdt_softc *sc) 638 { 639 /* XXX Not yet implemented */ 640 return (0); 641 } 642 643 /* 644 * "new" PCI controller-specific functions 645 */ 646 647 void 648 gdt_pcinew_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 649 { 650 /* XXX Not yet implemented */ 651 } 652 653 u_int8_t 654 gdt_pcinew_get_status(struct gdt_softc *sc) 655 { 656 /* XXX Not yet implemented */ 657 return (0); 658 } 659 660 void 661 gdt_pcinew_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 662 { 663 /* XXX Not yet implemented */ 664 } 665 666 void 667 gdt_pcinew_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 668 { 669 /* XXX Not yet implemented */ 670 } 671 672 void 673 gdt_pcinew_set_sema0(struct gdt_softc *sc) 674 { 675 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_SEMA0_REG, 1); 676 } 677 678 int 679 gdt_pcinew_test_busy(struct gdt_softc *sc) 680 { 681 /* XXX Not yet implemented */ 682 return (0); 683 } 684 685 /* 686 * MPR PCI controller-specific functions 687 */ 688 689 void 690 gdt_mpr_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 691 { 692 u_int16_t cp_count = roundup(sc->sc_cmd_len, sizeof (u_int32_t)); 693 u_int16_t dp_offset = sc->sc_cmd_off; 694 u_int16_t cmd_no = sc->sc_cmd_cnt++; 695 696 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", sc)); 697 698 sc->sc_cmd_off += cp_count; 699 700 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 701 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 702 GDT_DPMEM_COMMAND_OFFSET + dp_offset); 703 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 704 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 705 ccb->gc_service); 706 bus_space_write_raw_region_4(sc->sc_dpmemt, sc->sc_dpmemh, 707 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, sc->sc_cmd, cp_count); 708 } 709 710 u_int8_t 711 gdt_mpr_get_status(struct gdt_softc *sc) 712 { 713 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", sc)); 714 715 return bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR); 716 } 717 718 void 719 gdt_mpr_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 720 { 721 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", sc)); 722 723 if (ctx->istatus & 0x80) { /* error flag */ 724 ctx->istatus &= ~0x80; 725 ctx->cmd_status = bus_space_read_2(sc->sc_dpmemt, 726 sc->sc_dpmemh, GDT_MPR_STATUS); 727 if (ctx->istatus == GDT_ASYNCINDEX) { 728 ctx->service = bus_space_read_2(sc->sc_dpmemt, 729 sc->sc_dpmemh, GDT_MPR_SERVICE); 730 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, 731 sc->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t)); 732 } 733 } else /* no error */ 734 ctx->cmd_status = GDT_S_OK; 735 736 ctx->info = 737 bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_INFO); 738 739 if (gdt_polling) /* init. -> more info */ 740 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, 741 GDT_MPR_INFO + sizeof (u_int32_t)); 742 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 743 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA1, 0); 744 } 745 746 void 747 gdt_mpr_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 748 { 749 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", sc)); 750 751 if (gdt_dec16(sc->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT) 752 ccb->gc_service |= 0x80; 753 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_LDOOR, 1); 754 } 755 756 void 757 gdt_mpr_set_sema0(struct gdt_softc *sc) 758 { 759 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", sc)); 760 761 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA0, 1); 762 } 763 764 int 765 gdt_mpr_test_busy(struct gdt_softc *sc) 766 { 767 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", sc)); 768 769 return (bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 770 GDT_MPR_SEMA0) & 1); 771 } 772