1 /* $OpenBSD: pci.h,v 1.18 2024/08/28 04:55:45 jsg Exp $ */ 2 /* 3 * Copyright (c) 2015 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _LINUX_PCI_H_ 19 #define _LINUX_PCI_H_ 20 21 #include <sys/types.h> 22 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */ 23 #include <sys/param.h> 24 #include <machine/cpu.h> 25 26 #include <dev/pci/pcireg.h> 27 #include <dev/pci/pcivar.h> 28 #include <dev/pci/pcidevs.h> 29 #include <uvm/uvm_extern.h> 30 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/kobject.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/mod_devicetable.h> 36 #include <linux/device.h> 37 38 struct pci_dev; 39 40 struct pci_bus { 41 pci_chipset_tag_t pc; 42 unsigned char number; 43 int domain_nr; 44 pcitag_t *bridgetag; 45 struct pci_dev *self; 46 }; 47 48 struct pci_acpi { 49 struct aml_node *node; 50 }; 51 52 struct pci_dev { 53 struct pci_bus _bus; 54 struct pci_bus *bus; 55 56 unsigned int devfn; 57 uint16_t vendor; 58 uint16_t device; 59 uint16_t subsystem_vendor; 60 uint16_t subsystem_device; 61 uint8_t revision; 62 uint32_t class; /* class:subclass:interface */ 63 64 pci_chipset_tag_t pc; 65 pcitag_t tag; 66 struct pci_softc *pci; 67 68 int irq; 69 int msi_enabled; 70 uint8_t no_64bit_msi; 71 uint8_t ltr_path; 72 73 struct pci_acpi dev; 74 struct device *_dev; 75 }; 76 #define PCI_ANY_ID (uint16_t) (~0U) 77 78 #define PCI_DEVICE(v, p) \ 79 .vendor = (v), \ 80 .device = (p), \ 81 .subvendor = PCI_ANY_ID, \ 82 .subdevice = PCI_ANY_ID 83 84 #ifndef PCI_MEM_START 85 #define PCI_MEM_START 0 86 #endif 87 88 #ifndef PCI_MEM_END 89 #define PCI_MEM_END 0xffffffff 90 #endif 91 92 #ifndef PCI_MEM64_END 93 #define PCI_MEM64_END 0xffffffffffffffff 94 #endif 95 96 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 97 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 98 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 99 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 100 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 101 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 102 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 103 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 104 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 105 106 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY 107 108 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 109 #define PCI_SUBDEVICE_ID_QEMU 0x1100 110 111 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func)) 112 #define PCI_SLOT(devfn) ((devfn) >> 3) 113 #define PCI_FUNC(devfn) ((devfn) & 0x7) 114 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 115 116 #define pci_dev_put(x) 117 118 #define PCI_EXP_DEVSTA 0x0a 119 #define PCI_EXP_DEVSTA_TRPND 0x0020 120 #define PCI_EXP_LNKCAP 0x0c 121 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 122 #define PCI_EXP_LNKCTL 0x10 123 #define PCI_EXP_LNKCTL_HAWD 0x0200 124 #define PCI_EXP_LNKCTL2 0x30 125 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 126 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 127 #define PCI_EXP_LNKCTL2_TLS PCI_PCIE_LCSR2_TLS 128 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCI_PCIE_LCSR2_TLS_2_5 129 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCI_PCIE_LCSR2_TLS_5 130 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCI_PCIE_LCSR2_TLS_8 131 132 #define PCI_COMMAND PCI_COMMAND_STATUS_REG 133 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE 134 135 static inline int 136 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) 137 { 138 *val = pci_conf_read(pdev->pc, pdev->tag, reg); 139 return 0; 140 } 141 142 static inline int 143 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) 144 { 145 uint32_t v; 146 147 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 148 *val = (v >> ((reg & 0x2) * 8)); 149 return 0; 150 } 151 152 static inline int 153 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) 154 { 155 uint32_t v; 156 157 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 158 *val = (v >> ((reg & 0x3) * 8)); 159 return 0; 160 } 161 162 static inline int 163 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) 164 { 165 pci_conf_write(pdev->pc, pdev->tag, reg, val); 166 return 0; 167 } 168 169 static inline int 170 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) 171 { 172 uint32_t v; 173 174 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 175 v &= ~(0xffff << ((reg & 0x2) * 8)); 176 v |= (val << ((reg & 0x2) * 8)); 177 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); 178 return 0; 179 } 180 181 static inline int 182 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) 183 { 184 uint32_t v; 185 186 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 187 v &= ~(0xff << ((reg & 0x3) * 8)); 188 v |= (val << ((reg & 0x3) * 8)); 189 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v); 190 return 0; 191 } 192 193 static inline int 194 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 195 int reg, u16 *val) 196 { 197 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 198 PCI_SLOT(devfn), PCI_FUNC(devfn)); 199 uint32_t v; 200 201 v = pci_conf_read(bus->pc, tag, (reg & ~0x2)); 202 *val = (v >> ((reg & 0x2) * 8)); 203 return 0; 204 } 205 206 static inline int 207 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 208 int reg, u8 *val) 209 { 210 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 211 PCI_SLOT(devfn), PCI_FUNC(devfn)); 212 uint32_t v; 213 214 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 215 *val = (v >> ((reg & 0x3) * 8)); 216 return 0; 217 } 218 219 static inline int 220 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 221 int reg, u8 val) 222 { 223 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 224 PCI_SLOT(devfn), PCI_FUNC(devfn)); 225 uint32_t v; 226 227 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 228 v &= ~(0xff << ((reg & 0x3) * 8)); 229 v |= (val << ((reg & 0x3) * 8)); 230 pci_conf_write(bus->pc, tag, (reg & ~0x3), v); 231 return 0; 232 } 233 234 static inline int 235 pci_pcie_cap(struct pci_dev *pdev) 236 { 237 int pos; 238 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 239 &pos, NULL)) 240 return -EINVAL; 241 return pos; 242 } 243 244 bool pcie_aspm_enabled(struct pci_dev *); 245 246 static inline bool 247 pci_is_pcie(struct pci_dev *pdev) 248 { 249 return (pci_pcie_cap(pdev) > 0); 250 } 251 252 static inline bool 253 pci_is_root_bus(struct pci_bus *pbus) 254 { 255 return (pbus->bridgetag == NULL); 256 } 257 258 static inline struct pci_dev * 259 pci_upstream_bridge(struct pci_dev *pdev) 260 { 261 if (pci_is_root_bus(pdev->bus)) 262 return NULL; 263 return pdev->bus->self; 264 } 265 266 /* XXX check for ACPI _PR3 */ 267 static inline bool 268 pci_pr3_present(struct pci_dev *pdev) 269 { 270 return false; 271 } 272 273 static inline int 274 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val) 275 { 276 int pos; 277 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 278 &pos, NULL)) { 279 *val = 0; 280 return -EINVAL; 281 } 282 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off); 283 return 0; 284 } 285 286 static inline int 287 pcie_capability_read_word(struct pci_dev *pdev, int off, u16 *val) 288 { 289 int pos; 290 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 291 &pos, NULL)) { 292 *val = 0; 293 return -EINVAL; 294 } 295 pci_read_config_word(pdev, pos + off, val); 296 return 0; 297 } 298 299 static inline int 300 pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val) 301 { 302 int pos; 303 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 304 &pos, NULL)) 305 return -EINVAL; 306 pci_write_config_word(pdev, pos + off, val); 307 return 0; 308 } 309 310 static inline int 311 pcie_capability_set_word(struct pci_dev *pdev, int off, u16 val) 312 { 313 u16 r; 314 pcie_capability_read_word(pdev, off, &r); 315 r |= val; 316 pcie_capability_write_word(pdev, off, r); 317 return 0; 318 } 319 320 static inline int 321 pcie_capability_clear_and_set_word(struct pci_dev *pdev, int off, u16 c, u16 s) 322 { 323 u16 r; 324 pcie_capability_read_word(pdev, off, &r); 325 r &= ~c; 326 r |= s; 327 pcie_capability_write_word(pdev, off, r); 328 return 0; 329 } 330 331 static inline int 332 pcie_get_readrq(struct pci_dev *pdev) 333 { 334 uint16_t val; 335 336 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 337 338 return 128 << ((val & PCI_PCIE_DCSR_MPS) >> 12); 339 } 340 341 static inline int 342 pcie_set_readrq(struct pci_dev *pdev, int rrq) 343 { 344 uint16_t val; 345 346 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 347 val &= ~PCI_PCIE_DCSR_MPS; 348 val |= (ffs(rrq) - 8) << 12; 349 return pcie_capability_write_word(pdev, PCI_PCIE_DCSR, val); 350 } 351 352 static inline void 353 pci_set_master(struct pci_dev *pdev) 354 { 355 } 356 357 static inline void 358 pci_clear_master(struct pci_dev *pdev) 359 { 360 } 361 362 static inline void 363 pci_save_state(struct pci_dev *pdev) 364 { 365 } 366 367 static inline void 368 pci_restore_state(struct pci_dev *pdev) 369 { 370 } 371 372 static inline int 373 pci_enable_msi(struct pci_dev *pdev) 374 { 375 return 0; 376 } 377 378 static inline void 379 pci_disable_msi(struct pci_dev *pdev) 380 { 381 } 382 383 typedef enum { 384 PCI_D0, 385 PCI_D1, 386 PCI_D2, 387 PCI_D3hot, 388 PCI_D3cold 389 } pci_power_t; 390 391 enum pci_bus_speed { 392 PCIE_SPEED_2_5GT, 393 PCIE_SPEED_5_0GT, 394 PCIE_SPEED_8_0GT, 395 PCIE_SPEED_16_0GT, 396 PCIE_SPEED_32_0GT, 397 PCIE_SPEED_64_0GT, 398 PCI_SPEED_UNKNOWN 399 }; 400 401 enum pcie_link_width { 402 PCIE_LNK_X1 = 1, 403 PCIE_LNK_X2 = 2, 404 PCIE_LNK_X4 = 4, 405 PCIE_LNK_X8 = 8, 406 PCIE_LNK_X12 = 12, 407 PCIE_LNK_X16 = 16, 408 PCIE_LNK_X32 = 32, 409 PCIE_LNK_WIDTH_UNKNOWN = 0xff 410 }; 411 412 typedef unsigned int pci_ers_result_t; 413 typedef unsigned int pci_channel_state_t; 414 415 #define PCI_ERS_RESULT_DISCONNECT 0 416 #define PCI_ERS_RESULT_RECOVERED 1 417 418 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *); 419 enum pcie_link_width pcie_get_width_cap(struct pci_dev *); 420 int pci_resize_resource(struct pci_dev *, int, int); 421 422 static inline void 423 pcie_bandwidth_available(struct pci_dev *pdev, struct pci_dev **ldev, 424 enum pci_bus_speed *speed, enum pcie_link_width *width) 425 { 426 struct pci_dev *bdev = pdev->bus->self; 427 if (bdev == NULL) 428 return; 429 430 if (speed) 431 *speed = pcie_get_speed_cap(bdev); 432 if (width) 433 *width = pcie_get_width_cap(bdev); 434 } 435 436 static inline int 437 pci_enable_device(struct pci_dev *pdev) 438 { 439 return 0; 440 } 441 442 static inline void 443 pci_disable_device(struct pci_dev *pdev) 444 { 445 } 446 447 static inline int 448 pci_wait_for_pending_transaction(struct pci_dev *pdev) 449 { 450 return 0; 451 } 452 453 static inline bool 454 pci_is_thunderbolt_attached(struct pci_dev *pdev) 455 { 456 return false; 457 } 458 459 static inline void 460 pci_set_drvdata(struct pci_dev *pdev, void *data) 461 { 462 dev_set_drvdata(pdev->_dev, data); 463 } 464 465 static inline void * 466 pci_get_drvdata(struct pci_dev *pdev) 467 { 468 return dev_get_drvdata(pdev->_dev); 469 } 470 471 static inline int 472 pci_domain_nr(struct pci_bus *pbus) 473 { 474 return pbus->domain_nr; 475 } 476 477 static inline int 478 pci_irq_vector(struct pci_dev *pdev, unsigned int num) 479 { 480 return pdev->irq; 481 } 482 483 static inline void 484 pci_free_irq_vectors(struct pci_dev *pdev) 485 { 486 } 487 488 static inline int 489 pci_set_power_state(struct pci_dev *dev, int state) 490 { 491 return 0; 492 } 493 494 struct pci_driver; 495 496 static inline int 497 pci_register_driver(struct pci_driver *pci_drv) 498 { 499 return 0; 500 } 501 502 static inline void 503 pci_unregister_driver(void *d) 504 { 505 } 506 507 static inline u16 508 pci_dev_id(struct pci_dev *dev) 509 { 510 return dev->devfn | (dev->bus->number << 8); 511 } 512 513 static inline const struct pci_device_id * 514 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 515 { 516 int i = 0; 517 518 for (i = 0; ids[i].vendor != 0; i++) { 519 if ((ids[i].vendor == pdev->vendor) && 520 (ids[i].device == pdev->device || 521 ids[i].device == PCI_ANY_ID) && 522 (ids[i].subvendor == PCI_ANY_ID) && 523 (ids[i].subdevice == PCI_ANY_ID)) 524 return &ids[i]; 525 } 526 return NULL; 527 } 528 529 #define PCI_CLASS_DISPLAY_VGA \ 530 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA) 531 #define PCI_CLASS_DISPLAY_OTHER \ 532 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC) 533 #define PCI_CLASS_ACCELERATOR_PROCESSING \ 534 (PCI_CLASS_ACCELERATOR << 8) 535 536 static inline int 537 pci_device_is_present(struct pci_dev *pdev) 538 { 539 return 1; 540 } 541 542 #endif /* _LINUX_PCI_H_ */ 543