1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 static u32 edid_extract_panel_id(struct edid *edid) 48 { 49 return (u32)edid->mfg_id[0] << 24 | 50 (u32)edid->mfg_id[1] << 16 | 51 (u32)EDID_PRODUCT_ID(edid); 52 } 53 54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 55 { 56 uint32_t panel_id = edid_extract_panel_id(edid); 57 58 switch (panel_id) { 59 /* Workaround for some monitors which does not work well with FAMS */ 60 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 63 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 64 edid_caps->panel_patch.disable_fams = true; 65 break; 66 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ 67 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB): 68 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B): 69 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A): 70 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1): 71 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); 72 edid_caps->panel_patch.remove_sink_ext_caps = true; 73 break; 74 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154): 75 DRM_DEBUG_DRIVER("Disabling VSC on monitor with panel id %X\n", panel_id); 76 edid_caps->panel_patch.disable_colorimetry = true; 77 break; 78 default: 79 return; 80 } 81 } 82 83 /** 84 * dm_helpers_parse_edid_caps() - Parse edid caps 85 * 86 * @link: current detected link 87 * @edid: [in] pointer to edid 88 * @edid_caps: [in] pointer to edid caps 89 * 90 * Return: void 91 */ 92 enum dc_edid_status dm_helpers_parse_edid_caps( 93 struct dc_link *link, 94 const struct dc_edid *edid, 95 struct dc_edid_caps *edid_caps) 96 { 97 struct amdgpu_dm_connector *aconnector = link->priv; 98 struct drm_connector *connector = &aconnector->base; 99 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 100 struct cea_sad *sads; 101 int sad_count = -1; 102 int sadb_count = -1; 103 int i = 0; 104 uint8_t *sadb = NULL; 105 106 enum dc_edid_status result = EDID_OK; 107 108 if (!edid_caps || !edid) 109 return EDID_BAD_INPUT; 110 111 if (!drm_edid_is_valid(edid_buf)) 112 result = EDID_BAD_CHECKSUM; 113 114 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 115 ((uint16_t) edid_buf->mfg_id[1])<<8; 116 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 117 ((uint16_t) edid_buf->prod_code[1])<<8; 118 edid_caps->serial_number = edid_buf->serial; 119 edid_caps->manufacture_week = edid_buf->mfg_week; 120 edid_caps->manufacture_year = edid_buf->mfg_year; 121 122 drm_edid_get_monitor_name(edid_buf, 123 edid_caps->display_name, 124 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 125 126 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 127 128 apply_edid_quirks(edid_buf, edid_caps); 129 130 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 131 if (sad_count <= 0) 132 return result; 133 134 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 135 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 136 struct cea_sad *sad = &sads[i]; 137 138 edid_caps->audio_modes[i].format_code = sad->format; 139 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 140 edid_caps->audio_modes[i].sample_rate = sad->freq; 141 edid_caps->audio_modes[i].sample_size = sad->byte2; 142 } 143 144 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 145 146 if (sadb_count < 0) { 147 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 148 sadb_count = 0; 149 } 150 151 if (sadb_count) 152 edid_caps->speaker_flags = sadb[0]; 153 else 154 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 155 156 kfree(sads); 157 kfree(sadb); 158 159 return result; 160 } 161 162 static void 163 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 164 bool enable, 165 struct drm_dp_mst_atomic_payload *target_payload, 166 struct dc_dp_mst_stream_allocation_table *table) 167 { 168 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 169 struct dc_dp_mst_stream_allocation *sa; 170 struct link_mst_stream_allocation_table copy_of_link_table = 171 link->mst_stream_alloc_table; 172 173 int i; 174 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 175 struct link_mst_stream_allocation *dc_alloc; 176 177 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 178 if (enable) { 179 dc_alloc = 180 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 181 dc_alloc->vcp_id = target_payload->vcpi; 182 dc_alloc->slot_count = target_payload->time_slots; 183 } else { 184 for (i = 0; i < copy_of_link_table.stream_count; i++) { 185 dc_alloc = 186 ©_of_link_table.stream_allocations[i]; 187 188 if (dc_alloc->vcp_id == target_payload->vcpi) { 189 dc_alloc->vcp_id = 0; 190 dc_alloc->slot_count = 0; 191 break; 192 } 193 } 194 ASSERT(i != copy_of_link_table.stream_count); 195 } 196 197 /* Fill payload info*/ 198 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 199 dc_alloc = 200 ©_of_link_table.stream_allocations[i]; 201 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 202 sa = &new_table.stream_allocations[new_table.stream_count]; 203 sa->slot_count = dc_alloc->slot_count; 204 sa->vcp_id = dc_alloc->vcp_id; 205 new_table.stream_count++; 206 } 207 } 208 209 /* Overwrite the old table */ 210 *table = new_table; 211 } 212 213 void dm_helpers_dp_update_branch_info( 214 struct dc_context *ctx, 215 const struct dc_link *link) 216 {} 217 218 static void dm_helpers_construct_old_payload( 219 struct dc_link *link, 220 int pbn_per_slot, 221 struct drm_dp_mst_atomic_payload *new_payload, 222 struct drm_dp_mst_atomic_payload *old_payload) 223 { 224 struct link_mst_stream_allocation_table current_link_table = 225 link->mst_stream_alloc_table; 226 struct link_mst_stream_allocation *dc_alloc; 227 int i; 228 229 *old_payload = *new_payload; 230 231 /* Set correct time_slots/PBN of old payload. 232 * other fields (delete & dsc_enabled) in 233 * struct drm_dp_mst_atomic_payload are don't care fields 234 * while calling drm_dp_remove_payload() 235 */ 236 for (i = 0; i < current_link_table.stream_count; i++) { 237 dc_alloc = 238 ¤t_link_table.stream_allocations[i]; 239 240 if (dc_alloc->vcp_id == new_payload->vcpi) { 241 old_payload->time_slots = dc_alloc->slot_count; 242 old_payload->pbn = dc_alloc->slot_count * pbn_per_slot; 243 break; 244 } 245 } 246 247 /* make sure there is an old payload*/ 248 ASSERT(i != current_link_table.stream_count); 249 250 } 251 252 /* 253 * Writes payload allocation table in immediate downstream device. 254 */ 255 bool dm_helpers_dp_mst_write_payload_allocation_table( 256 struct dc_context *ctx, 257 const struct dc_stream_state *stream, 258 struct dc_dp_mst_stream_allocation_table *proposed_table, 259 bool enable) 260 { 261 struct amdgpu_dm_connector *aconnector; 262 struct drm_dp_mst_topology_state *mst_state; 263 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 264 struct drm_dp_mst_topology_mgr *mst_mgr; 265 266 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 267 /* Accessing the connector state is required for vcpi_slots allocation 268 * and directly relies on behaviour in commit check 269 * that blocks before commit guaranteeing that the state 270 * is not gonna be swapped while still in use in commit tail 271 */ 272 273 if (!aconnector || !aconnector->mst_root) 274 return false; 275 276 mst_mgr = &aconnector->mst_root->mst_mgr; 277 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 278 279 /* It's OK for this to fail */ 280 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 281 282 if (enable) { 283 target_payload = new_payload; 284 285 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 286 } else { 287 /* construct old payload by VCPI*/ 288 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div, 289 new_payload, &old_payload); 290 target_payload = &old_payload; 291 292 drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); 293 } 294 295 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 296 * AUX message. The sequence is slot 1-63 allocated sequence for each 297 * stream. AMD ASIC stream slot allocation should follow the same 298 * sequence. copy DRM MST allocation to dc 299 */ 300 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 301 302 return true; 303 } 304 305 /* 306 * poll pending down reply 307 */ 308 void dm_helpers_dp_mst_poll_pending_down_reply( 309 struct dc_context *ctx, 310 const struct dc_link *link) 311 {} 312 313 /* 314 * Clear payload allocation table before enable MST DP link. 315 */ 316 void dm_helpers_dp_mst_clear_payload_allocation_table( 317 struct dc_context *ctx, 318 const struct dc_link *link) 319 {} 320 321 /* 322 * Polls for ACT (allocation change trigger) handled and sends 323 * ALLOCATE_PAYLOAD message. 324 */ 325 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 326 struct dc_context *ctx, 327 const struct dc_stream_state *stream) 328 { 329 struct amdgpu_dm_connector *aconnector; 330 struct drm_dp_mst_topology_mgr *mst_mgr; 331 int ret; 332 333 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 334 335 if (!aconnector || !aconnector->mst_root) 336 return ACT_FAILED; 337 338 mst_mgr = &aconnector->mst_root->mst_mgr; 339 340 if (!mst_mgr->mst_state) 341 return ACT_FAILED; 342 343 ret = drm_dp_check_act_status(mst_mgr); 344 345 if (ret) 346 return ACT_FAILED; 347 348 return ACT_SUCCESS; 349 } 350 351 bool dm_helpers_dp_mst_send_payload_allocation( 352 struct dc_context *ctx, 353 const struct dc_stream_state *stream, 354 bool enable) 355 { 356 struct amdgpu_dm_connector *aconnector; 357 struct drm_dp_mst_topology_state *mst_state; 358 struct drm_dp_mst_topology_mgr *mst_mgr; 359 struct drm_dp_mst_atomic_payload *payload; 360 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 361 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 362 int ret = 0; 363 364 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 365 366 if (!aconnector || !aconnector->mst_root) 367 return false; 368 369 mst_mgr = &aconnector->mst_root->mst_mgr; 370 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 371 372 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 373 374 if (!enable) { 375 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 376 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 377 } 378 379 if (enable) 380 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload); 381 382 if (ret) { 383 amdgpu_dm_set_mst_status(&aconnector->mst_status, 384 set_flag, false); 385 } else { 386 amdgpu_dm_set_mst_status(&aconnector->mst_status, 387 set_flag, true); 388 amdgpu_dm_set_mst_status(&aconnector->mst_status, 389 clr_flag, false); 390 } 391 392 return true; 393 } 394 395 void dm_dtn_log_begin(struct dc_context *ctx, 396 struct dc_log_buffer_ctx *log_ctx) 397 { 398 static const char msg[] = "[dtn begin]\n"; 399 400 if (!log_ctx) { 401 pr_info("%s", msg); 402 return; 403 } 404 405 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 406 } 407 408 __printf(3, 4) 409 void dm_dtn_log_append_v(struct dc_context *ctx, 410 struct dc_log_buffer_ctx *log_ctx, 411 const char *msg, ...) 412 { 413 va_list args; 414 size_t total; 415 int n; 416 417 if (!log_ctx) { 418 /* No context, redirect to dmesg. */ 419 struct va_format vaf; 420 421 vaf.fmt = msg; 422 vaf.va = &args; 423 424 va_start(args, msg); 425 pr_info("%pV", &vaf); 426 va_end(args); 427 428 return; 429 } 430 431 /* Measure the output. */ 432 va_start(args, msg); 433 n = vsnprintf(NULL, 0, msg, args); 434 va_end(args); 435 436 if (n <= 0) 437 return; 438 439 /* Reallocate the string buffer as needed. */ 440 total = log_ctx->pos + n + 1; 441 442 if (total > log_ctx->size) { 443 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 444 445 if (buf) { 446 memcpy(buf, log_ctx->buf, log_ctx->pos); 447 kfree(log_ctx->buf); 448 449 log_ctx->buf = buf; 450 log_ctx->size = total; 451 } 452 } 453 454 if (!log_ctx->buf) 455 return; 456 457 /* Write the formatted string to the log buffer. */ 458 va_start(args, msg); 459 n = vscnprintf( 460 log_ctx->buf + log_ctx->pos, 461 log_ctx->size - log_ctx->pos, 462 msg, 463 args); 464 va_end(args); 465 466 if (n > 0) 467 log_ctx->pos += n; 468 } 469 470 void dm_dtn_log_end(struct dc_context *ctx, 471 struct dc_log_buffer_ctx *log_ctx) 472 { 473 static const char msg[] = "[dtn end]\n"; 474 475 if (!log_ctx) { 476 pr_info("%s", msg); 477 return; 478 } 479 480 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 481 } 482 483 bool dm_helpers_dp_mst_start_top_mgr( 484 struct dc_context *ctx, 485 const struct dc_link *link, 486 bool boot) 487 { 488 struct amdgpu_dm_connector *aconnector = link->priv; 489 int ret; 490 491 if (!aconnector) { 492 DRM_ERROR("Failed to find connector for link!"); 493 return false; 494 } 495 496 if (boot) { 497 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 498 aconnector, aconnector->base.base.id); 499 return true; 500 } 501 502 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 503 aconnector, aconnector->base.base.id); 504 505 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 506 if (ret < 0) { 507 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 508 return false; 509 } 510 511 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 512 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 513 514 return true; 515 } 516 517 bool dm_helpers_dp_mst_stop_top_mgr( 518 struct dc_context *ctx, 519 struct dc_link *link) 520 { 521 struct amdgpu_dm_connector *aconnector = link->priv; 522 523 if (!aconnector) { 524 DRM_ERROR("Failed to find connector for link!"); 525 return false; 526 } 527 528 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 529 aconnector, aconnector->base.base.id); 530 531 if (aconnector->mst_mgr.mst_state == true) { 532 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 533 link->cur_link_settings.lane_count = 0; 534 } 535 536 return false; 537 } 538 539 bool dm_helpers_dp_read_dpcd( 540 struct dc_context *ctx, 541 const struct dc_link *link, 542 uint32_t address, 543 uint8_t *data, 544 uint32_t size) 545 { 546 547 struct amdgpu_dm_connector *aconnector = link->priv; 548 549 if (!aconnector) { 550 DC_LOG_DC("Failed to find connector for link!\n"); 551 return false; 552 } 553 554 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 555 size) == size; 556 } 557 558 bool dm_helpers_dp_write_dpcd( 559 struct dc_context *ctx, 560 const struct dc_link *link, 561 uint32_t address, 562 const uint8_t *data, 563 uint32_t size) 564 { 565 struct amdgpu_dm_connector *aconnector = link->priv; 566 567 if (!aconnector) { 568 DRM_ERROR("Failed to find connector for link!"); 569 return false; 570 } 571 572 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 573 address, (uint8_t *)data, size) > 0; 574 } 575 576 bool dm_helpers_submit_i2c( 577 struct dc_context *ctx, 578 const struct dc_link *link, 579 struct i2c_command *cmd) 580 { 581 struct amdgpu_dm_connector *aconnector = link->priv; 582 struct i2c_msg *msgs; 583 int i = 0; 584 int num = cmd->number_of_payloads; 585 bool result; 586 587 if (!aconnector) { 588 DRM_ERROR("Failed to find connector for link!"); 589 return false; 590 } 591 592 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 593 594 if (!msgs) 595 return false; 596 597 for (i = 0; i < num; i++) { 598 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 599 msgs[i].addr = cmd->payloads[i].address; 600 msgs[i].len = cmd->payloads[i].length; 601 msgs[i].buf = cmd->payloads[i].data; 602 } 603 604 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 605 606 kfree(msgs); 607 608 return result; 609 } 610 611 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 612 bool is_write_cmd, 613 unsigned char cmd, 614 unsigned int length, 615 unsigned int offset, 616 unsigned char *data) 617 { 618 bool success = false; 619 unsigned char rc_data[16] = {0}; 620 unsigned char rc_offset[4] = {0}; 621 unsigned char rc_length[2] = {0}; 622 unsigned char rc_cmd = 0; 623 unsigned char rc_result = 0xFF; 624 unsigned char i = 0; 625 int ret; 626 627 if (is_write_cmd) { 628 // write rc data 629 memmove(rc_data, data, length); 630 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 631 } 632 633 // write rc offset 634 rc_offset[0] = (unsigned char) offset & 0xFF; 635 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 636 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 637 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 638 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 639 640 // write rc length 641 rc_length[0] = (unsigned char) length & 0xFF; 642 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 643 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 644 645 // write rc cmd 646 rc_cmd = cmd | 0x80; 647 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 648 649 if (ret < 0) { 650 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 651 return false; 652 } 653 654 // poll until active is 0 655 for (i = 0; i < 10; i++) { 656 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 657 if (rc_cmd == cmd) 658 // active is 0 659 break; 660 drm_msleep(10); 661 } 662 663 // read rc result 664 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 665 success = (rc_result == 0); 666 667 if (success && !is_write_cmd) { 668 // read rc data 669 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 670 } 671 672 DC_LOG_DC("%s: success = %d\n", __func__, success); 673 674 return success; 675 } 676 677 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 678 { 679 unsigned char data[16] = {0}; 680 681 DC_LOG_DC("Start %s\n", __func__); 682 683 // Step 2 684 data[0] = 'P'; 685 data[1] = 'R'; 686 data[2] = 'I'; 687 data[3] = 'U'; 688 data[4] = 'S'; 689 690 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 691 return; 692 693 // Step 3 and 4 694 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 695 return; 696 697 data[0] &= (~(1 << 1)); // set bit 1 to 0 698 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 699 return; 700 701 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 702 return; 703 704 data[0] &= (~(1 << 1)); // set bit 1 to 0 705 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 706 return; 707 708 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 709 return; 710 711 data[0] &= (~(1 << 1)); // set bit 1 to 0 712 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 713 return; 714 715 // Step 3 and 5 716 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 717 return; 718 719 data[0] |= (1 << 1); // set bit 1 to 1 720 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 721 return; 722 723 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 724 return; 725 726 data[0] |= (1 << 1); // set bit 1 to 1 727 728 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 729 return; 730 731 data[0] |= (1 << 1); // set bit 1 to 1 732 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 733 return; 734 735 // Step 6 736 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 737 return; 738 739 DC_LOG_DC("Done %s\n", __func__); 740 } 741 742 /* MST Dock */ 743 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 744 745 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 746 struct drm_dp_aux *aux, 747 const struct dc_stream_state *stream, 748 bool enable) 749 { 750 uint8_t ret = 0; 751 752 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n"); 753 754 if (enable) { 755 /* When DSC is enabled on previous boot and reboot with the hub, 756 * there is a chance that Synaptics hub gets stuck during reboot sequence. 757 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 758 */ 759 if (!stream->link->link_status.link_active && 760 memcmp(stream->link->dpcd_caps.branch_dev_name, 761 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 762 apply_synaptics_fifo_reset_wa(aux); 763 764 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 765 DRM_INFO("Send DSC enable to synaptics\n"); 766 767 } else { 768 /* Synaptics hub not support virtual dpcd, 769 * external monitor occur garbage while disable DSC, 770 * Disable DSC only when entire link status turn to false, 771 */ 772 if (!stream->link->link_status.link_active) { 773 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 774 DRM_INFO("Send DSC disable to synaptics\n"); 775 } 776 } 777 778 return ret; 779 } 780 781 bool dm_helpers_dp_write_dsc_enable( 782 struct dc_context *ctx, 783 const struct dc_stream_state *stream, 784 bool enable) 785 { 786 static const uint8_t DSC_DISABLE; 787 static const uint8_t DSC_DECODING = 0x01; 788 static const uint8_t DSC_PASSTHROUGH = 0x02; 789 790 struct amdgpu_dm_connector *aconnector; 791 struct drm_dp_mst_port *port; 792 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 793 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 794 uint8_t ret = 0; 795 796 if (!stream) 797 return false; 798 799 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 800 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 801 802 if (!aconnector->dsc_aux) 803 return false; 804 805 // apply w/a to synaptics 806 if (needs_dsc_aux_workaround(aconnector->dc_link) && 807 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 808 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 809 aconnector->dsc_aux, stream, enable_dsc); 810 811 port = aconnector->mst_output_port; 812 813 if (enable) { 814 if (port->passthrough_aux) { 815 ret = drm_dp_dpcd_write(port->passthrough_aux, 816 DP_DSC_ENABLE, 817 &enable_passthrough, 1); 818 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 819 ret); 820 } 821 822 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 823 DP_DSC_ENABLE, &enable_dsc, 1); 824 DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", 825 (port->passthrough_aux) ? "remote RX" : 826 "virtual dpcd", 827 ret); 828 } else { 829 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 830 DP_DSC_ENABLE, &enable_dsc, 1); 831 DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", 832 (port->passthrough_aux) ? "remote RX" : 833 "virtual dpcd", 834 ret); 835 836 if (port->passthrough_aux) { 837 ret = drm_dp_dpcd_write(port->passthrough_aux, 838 DP_DSC_ENABLE, 839 &enable_passthrough, 1); 840 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 841 ret); 842 } 843 } 844 } 845 846 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 847 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 848 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 849 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); 850 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 851 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 852 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); 853 } 854 } 855 856 return ret; 857 } 858 859 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 860 { 861 bool dp_sink_present; 862 struct amdgpu_dm_connector *aconnector = link->priv; 863 864 if (!aconnector) { 865 BUG_ON("Failed to find connector for link!"); 866 return true; 867 } 868 869 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 870 dp_sink_present = dc_link_is_dp_sink_present(link); 871 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 872 return dp_sink_present; 873 } 874 875 enum dc_edid_status dm_helpers_read_local_edid( 876 struct dc_context *ctx, 877 struct dc_link *link, 878 struct dc_sink *sink) 879 { 880 struct amdgpu_dm_connector *aconnector = link->priv; 881 struct drm_connector *connector = &aconnector->base; 882 struct i2c_adapter *ddc; 883 int retry = 3; 884 enum dc_edid_status edid_status; 885 struct edid *edid; 886 887 if (link->aux_mode) 888 ddc = &aconnector->dm_dp_aux.aux.ddc; 889 else 890 ddc = &aconnector->i2c->base; 891 892 /* some dongles read edid incorrectly the first time, 893 * do check sum and retry to make sure read correct edid. 894 */ 895 do { 896 897 edid = drm_get_edid(&aconnector->base, ddc); 898 899 /* DP Compliance Test 4.2.2.6 */ 900 if (link->aux_mode && connector->edid_corrupt) 901 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 902 903 if (!edid && connector->edid_corrupt) { 904 connector->edid_corrupt = false; 905 return EDID_BAD_CHECKSUM; 906 } 907 908 if (!edid) 909 return EDID_NO_RESPONSE; 910 911 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 912 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 913 914 /* We don't need the original edid anymore */ 915 kfree(edid); 916 917 edid_status = dm_helpers_parse_edid_caps( 918 link, 919 &sink->dc_edid, 920 &sink->edid_caps); 921 922 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 923 924 if (edid_status != EDID_OK) 925 DRM_ERROR("EDID err: %d, on connector: %s", 926 edid_status, 927 aconnector->base.name); 928 if (link->aux_mode) { 929 union test_request test_request = {0}; 930 union test_response test_response = {0}; 931 932 dm_helpers_dp_read_dpcd(ctx, 933 link, 934 DP_TEST_REQUEST, 935 &test_request.raw, 936 sizeof(union test_request)); 937 938 if (!test_request.bits.EDID_READ) 939 return edid_status; 940 941 test_response.bits.EDID_CHECKSUM_WRITE = 1; 942 943 dm_helpers_dp_write_dpcd(ctx, 944 link, 945 DP_TEST_EDID_CHECKSUM, 946 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 947 1); 948 949 dm_helpers_dp_write_dpcd(ctx, 950 link, 951 DP_TEST_RESPONSE, 952 &test_response.raw, 953 sizeof(test_response)); 954 955 } 956 957 return edid_status; 958 } 959 int dm_helper_dmub_aux_transfer_sync( 960 struct dc_context *ctx, 961 const struct dc_link *link, 962 struct aux_payload *payload, 963 enum aux_return_code_type *operation_result) 964 { 965 if (!link->hpd_status) { 966 *operation_result = AUX_RET_ERROR_HPD_DISCON; 967 return -1; 968 } 969 970 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 971 operation_result); 972 } 973 974 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 975 const struct dc_link *link, 976 struct set_config_cmd_payload *payload, 977 enum set_config_status *operation_result) 978 { 979 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 980 operation_result); 981 } 982 983 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 984 { 985 /* TODO: something */ 986 } 987 988 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 989 { 990 // TODO: 991 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 992 } 993 994 void dm_helpers_init_panel_settings( 995 struct dc_context *ctx, 996 struct dc_panel_config *panel_config, 997 struct dc_sink *sink) 998 { 999 // Extra Panel Power Sequence 1000 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 1001 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 1002 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 1003 panel_config->pps.extra_post_t7_ms = 0; 1004 panel_config->pps.extra_pre_t11_ms = 0; 1005 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1006 panel_config->pps.extra_post_OUI_ms = 0; 1007 // Feature DSC 1008 panel_config->dsc.disable_dsc_edp = false; 1009 panel_config->dsc.force_dsc_edp_policy = 0; 1010 } 1011 1012 void dm_helpers_override_panel_settings( 1013 struct dc_context *ctx, 1014 struct dc_panel_config *panel_config) 1015 { 1016 // Feature DSC 1017 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1018 panel_config->dsc.disable_dsc_edp = true; 1019 } 1020 1021 void *dm_helpers_allocate_gpu_mem( 1022 struct dc_context *ctx, 1023 enum dc_gpu_mem_alloc_type type, 1024 size_t size, 1025 long long *addr) 1026 { 1027 struct amdgpu_device *adev = ctx->driver_context; 1028 struct dal_allocation *da; 1029 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1030 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1031 int ret; 1032 1033 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1034 if (!da) 1035 return NULL; 1036 1037 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1038 domain, &da->bo, 1039 &da->gpu_addr, &da->cpu_ptr); 1040 1041 *addr = da->gpu_addr; 1042 1043 if (ret) { 1044 kfree(da); 1045 return NULL; 1046 } 1047 1048 /* add da to list in dm */ 1049 list_add(&da->list, &adev->dm.da_list); 1050 1051 return da->cpu_ptr; 1052 } 1053 1054 void dm_helpers_free_gpu_mem( 1055 struct dc_context *ctx, 1056 enum dc_gpu_mem_alloc_type type, 1057 void *pvMem) 1058 { 1059 struct amdgpu_device *adev = ctx->driver_context; 1060 struct dal_allocation *da; 1061 1062 /* walk the da list in DM */ 1063 list_for_each_entry(da, &adev->dm.da_list, list) { 1064 if (pvMem == da->cpu_ptr) { 1065 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1066 list_del(&da->list); 1067 kfree(da); 1068 break; 1069 } 1070 } 1071 } 1072 1073 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1074 { 1075 enum dc_irq_source irq_source; 1076 bool ret; 1077 1078 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1079 1080 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1081 1082 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1083 enable ? "en" : "dis", ret); 1084 return ret; 1085 } 1086 1087 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1088 { 1089 /* TODO: virtual DPCD */ 1090 struct dc_link *link = stream->link; 1091 union down_spread_ctrl old_downspread; 1092 union down_spread_ctrl new_downspread; 1093 1094 if (link->aux_access_disabled) 1095 return; 1096 1097 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1098 &old_downspread.raw, 1099 sizeof(old_downspread))) 1100 return; 1101 1102 new_downspread.raw = old_downspread.raw; 1103 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1104 (stream->ignore_msa_timing_param) ? 1 : 0; 1105 1106 if (new_downspread.raw != old_downspread.raw) 1107 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1108 &new_downspread.raw, 1109 sizeof(new_downspread)); 1110 } 1111 1112 bool dm_helpers_dp_handle_test_pattern_request( 1113 struct dc_context *ctx, 1114 const struct dc_link *link, 1115 union link_test_pattern dpcd_test_pattern, 1116 union test_misc dpcd_test_params) 1117 { 1118 enum dp_test_pattern test_pattern; 1119 enum dp_test_pattern_color_space test_pattern_color_space = 1120 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1121 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1122 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1123 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1124 struct pipe_ctx *pipe_ctx = NULL; 1125 struct amdgpu_dm_connector *aconnector = link->priv; 1126 int i; 1127 1128 for (i = 0; i < MAX_PIPES; i++) { 1129 if (pipes[i].stream == NULL) 1130 continue; 1131 1132 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1133 !pipes[i].prev_odm_pipe) { 1134 pipe_ctx = &pipes[i]; 1135 break; 1136 } 1137 } 1138 1139 if (pipe_ctx == NULL) 1140 return false; 1141 1142 switch (dpcd_test_pattern.bits.PATTERN) { 1143 case LINK_TEST_PATTERN_COLOR_RAMP: 1144 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1145 break; 1146 case LINK_TEST_PATTERN_VERTICAL_BARS: 1147 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1148 break; /* black and white */ 1149 case LINK_TEST_PATTERN_COLOR_SQUARES: 1150 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1151 TEST_DYN_RANGE_VESA ? 1152 DP_TEST_PATTERN_COLOR_SQUARES : 1153 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1154 break; 1155 default: 1156 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1157 break; 1158 } 1159 1160 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1161 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1162 else 1163 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1164 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1165 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1166 1167 switch (dpcd_test_params.bits.BPC) { 1168 case 0: // 6 bits 1169 requestColorDepth = COLOR_DEPTH_666; 1170 break; 1171 case 1: // 8 bits 1172 requestColorDepth = COLOR_DEPTH_888; 1173 break; 1174 case 2: // 10 bits 1175 requestColorDepth = COLOR_DEPTH_101010; 1176 break; 1177 case 3: // 12 bits 1178 requestColorDepth = COLOR_DEPTH_121212; 1179 break; 1180 default: 1181 break; 1182 } 1183 1184 switch (dpcd_test_params.bits.CLR_FORMAT) { 1185 case 0: 1186 requestPixelEncoding = PIXEL_ENCODING_RGB; 1187 break; 1188 case 1: 1189 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1190 break; 1191 case 2: 1192 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1193 break; 1194 default: 1195 requestPixelEncoding = PIXEL_ENCODING_RGB; 1196 break; 1197 } 1198 1199 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1200 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1201 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1202 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1203 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d %d\n", 1204 __func__, 1205 pipe_ctx->stream->timing.display_color_depth, 1206 pipe_ctx->stream->timing.pixel_encoding, 1207 requestColorDepth, 1208 requestPixelEncoding); 1209 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1210 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1211 1212 dc_link_update_dsc_config(pipe_ctx); 1213 1214 aconnector->timing_changed = true; 1215 /* store current timing */ 1216 if (aconnector->timing_requested) 1217 *aconnector->timing_requested = pipe_ctx->stream->timing; 1218 else 1219 DC_LOG_ERROR("%s: timing storage failed\n", __func__); 1220 1221 } 1222 1223 dc_link_dp_set_test_pattern( 1224 (struct dc_link *) link, 1225 test_pattern, 1226 test_pattern_color_space, 1227 NULL, 1228 NULL, 1229 0); 1230 1231 return false; 1232 } 1233 1234 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1235 { 1236 // TODO 1237 } 1238 1239 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1240 { 1241 /* TODO: add periodic detection implementation */ 1242 } 1243 1244 void dm_helpers_dp_mst_update_branch_bandwidth( 1245 struct dc_context *ctx, 1246 struct dc_link *link) 1247 { 1248 // TODO 1249 } 1250 1251 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1252 { 1253 bool ret_val = false; 1254 1255 switch (branch_dev_id) { 1256 case DP_BRANCH_DEVICE_ID_0060AD: 1257 case DP_BRANCH_DEVICE_ID_00E04C: 1258 case DP_BRANCH_DEVICE_ID_90CC24: 1259 ret_val = true; 1260 break; 1261 default: 1262 break; 1263 } 1264 1265 return ret_val; 1266 } 1267 1268 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1269 { 1270 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1271 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1272 1273 switch (dpcd_caps->dongle_type) { 1274 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1275 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1276 dpcd_caps->allow_invalid_MSA_timing_param == true && 1277 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1278 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1279 break; 1280 default: 1281 break; 1282 } 1283 1284 return as_type; 1285 } 1286