1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/dma-buf.h> 42 #include <linux/sizes.h> 43 #include <linux/module.h> 44 45 #include <drm/drm_drv.h> 46 #include <drm/ttm/ttm_bo.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 #include <drm/ttm/ttm_tt.h> 50 51 #include <drm/amdgpu_drm.h> 52 53 #include "amdgpu.h" 54 #include "amdgpu_object.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_sdma.h" 58 #include "amdgpu_ras.h" 59 #include "amdgpu_hmm.h" 60 #include "amdgpu_atomfirmware.h" 61 #include "amdgpu_res_cursor.h" 62 #include "bif/bif_4_1_d.h" 63 64 MODULE_IMPORT_NS(DMA_BUF); 65 66 #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) 67 68 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 69 struct ttm_tt *ttm, 70 struct ttm_resource *bo_mem); 71 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 72 struct ttm_tt *ttm); 73 74 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 75 unsigned int type, 76 uint64_t size_in_page) 77 { 78 return ttm_range_man_init(&adev->mman.bdev, type, 79 false, size_in_page); 80 } 81 82 /** 83 * amdgpu_evict_flags - Compute placement flags 84 * 85 * @bo: The buffer object to evict 86 * @placement: Possible destination(s) for evicted BO 87 * 88 * Fill in placement data when ttm_bo_evict() is called 89 */ 90 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 91 struct ttm_placement *placement) 92 { 93 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 94 struct amdgpu_bo *abo; 95 static const struct ttm_place placements = { 96 .fpfn = 0, 97 .lpfn = 0, 98 .mem_type = TTM_PL_SYSTEM, 99 .flags = 0 100 }; 101 102 /* Don't handle scatter gather BOs */ 103 if (bo->type == ttm_bo_type_sg) { 104 placement->num_placement = 0; 105 placement->num_busy_placement = 0; 106 return; 107 } 108 109 /* Object isn't an AMDGPU object so ignore */ 110 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 111 placement->placement = &placements; 112 placement->busy_placement = &placements; 113 placement->num_placement = 1; 114 placement->num_busy_placement = 1; 115 return; 116 } 117 118 abo = ttm_to_amdgpu_bo(bo); 119 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 120 placement->num_placement = 0; 121 placement->num_busy_placement = 0; 122 return; 123 } 124 125 switch (bo->resource->mem_type) { 126 case AMDGPU_PL_GDS: 127 case AMDGPU_PL_GWS: 128 case AMDGPU_PL_OA: 129 case AMDGPU_PL_DOORBELL: 130 placement->num_placement = 0; 131 placement->num_busy_placement = 0; 132 return; 133 134 case TTM_PL_VRAM: 135 if (!adev->mman.buffer_funcs_enabled) { 136 /* Move to system memory */ 137 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 139 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 140 amdgpu_res_cpu_visible(adev, bo->resource)) { 141 142 /* Try evicting to the CPU inaccessible part of VRAM 143 * first, but only set GTT as busy placement, so this 144 * BO will be evicted to GTT rather than causing other 145 * BOs to be evicted from VRAM 146 */ 147 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 148 AMDGPU_GEM_DOMAIN_GTT | 149 AMDGPU_GEM_DOMAIN_CPU); 150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 151 abo->placements[0].lpfn = 0; 152 abo->placement.busy_placement = &abo->placements[1]; 153 abo->placement.num_busy_placement = 1; 154 } else { 155 /* Move to GTT memory */ 156 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 157 AMDGPU_GEM_DOMAIN_CPU); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @window: which GART window to use 175 * @ring: DMA ring to use for the copy 176 * @tmz: if we should setup a TMZ enabled mapping 177 * @size: in number of bytes to map, out number of bytes mapped 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned int window, struct amdgpu_ring *ring, 187 bool tmz, uint64_t *size, uint64_t *addr) 188 { 189 struct amdgpu_device *adev = ring->adev; 190 unsigned int offset, num_pages, num_dw, num_bytes; 191 uint64_t src_addr, dst_addr; 192 struct amdgpu_job *job; 193 void *cpu_addr; 194 uint64_t flags; 195 unsigned int i; 196 int r; 197 198 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 199 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 200 201 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 202 return -EINVAL; 203 204 /* Map only what can't be accessed directly */ 205 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 206 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 207 mm_cur->start; 208 return 0; 209 } 210 211 212 /* 213 * If start begins at an offset inside the page, then adjust the size 214 * and addr accordingly 215 */ 216 offset = mm_cur->start & ~LINUX_PAGE_MASK; 217 218 num_pages = PFN_UP(*size + offset); 219 num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE); 220 221 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 222 223 *addr = adev->gmc.gart_start; 224 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 225 AMDGPU_GPU_PAGE_SIZE; 226 *addr += offset; 227 228 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 229 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 230 231 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, 232 AMDGPU_FENCE_OWNER_UNDEFINED, 233 num_dw * 4 + num_bytes, 234 AMDGPU_IB_POOL_DELAYED, &job); 235 if (r) 236 return r; 237 238 src_addr = num_dw * 4; 239 src_addr += job->ibs[0].gpu_addr; 240 241 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 242 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 243 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 244 dst_addr, num_bytes, false); 245 246 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 247 WARN_ON(job->ibs[0].length_dw > num_dw); 248 249 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 250 if (tmz) 251 flags |= AMDGPU_PTE_TMZ; 252 253 cpu_addr = &job->ibs[0].ptr[num_dw]; 254 255 if (mem->mem_type == TTM_PL_TT) { 256 dma_addr_t *dma_addr; 257 258 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 259 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 260 } else { 261 dma_addr_t dma_address; 262 263 dma_address = mm_cur->start; 264 dma_address += adev->vm_manager.vram_base_offset; 265 266 for (i = 0; i < num_pages; ++i) { 267 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, 268 flags, cpu_addr); 269 dma_address += PAGE_SIZE; 270 } 271 } 272 273 dma_fence_put(amdgpu_job_submit(job)); 274 return 0; 275 } 276 277 /** 278 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 279 * @adev: amdgpu device 280 * @src: buffer/address where to read from 281 * @dst: buffer/address where to write to 282 * @size: number of bytes to copy 283 * @tmz: if a secure copy should be used 284 * @resv: resv object to sync to 285 * @f: Returns the last fence if multiple jobs are submitted. 286 * 287 * The function copies @size bytes from {src->mem + src->offset} to 288 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 289 * move and different for a BO to BO copy. 290 * 291 */ 292 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 293 const struct amdgpu_copy_mem *src, 294 const struct amdgpu_copy_mem *dst, 295 uint64_t size, bool tmz, 296 struct dma_resv *resv, 297 struct dma_fence **f) 298 { 299 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 300 struct amdgpu_res_cursor src_mm, dst_mm; 301 struct dma_fence *fence = NULL; 302 int r = 0; 303 304 if (!adev->mman.buffer_funcs_enabled) { 305 DRM_ERROR("Trying to move memory with ring turned off.\n"); 306 return -EINVAL; 307 } 308 309 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 310 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 311 312 mutex_lock(&adev->mman.gtt_window_lock); 313 while (src_mm.remaining) { 314 uint64_t from, to, cur_size; 315 struct dma_fence *next; 316 317 /* Never copy more than 256MiB at once to avoid a timeout */ 318 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 319 320 /* Map src to window 0 and dst to window 1. */ 321 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 322 0, ring, tmz, &cur_size, &from); 323 if (r) 324 goto error; 325 326 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 327 1, ring, tmz, &cur_size, &to); 328 if (r) 329 goto error; 330 331 r = amdgpu_copy_buffer(ring, from, to, cur_size, 332 resv, &next, false, true, tmz); 333 if (r) 334 goto error; 335 336 dma_fence_put(fence); 337 fence = next; 338 339 amdgpu_res_next(&src_mm, cur_size); 340 amdgpu_res_next(&dst_mm, cur_size); 341 } 342 error: 343 mutex_unlock(&adev->mman.gtt_window_lock); 344 if (f) 345 *f = dma_fence_get(fence); 346 dma_fence_put(fence); 347 return r; 348 } 349 350 /* 351 * amdgpu_move_blit - Copy an entire buffer to another buffer 352 * 353 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 354 * help move buffers to and from VRAM. 355 */ 356 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 357 bool evict, 358 struct ttm_resource *new_mem, 359 struct ttm_resource *old_mem) 360 { 361 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 362 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 363 struct amdgpu_copy_mem src, dst; 364 struct dma_fence *fence = NULL; 365 int r; 366 367 src.bo = bo; 368 dst.bo = bo; 369 src.mem = old_mem; 370 dst.mem = new_mem; 371 src.offset = 0; 372 dst.offset = 0; 373 374 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 375 new_mem->size, 376 amdgpu_bo_encrypted(abo), 377 bo->base.resv, &fence); 378 if (r) 379 goto error; 380 381 /* clear the space being freed */ 382 if (old_mem->mem_type == TTM_PL_VRAM && 383 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 384 struct dma_fence *wipe_fence = NULL; 385 386 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence, 387 false); 388 if (r) { 389 goto error; 390 } else if (wipe_fence) { 391 dma_fence_put(fence); 392 fence = wipe_fence; 393 } 394 } 395 396 /* Always block for VM page tables before committing the new location */ 397 if (bo->type == ttm_bo_type_kernel) 398 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 399 else 400 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 401 dma_fence_put(fence); 402 return r; 403 404 error: 405 if (fence) 406 dma_fence_wait(fence, false); 407 dma_fence_put(fence); 408 return r; 409 } 410 411 /** 412 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU 413 * @adev: amdgpu device 414 * @res: the resource to check 415 * 416 * Returns: true if the full resource is CPU visible, false otherwise. 417 */ 418 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 419 struct ttm_resource *res) 420 { 421 struct amdgpu_res_cursor cursor; 422 423 if (!res) 424 return false; 425 426 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || 427 res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL) 428 return true; 429 430 if (res->mem_type != TTM_PL_VRAM) 431 return false; 432 433 amdgpu_res_first(res, 0, res->size, &cursor); 434 while (cursor.remaining) { 435 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) 436 return false; 437 amdgpu_res_next(&cursor, cursor.size); 438 } 439 440 return true; 441 } 442 443 /* 444 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy 445 * 446 * Called by amdgpu_bo_move() 447 */ 448 static bool amdgpu_res_copyable(struct amdgpu_device *adev, 449 struct ttm_resource *mem) 450 { 451 if (!amdgpu_res_cpu_visible(adev, mem)) 452 return false; 453 454 /* ttm_resource_ioremap only supports contiguous memory */ 455 if (mem->mem_type == TTM_PL_VRAM && 456 !(mem->placement & TTM_PL_FLAG_CONTIGUOUS)) 457 return false; 458 459 return true; 460 } 461 462 /* 463 * amdgpu_bo_move - Move a buffer object to a new memory location 464 * 465 * Called by ttm_bo_handle_move_mem() 466 */ 467 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 468 struct ttm_operation_ctx *ctx, 469 struct ttm_resource *new_mem, 470 struct ttm_place *hop) 471 { 472 struct amdgpu_device *adev; 473 struct amdgpu_bo *abo; 474 struct ttm_resource *old_mem = bo->resource; 475 int r; 476 477 if (new_mem->mem_type == TTM_PL_TT || 478 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 479 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 480 if (r) 481 return r; 482 } 483 484 abo = ttm_to_amdgpu_bo(bo); 485 adev = amdgpu_ttm_adev(bo->bdev); 486 487 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 488 bo->ttm == NULL)) { 489 amdgpu_bo_move_notify(bo, evict, new_mem); 490 ttm_bo_move_null(bo, new_mem); 491 return 0; 492 } 493 if (old_mem->mem_type == TTM_PL_SYSTEM && 494 (new_mem->mem_type == TTM_PL_TT || 495 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 496 amdgpu_bo_move_notify(bo, evict, new_mem); 497 ttm_bo_move_null(bo, new_mem); 498 return 0; 499 } 500 if ((old_mem->mem_type == TTM_PL_TT || 501 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 502 new_mem->mem_type == TTM_PL_SYSTEM) { 503 r = ttm_bo_wait_ctx(bo, ctx); 504 if (r) 505 return r; 506 507 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 508 amdgpu_bo_move_notify(bo, evict, new_mem); 509 ttm_resource_free(bo, &bo->resource); 510 ttm_bo_assign_mem(bo, new_mem); 511 return 0; 512 } 513 514 if (old_mem->mem_type == AMDGPU_PL_GDS || 515 old_mem->mem_type == AMDGPU_PL_GWS || 516 old_mem->mem_type == AMDGPU_PL_OA || 517 old_mem->mem_type == AMDGPU_PL_DOORBELL || 518 new_mem->mem_type == AMDGPU_PL_GDS || 519 new_mem->mem_type == AMDGPU_PL_GWS || 520 new_mem->mem_type == AMDGPU_PL_OA || 521 new_mem->mem_type == AMDGPU_PL_DOORBELL) { 522 /* Nothing to save here */ 523 amdgpu_bo_move_notify(bo, evict, new_mem); 524 ttm_bo_move_null(bo, new_mem); 525 return 0; 526 } 527 528 if (bo->type == ttm_bo_type_device && 529 new_mem->mem_type == TTM_PL_VRAM && 530 old_mem->mem_type != TTM_PL_VRAM) { 531 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 532 * accesses the BO after it's moved. 533 */ 534 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 535 } 536 537 if (adev->mman.buffer_funcs_enabled && 538 ((old_mem->mem_type == TTM_PL_SYSTEM && 539 new_mem->mem_type == TTM_PL_VRAM) || 540 (old_mem->mem_type == TTM_PL_VRAM && 541 new_mem->mem_type == TTM_PL_SYSTEM))) { 542 hop->fpfn = 0; 543 hop->lpfn = 0; 544 hop->mem_type = TTM_PL_TT; 545 hop->flags = TTM_PL_FLAG_TEMPORARY; 546 return -EMULTIHOP; 547 } 548 549 amdgpu_bo_move_notify(bo, evict, new_mem); 550 if (adev->mman.buffer_funcs_enabled) 551 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 552 else 553 r = -ENODEV; 554 555 if (r) { 556 /* Check that all memory is CPU accessible */ 557 if (!amdgpu_res_copyable(adev, old_mem) || 558 !amdgpu_res_copyable(adev, new_mem)) { 559 pr_err("Move buffer fallback to memcpy unavailable\n"); 560 return r; 561 } 562 563 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 564 if (r) 565 return r; 566 } 567 568 /* update statistics after the move */ 569 if (evict) 570 atomic64_inc(&adev->num_evictions); 571 atomic64_add(bo->base.size, &adev->num_bytes_moved); 572 return 0; 573 } 574 575 /* 576 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 577 * 578 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 579 */ 580 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 581 struct ttm_resource *mem) 582 { 583 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 584 585 switch (mem->mem_type) { 586 case TTM_PL_SYSTEM: 587 /* system memory */ 588 return 0; 589 case TTM_PL_TT: 590 case AMDGPU_PL_PREEMPT: 591 break; 592 case TTM_PL_VRAM: 593 mem->bus.offset = mem->start << PAGE_SHIFT; 594 595 if (adev->mman.aper_base_kaddr && 596 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 597 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 598 mem->bus.offset; 599 600 mem->bus.offset += adev->gmc.aper_base; 601 mem->bus.is_iomem = true; 602 break; 603 case AMDGPU_PL_DOORBELL: 604 mem->bus.offset = mem->start << PAGE_SHIFT; 605 mem->bus.offset += adev->doorbell.base; 606 mem->bus.is_iomem = true; 607 mem->bus.caching = ttm_uncached; 608 break; 609 default: 610 return -EINVAL; 611 } 612 return 0; 613 } 614 615 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 616 unsigned long page_offset) 617 { 618 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 619 struct amdgpu_res_cursor cursor; 620 621 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 622 &cursor); 623 624 if (bo->resource->mem_type == AMDGPU_PL_DOORBELL) 625 return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT; 626 627 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 628 } 629 630 /** 631 * amdgpu_ttm_domain_start - Returns GPU start address 632 * @adev: amdgpu device object 633 * @type: type of the memory 634 * 635 * Returns: 636 * GPU start address of a memory domain 637 */ 638 639 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 640 { 641 switch (type) { 642 case TTM_PL_TT: 643 return adev->gmc.gart_start; 644 case TTM_PL_VRAM: 645 return adev->gmc.vram_start; 646 } 647 648 return 0; 649 } 650 651 /* 652 * TTM backend functions. 653 */ 654 struct amdgpu_ttm_tt { 655 struct ttm_tt ttm; 656 struct drm_gem_object *gobj; 657 u64 offset; 658 uint64_t userptr; 659 struct task_struct *usertask; 660 uint32_t userflags; 661 bool bound; 662 int32_t pool_id; 663 }; 664 665 #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) 666 667 #ifdef CONFIG_DRM_AMDGPU_USERPTR 668 /* 669 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 670 * memory and start HMM tracking CPU page table update 671 * 672 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 673 * once afterwards to stop HMM tracking 674 */ 675 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct vm_page **pages, 676 struct hmm_range **range) 677 { 678 struct ttm_tt *ttm = bo->tbo.ttm; 679 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 680 unsigned long start = gtt->userptr; 681 struct vm_area_struct *vma; 682 struct mm_struct *mm; 683 bool readonly; 684 int r = 0; 685 686 /* Make sure get_user_pages_done() can cleanup gracefully */ 687 *range = NULL; 688 689 mm = bo->notifier.mm; 690 if (unlikely(!mm)) { 691 DRM_DEBUG_DRIVER("BO is not registered?\n"); 692 return -EFAULT; 693 } 694 695 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 696 return -ESRCH; 697 698 mmap_read_lock(mm); 699 vma = vma_lookup(mm, start); 700 if (unlikely(!vma)) { 701 r = -EFAULT; 702 goto out_unlock; 703 } 704 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 705 vma->vm_file)) { 706 r = -EPERM; 707 goto out_unlock; 708 } 709 710 readonly = amdgpu_ttm_tt_is_readonly(ttm); 711 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, 712 readonly, NULL, pages, range); 713 out_unlock: 714 mmap_read_unlock(mm); 715 if (r) 716 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 717 718 mmput(mm); 719 720 return r; 721 } 722 723 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations 724 */ 725 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 726 struct hmm_range *range) 727 { 728 struct amdgpu_ttm_tt *gtt = (void *)ttm; 729 730 if (gtt && gtt->userptr && range) 731 amdgpu_hmm_range_get_pages_done(range); 732 } 733 734 /* 735 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change 736 * Check if the pages backing this ttm range have been invalidated 737 * 738 * Returns: true if pages are still valid 739 */ 740 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 741 struct hmm_range *range) 742 { 743 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 744 745 if (!gtt || !gtt->userptr || !range) 746 return false; 747 748 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 749 gtt->userptr, ttm->num_pages); 750 751 WARN_ONCE(!range->hmm_pfns, "No user pages to check\n"); 752 753 return !amdgpu_hmm_range_get_pages_done(range); 754 } 755 #endif 756 757 /* 758 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 759 * 760 * Called by amdgpu_cs_list_validate(). This creates the page list 761 * that backs user memory and will ultimately be mapped into the device 762 * address space. 763 */ 764 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct vm_page **pages) 765 { 766 unsigned long i; 767 768 for (i = 0; i < ttm->num_pages; ++i) 769 ttm->pages[i] = pages ? pages[i] : NULL; 770 } 771 772 /* 773 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 774 * 775 * Called by amdgpu_ttm_backend_bind() 776 **/ 777 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 778 struct ttm_tt *ttm) 779 { 780 STUB(); 781 return -ENOSYS; 782 #ifdef notyet 783 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 784 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 785 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 786 enum dma_data_direction direction = write ? 787 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 788 int r; 789 790 /* Allocate an SG array and squash pages into it */ 791 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 792 (u64)ttm->num_pages << PAGE_SHIFT, 793 GFP_KERNEL); 794 if (r) 795 goto release_sg; 796 797 /* Map SG to device */ 798 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 799 if (r) 800 goto release_sg_table; 801 802 /* convert SG to linear array of pages and dma addresses */ 803 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 804 ttm->num_pages); 805 806 return 0; 807 808 release_sg_table: 809 sg_free_table(ttm->sg); 810 release_sg: 811 kfree(ttm->sg); 812 ttm->sg = NULL; 813 return r; 814 #endif 815 } 816 817 /* 818 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 819 */ 820 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 821 struct ttm_tt *ttm) 822 { 823 STUB(); 824 #ifdef notyet 825 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 826 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 827 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 828 enum dma_data_direction direction = write ? 829 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 830 831 /* double check that we don't free the table twice */ 832 if (!ttm->sg || !ttm->sg->sgl) 833 return; 834 835 /* unmap the pages mapped to the device */ 836 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 837 sg_free_table(ttm->sg); 838 #endif 839 } 840 841 /* 842 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ... 843 * MQDn+CtrlStackn where n is the number of XCCs per partition. 844 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD 845 * and uses memory type default, UC. The rest of pages_per_xcc are 846 * Ctrl stack and modify their memory type to NC. 847 */ 848 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 849 struct ttm_tt *ttm, uint64_t flags) 850 { 851 struct amdgpu_ttm_tt *gtt = (void *)ttm; 852 uint64_t total_pages = ttm->num_pages; 853 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 854 uint64_t page_idx, pages_per_xcc; 855 int i; 856 uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 857 AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 858 859 pages_per_xcc = total_pages; 860 do_div(pages_per_xcc, num_xcc); 861 862 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 863 /* MQD page: use default flags */ 864 amdgpu_gart_bind(adev, 865 gtt->offset + (page_idx << PAGE_SHIFT), 866 1, >t->ttm.dma_address[page_idx], flags); 867 /* 868 * Ctrl pages - modify the memory type to NC (ctrl_flags) from 869 * the second page of the BO onward. 870 */ 871 amdgpu_gart_bind(adev, 872 gtt->offset + ((page_idx + 1) << PAGE_SHIFT), 873 pages_per_xcc - 1, 874 >t->ttm.dma_address[page_idx + 1], 875 ctrl_flags); 876 } 877 } 878 879 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 880 struct ttm_buffer_object *tbo, 881 uint64_t flags) 882 { 883 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 884 struct ttm_tt *ttm = tbo->ttm; 885 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 886 887 if (amdgpu_bo_encrypted(abo)) 888 flags |= AMDGPU_PTE_TMZ; 889 890 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 891 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags); 892 } else { 893 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 894 gtt->ttm.dma_address, flags); 895 } 896 gtt->bound = true; 897 } 898 899 /* 900 * amdgpu_ttm_backend_bind - Bind GTT memory 901 * 902 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 903 * This handles binding GTT memory to the device address space. 904 */ 905 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 906 struct ttm_tt *ttm, 907 struct ttm_resource *bo_mem) 908 { 909 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 910 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 911 uint64_t flags; 912 int r; 913 914 if (!bo_mem) 915 return -EINVAL; 916 917 if (gtt->bound) 918 return 0; 919 920 if (gtt->userptr) { 921 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 922 if (r) { 923 DRM_ERROR("failed to pin userptr\n"); 924 return r; 925 } 926 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 927 if (!ttm->sg) { 928 struct dma_buf_attachment *attach; 929 struct sg_table *sgt; 930 931 attach = gtt->gobj->import_attach; 932 #ifdef notyet 933 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 934 if (IS_ERR(sgt)) 935 return PTR_ERR(sgt); 936 #else 937 STUB(); 938 return -ENOSYS; 939 #endif 940 941 ttm->sg = sgt; 942 } 943 944 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 945 ttm->num_pages); 946 } 947 948 if (!ttm->num_pages) { 949 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 950 ttm->num_pages, bo_mem, ttm); 951 } 952 953 if (bo_mem->mem_type != TTM_PL_TT || 954 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 955 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 956 return 0; 957 } 958 959 /* compute PTE flags relevant to this BO memory */ 960 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 961 962 /* bind pages into GART page tables */ 963 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 964 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 965 gtt->ttm.dma_address, flags); 966 gtt->bound = true; 967 return 0; 968 } 969 970 /* 971 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 972 * through AGP or GART aperture. 973 * 974 * If bo is accessible through AGP aperture, then use AGP aperture 975 * to access bo; otherwise allocate logical space in GART aperture 976 * and map bo to GART aperture. 977 */ 978 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 979 { 980 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 981 struct ttm_operation_ctx ctx = { false, false }; 982 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 983 struct ttm_placement placement; 984 struct ttm_place placements; 985 struct ttm_resource *tmp; 986 uint64_t addr, flags; 987 int r; 988 989 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 990 return 0; 991 992 addr = amdgpu_gmc_agp_addr(bo); 993 if (addr != AMDGPU_BO_INVALID_OFFSET) { 994 bo->resource->start = addr >> PAGE_SHIFT; 995 return 0; 996 } 997 998 /* allocate GART space */ 999 placement.num_placement = 1; 1000 placement.placement = &placements; 1001 placement.num_busy_placement = 1; 1002 placement.busy_placement = &placements; 1003 placements.fpfn = 0; 1004 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1005 placements.mem_type = TTM_PL_TT; 1006 placements.flags = bo->resource->placement; 1007 1008 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1009 if (unlikely(r)) 1010 return r; 1011 1012 /* compute PTE flags for this buffer object */ 1013 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 1014 1015 /* Bind pages */ 1016 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 1017 amdgpu_ttm_gart_bind(adev, bo, flags); 1018 amdgpu_gart_invalidate_tlb(adev); 1019 ttm_resource_free(bo, &bo->resource); 1020 ttm_bo_assign_mem(bo, tmp); 1021 1022 return 0; 1023 } 1024 1025 /* 1026 * amdgpu_ttm_recover_gart - Rebind GTT pages 1027 * 1028 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1029 * rebind GTT pages during a GPU reset. 1030 */ 1031 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1032 { 1033 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1034 uint64_t flags; 1035 1036 if (!tbo->ttm) 1037 return; 1038 1039 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1040 amdgpu_ttm_gart_bind(adev, tbo, flags); 1041 } 1042 1043 /* 1044 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1045 * 1046 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1047 * ttm_tt_destroy(). 1048 */ 1049 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1050 struct ttm_tt *ttm) 1051 { 1052 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1053 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1054 1055 /* if the pages have userptr pinning then clear that first */ 1056 if (gtt->userptr) { 1057 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1058 } else if (ttm->sg && gtt->gobj->import_attach) { 1059 struct dma_buf_attachment *attach; 1060 1061 attach = gtt->gobj->import_attach; 1062 #ifdef notyet 1063 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1064 #else 1065 STUB(); 1066 #endif 1067 ttm->sg = NULL; 1068 } 1069 1070 if (!gtt->bound) 1071 return; 1072 1073 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1074 return; 1075 1076 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1077 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1078 gtt->bound = false; 1079 } 1080 1081 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1082 struct ttm_tt *ttm) 1083 { 1084 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1085 1086 #ifdef notyet 1087 if (gtt->usertask) 1088 put_task_struct(gtt->usertask); 1089 #endif 1090 1091 ttm_tt_fini(>t->ttm); 1092 kfree(gtt); 1093 } 1094 1095 /** 1096 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1097 * 1098 * @bo: The buffer object to create a GTT ttm_tt object around 1099 * @page_flags: Page flags to be added to the ttm_tt object 1100 * 1101 * Called by ttm_tt_create(). 1102 */ 1103 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1104 uint32_t page_flags) 1105 { 1106 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1107 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1108 struct amdgpu_ttm_tt *gtt; 1109 enum ttm_caching caching; 1110 1111 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1112 if (!gtt) 1113 return NULL; 1114 1115 gtt->gobj = &bo->base; 1116 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) 1117 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 1118 else 1119 gtt->pool_id = abo->xcp_id; 1120 1121 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1122 caching = ttm_write_combined; 1123 else 1124 caching = ttm_cached; 1125 1126 /* allocate space for the uninitialized page entries */ 1127 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1128 kfree(gtt); 1129 return NULL; 1130 } 1131 return >t->ttm; 1132 } 1133 1134 /* 1135 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1136 * 1137 * Map the pages of a ttm_tt object to an address space visible 1138 * to the underlying device. 1139 */ 1140 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1141 struct ttm_tt *ttm, 1142 struct ttm_operation_ctx *ctx) 1143 { 1144 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1145 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1146 struct ttm_pool *pool; 1147 pgoff_t i; 1148 int ret; 1149 1150 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1151 if (gtt->userptr) { 1152 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1153 if (!ttm->sg) 1154 return -ENOMEM; 1155 return 0; 1156 } 1157 1158 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1159 return 0; 1160 1161 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1162 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1163 else 1164 pool = &adev->mman.bdev.pool; 1165 ret = ttm_pool_alloc(pool, ttm, ctx); 1166 if (ret) 1167 return ret; 1168 1169 #ifdef notyet 1170 for (i = 0; i < ttm->num_pages; ++i) 1171 ttm->pages[i]->mapping = bdev->dev_mapping; 1172 #endif 1173 1174 return 0; 1175 } 1176 1177 /* 1178 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1179 * 1180 * Unmaps pages of a ttm_tt object from the device address space and 1181 * unpopulates the page array backing it. 1182 */ 1183 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1184 struct ttm_tt *ttm) 1185 { 1186 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1187 struct amdgpu_device *adev; 1188 struct ttm_pool *pool; 1189 pgoff_t i; 1190 struct vm_page *page; 1191 1192 amdgpu_ttm_backend_unbind(bdev, ttm); 1193 1194 if (gtt->userptr) { 1195 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1196 kfree(ttm->sg); 1197 ttm->sg = NULL; 1198 return; 1199 } 1200 1201 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1202 return; 1203 1204 for (i = 0; i < ttm->num_pages; ++i) { 1205 page = ttm->pages[i]; 1206 if (unlikely(page == NULL)) 1207 continue; 1208 pmap_page_protect(page, PROT_NONE); 1209 } 1210 1211 adev = amdgpu_ttm_adev(bdev); 1212 1213 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1214 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1215 else 1216 pool = &adev->mman.bdev.pool; 1217 1218 return ttm_pool_free(pool, ttm); 1219 } 1220 1221 /** 1222 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1223 * task 1224 * 1225 * @tbo: The ttm_buffer_object that contains the userptr 1226 * @user_addr: The returned value 1227 */ 1228 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1229 uint64_t *user_addr) 1230 { 1231 struct amdgpu_ttm_tt *gtt; 1232 1233 if (!tbo->ttm) 1234 return -EINVAL; 1235 1236 gtt = (void *)tbo->ttm; 1237 *user_addr = gtt->userptr; 1238 return 0; 1239 } 1240 1241 /** 1242 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1243 * task 1244 * 1245 * @bo: The ttm_buffer_object to bind this userptr to 1246 * @addr: The address in the current tasks VM space to use 1247 * @flags: Requirements of userptr object. 1248 * 1249 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to 1250 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to 1251 * initialize GPU VM for a KFD process. 1252 */ 1253 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1254 uint64_t addr, uint32_t flags) 1255 { 1256 struct amdgpu_ttm_tt *gtt; 1257 1258 if (!bo->ttm) { 1259 /* TODO: We want a separate TTM object type for userptrs */ 1260 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1261 if (bo->ttm == NULL) 1262 return -ENOMEM; 1263 } 1264 1265 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1266 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1267 1268 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 1269 gtt->userptr = addr; 1270 gtt->userflags = flags; 1271 1272 #ifdef notyet 1273 if (gtt->usertask) 1274 put_task_struct(gtt->usertask); 1275 gtt->usertask = current->group_leader; 1276 get_task_struct(gtt->usertask); 1277 #endif 1278 1279 return 0; 1280 } 1281 1282 /* 1283 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1284 */ 1285 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1286 { 1287 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1288 1289 if (gtt == NULL) 1290 return NULL; 1291 1292 if (gtt->usertask == NULL) 1293 return NULL; 1294 1295 #ifdef notyet 1296 return gtt->usertask->mm; 1297 #else 1298 STUB(); 1299 return NULL; 1300 #endif 1301 } 1302 1303 /* 1304 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1305 * address range for the current task. 1306 * 1307 */ 1308 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1309 unsigned long end, unsigned long *userptr) 1310 { 1311 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1312 unsigned long size; 1313 1314 if (gtt == NULL || !gtt->userptr) 1315 return false; 1316 1317 /* Return false if no part of the ttm_tt object lies within 1318 * the range 1319 */ 1320 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1321 if (gtt->userptr > end || gtt->userptr + size <= start) 1322 return false; 1323 1324 if (userptr) 1325 *userptr = gtt->userptr; 1326 return true; 1327 } 1328 1329 /* 1330 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1331 */ 1332 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1333 { 1334 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1335 1336 if (gtt == NULL || !gtt->userptr) 1337 return false; 1338 1339 return true; 1340 } 1341 1342 /* 1343 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1344 */ 1345 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1346 { 1347 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1348 1349 if (gtt == NULL) 1350 return false; 1351 1352 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1353 } 1354 1355 /** 1356 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1357 * 1358 * @ttm: The ttm_tt object to compute the flags for 1359 * @mem: The memory registry backing this ttm_tt object 1360 * 1361 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1362 */ 1363 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1364 { 1365 uint64_t flags = 0; 1366 1367 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1368 flags |= AMDGPU_PTE_VALID; 1369 1370 if (mem && (mem->mem_type == TTM_PL_TT || 1371 mem->mem_type == AMDGPU_PL_DOORBELL || 1372 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1373 flags |= AMDGPU_PTE_SYSTEM; 1374 1375 if (ttm->caching == ttm_cached) 1376 flags |= AMDGPU_PTE_SNOOPED; 1377 } 1378 1379 if (mem && mem->mem_type == TTM_PL_VRAM && 1380 mem->bus.caching == ttm_cached) 1381 flags |= AMDGPU_PTE_SNOOPED; 1382 1383 return flags; 1384 } 1385 1386 /** 1387 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1388 * 1389 * @adev: amdgpu_device pointer 1390 * @ttm: The ttm_tt object to compute the flags for 1391 * @mem: The memory registry backing this ttm_tt object 1392 * 1393 * Figure out the flags to use for a VM PTE (Page Table Entry). 1394 */ 1395 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1396 struct ttm_resource *mem) 1397 { 1398 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1399 1400 flags |= adev->gart.gart_pte_flags; 1401 flags |= AMDGPU_PTE_READABLE; 1402 1403 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1404 flags |= AMDGPU_PTE_WRITEABLE; 1405 1406 return flags; 1407 } 1408 1409 /* 1410 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1411 * object. 1412 * 1413 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1414 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1415 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1416 * used to clean out a memory space. 1417 */ 1418 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1419 const struct ttm_place *place) 1420 { 1421 struct dma_resv_iter resv_cursor; 1422 struct dma_fence *f; 1423 1424 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1425 return ttm_bo_eviction_valuable(bo, place); 1426 1427 /* Swapout? */ 1428 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1429 return true; 1430 1431 if (bo->type == ttm_bo_type_kernel && 1432 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1433 return false; 1434 1435 /* If bo is a KFD BO, check if the bo belongs to the current process. 1436 * If true, then return false as any KFD process needs all its BOs to 1437 * be resident to run successfully 1438 */ 1439 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1440 DMA_RESV_USAGE_BOOKKEEP, f) { 1441 #ifdef notyet 1442 if (amdkfd_fence_check_mm(f, current->mm)) 1443 return false; 1444 #endif 1445 } 1446 1447 /* Preemptible BOs don't own system resources managed by the 1448 * driver (pages, VRAM, GART space). They point to resources 1449 * owned by someone else (e.g. pageable memory in user mode 1450 * or a DMABuf). They are used in a preemptible context so we 1451 * can guarantee no deadlocks and good QoS in case of MMU 1452 * notifiers or DMABuf move notifiers from the resource owner. 1453 */ 1454 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) 1455 return false; 1456 1457 if (bo->resource->mem_type == TTM_PL_TT && 1458 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1459 return false; 1460 1461 return ttm_bo_eviction_valuable(bo, place); 1462 } 1463 1464 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1465 void *buf, size_t size, bool write) 1466 { 1467 STUB(); 1468 #ifdef notyet 1469 while (size) { 1470 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1471 uint64_t bytes = 4 - (pos & 0x3); 1472 uint32_t shift = (pos & 0x3) * 8; 1473 uint32_t mask = 0xffffffff << shift; 1474 uint32_t value = 0; 1475 1476 if (size < bytes) { 1477 mask &= 0xffffffff >> (bytes - size) * 8; 1478 bytes = size; 1479 } 1480 1481 if (mask != 0xffffffff) { 1482 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1483 if (write) { 1484 value &= ~mask; 1485 value |= (*(uint32_t *)buf << shift) & mask; 1486 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1487 } else { 1488 value = (value & mask) >> shift; 1489 memcpy(buf, &value, bytes); 1490 } 1491 } else { 1492 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1493 } 1494 1495 pos += bytes; 1496 buf += bytes; 1497 size -= bytes; 1498 } 1499 #endif 1500 } 1501 1502 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1503 unsigned long offset, void *buf, 1504 int len, int write) 1505 { 1506 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1507 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1508 struct amdgpu_res_cursor src_mm; 1509 struct amdgpu_job *job; 1510 struct dma_fence *fence; 1511 uint64_t src_addr, dst_addr; 1512 unsigned int num_dw; 1513 int r, idx; 1514 1515 if (len != PAGE_SIZE) 1516 return -EINVAL; 1517 1518 if (!adev->mman.sdma_access_ptr) 1519 return -EACCES; 1520 1521 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1522 return -ENODEV; 1523 1524 if (write) 1525 memcpy(adev->mman.sdma_access_ptr, buf, len); 1526 1527 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1528 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, 1529 AMDGPU_FENCE_OWNER_UNDEFINED, 1530 num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1531 &job); 1532 if (r) 1533 goto out; 1534 1535 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1536 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + 1537 src_mm.start; 1538 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1539 if (write) 1540 swap(src_addr, dst_addr); 1541 1542 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, 1543 PAGE_SIZE, false); 1544 1545 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); 1546 WARN_ON(job->ibs[0].length_dw > num_dw); 1547 1548 fence = amdgpu_job_submit(job); 1549 1550 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1551 r = -ETIMEDOUT; 1552 dma_fence_put(fence); 1553 1554 if (!(r || write)) 1555 memcpy(buf, adev->mman.sdma_access_ptr, len); 1556 out: 1557 drm_dev_exit(idx); 1558 return r; 1559 } 1560 1561 /** 1562 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1563 * 1564 * @bo: The buffer object to read/write 1565 * @offset: Offset into buffer object 1566 * @buf: Secondary buffer to write/read from 1567 * @len: Length in bytes of access 1568 * @write: true if writing 1569 * 1570 * This is used to access VRAM that backs a buffer object via MMIO 1571 * access for debugging purposes. 1572 */ 1573 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1574 unsigned long offset, void *buf, int len, 1575 int write) 1576 { 1577 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1578 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1579 struct amdgpu_res_cursor cursor; 1580 int ret = 0; 1581 1582 if (bo->resource->mem_type != TTM_PL_VRAM) 1583 return -EIO; 1584 1585 if (amdgpu_device_has_timeouts_enabled(adev) && 1586 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1587 return len; 1588 1589 amdgpu_res_first(bo->resource, offset, len, &cursor); 1590 while (cursor.remaining) { 1591 size_t count, size = cursor.size; 1592 loff_t pos = cursor.start; 1593 1594 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1595 size -= count; 1596 if (size) { 1597 /* using MM to access rest vram and handle un-aligned address */ 1598 pos += count; 1599 buf += count; 1600 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1601 } 1602 1603 ret += cursor.size; 1604 buf += cursor.size; 1605 amdgpu_res_next(&cursor, cursor.size); 1606 } 1607 1608 return ret; 1609 } 1610 1611 static void 1612 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1613 { 1614 amdgpu_bo_move_notify(bo, false, NULL); 1615 } 1616 1617 static struct ttm_device_funcs amdgpu_bo_driver = { 1618 .ttm_tt_create = &amdgpu_ttm_tt_create, 1619 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1620 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1621 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1622 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1623 .evict_flags = &amdgpu_evict_flags, 1624 .move = &amdgpu_bo_move, 1625 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1626 .release_notify = &amdgpu_bo_release_notify, 1627 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1628 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1629 .access_memory = &amdgpu_ttm_access_memory, 1630 }; 1631 1632 /* 1633 * Firmware Reservation functions 1634 */ 1635 /** 1636 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1637 * 1638 * @adev: amdgpu_device pointer 1639 * 1640 * free fw reserved vram if it has been reserved. 1641 */ 1642 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1643 { 1644 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1645 NULL, &adev->mman.fw_vram_usage_va); 1646 } 1647 1648 /* 1649 * Driver Reservation functions 1650 */ 1651 /** 1652 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram 1653 * 1654 * @adev: amdgpu_device pointer 1655 * 1656 * free drv reserved vram if it has been reserved. 1657 */ 1658 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev) 1659 { 1660 amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo, 1661 NULL, 1662 &adev->mman.drv_vram_usage_va); 1663 } 1664 1665 /** 1666 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1667 * 1668 * @adev: amdgpu_device pointer 1669 * 1670 * create bo vram reservation from fw. 1671 */ 1672 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1673 { 1674 uint64_t vram_size = adev->gmc.visible_vram_size; 1675 1676 adev->mman.fw_vram_usage_va = NULL; 1677 adev->mman.fw_vram_usage_reserved_bo = NULL; 1678 1679 if (adev->mman.fw_vram_usage_size == 0 || 1680 adev->mman.fw_vram_usage_size > vram_size) 1681 return 0; 1682 1683 return amdgpu_bo_create_kernel_at(adev, 1684 adev->mman.fw_vram_usage_start_offset, 1685 adev->mman.fw_vram_usage_size, 1686 &adev->mman.fw_vram_usage_reserved_bo, 1687 &adev->mman.fw_vram_usage_va); 1688 } 1689 1690 /** 1691 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver 1692 * 1693 * @adev: amdgpu_device pointer 1694 * 1695 * create bo vram reservation from drv. 1696 */ 1697 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev) 1698 { 1699 u64 vram_size = adev->gmc.visible_vram_size; 1700 1701 adev->mman.drv_vram_usage_va = NULL; 1702 adev->mman.drv_vram_usage_reserved_bo = NULL; 1703 1704 if (adev->mman.drv_vram_usage_size == 0 || 1705 adev->mman.drv_vram_usage_size > vram_size) 1706 return 0; 1707 1708 return amdgpu_bo_create_kernel_at(adev, 1709 adev->mman.drv_vram_usage_start_offset, 1710 adev->mman.drv_vram_usage_size, 1711 &adev->mman.drv_vram_usage_reserved_bo, 1712 &adev->mman.drv_vram_usage_va); 1713 } 1714 1715 /* 1716 * Memoy training reservation functions 1717 */ 1718 1719 /** 1720 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1721 * 1722 * @adev: amdgpu_device pointer 1723 * 1724 * free memory training reserved vram if it has been reserved. 1725 */ 1726 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1727 { 1728 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1729 1730 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1731 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1732 ctx->c2p_bo = NULL; 1733 1734 return 0; 1735 } 1736 1737 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev, 1738 uint32_t reserve_size) 1739 { 1740 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1741 1742 memset(ctx, 0, sizeof(*ctx)); 1743 1744 ctx->c2p_train_data_offset = 1745 ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1746 ctx->p2c_train_data_offset = 1747 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1748 ctx->train_data_size = 1749 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1750 1751 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1752 ctx->train_data_size, 1753 ctx->p2c_train_data_offset, 1754 ctx->c2p_train_data_offset); 1755 } 1756 1757 /* 1758 * reserve TMR memory at the top of VRAM which holds 1759 * IP Discovery data and is protected by PSP. 1760 */ 1761 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1762 { 1763 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1764 bool mem_train_support = false; 1765 uint32_t reserve_size = 0; 1766 int ret; 1767 1768 if (adev->bios && !amdgpu_sriov_vf(adev)) { 1769 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1770 mem_train_support = true; 1771 else 1772 DRM_DEBUG("memory training does not support!\n"); 1773 } 1774 1775 /* 1776 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1777 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1778 * 1779 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1780 * discovery data and G6 memory training data respectively 1781 */ 1782 if (adev->bios) 1783 reserve_size = 1784 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1785 1786 if (!adev->bios && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1787 reserve_size = max(reserve_size, (uint32_t)280 << 20); 1788 else if (!reserve_size) 1789 reserve_size = DISCOVERY_TMR_OFFSET; 1790 1791 if (mem_train_support) { 1792 /* reserve vram for mem train according to TMR location */ 1793 amdgpu_ttm_training_data_block_init(adev, reserve_size); 1794 ret = amdgpu_bo_create_kernel_at(adev, 1795 ctx->c2p_train_data_offset, 1796 ctx->train_data_size, 1797 &ctx->c2p_bo, 1798 NULL); 1799 if (ret) { 1800 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1801 amdgpu_ttm_training_reserve_vram_fini(adev); 1802 return ret; 1803 } 1804 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1805 } 1806 1807 if (!adev->gmc.is_app_apu) { 1808 ret = amdgpu_bo_create_kernel_at( 1809 adev, adev->gmc.real_vram_size - reserve_size, 1810 reserve_size, &adev->mman.fw_reserved_memory, NULL); 1811 if (ret) { 1812 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1813 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, 1814 NULL, NULL); 1815 return ret; 1816 } 1817 } else { 1818 DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n"); 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) 1825 { 1826 int i; 1827 1828 if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions) 1829 return 0; 1830 1831 adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions, 1832 sizeof(*adev->mman.ttm_pools), 1833 GFP_KERNEL); 1834 if (!adev->mman.ttm_pools) 1835 return -ENOMEM; 1836 1837 for (i = 0; i < adev->gmc.num_mem_partitions; i++) { 1838 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev, 1839 adev->gmc.mem_partitions[i].numa.node, 1840 false, false); 1841 } 1842 return 0; 1843 } 1844 1845 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) 1846 { 1847 int i; 1848 1849 if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools) 1850 return; 1851 1852 for (i = 0; i < adev->gmc.num_mem_partitions; i++) 1853 ttm_pool_fini(&adev->mman.ttm_pools[i]); 1854 1855 kfree(adev->mman.ttm_pools); 1856 adev->mman.ttm_pools = NULL; 1857 } 1858 1859 /* 1860 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1861 * gtt/vram related fields. 1862 * 1863 * This initializes all of the memory space pools that the TTM layer 1864 * will need such as the GTT space (system memory mapped to the device), 1865 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1866 * can be mapped per VMID. 1867 */ 1868 int amdgpu_ttm_init(struct amdgpu_device *adev) 1869 { 1870 uint64_t gtt_size; 1871 int r; 1872 1873 rw_init(&adev->mman.gtt_window_lock, "gttwin"); 1874 1875 dma_set_max_seg_size(adev->dev, UINT_MAX); 1876 /* No others user of address space so set it to 0 */ 1877 #ifdef notyet 1878 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1879 adev_to_drm(adev)->anon_inode->i_mapping, 1880 adev_to_drm(adev)->vma_offset_manager, 1881 adev->need_swiotlb, 1882 dma_addressing_limited(adev->dev)); 1883 #else 1884 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1885 /*adev_to_drm(adev)->anon_inode->i_mapping*/NULL, 1886 adev_to_drm(adev)->vma_offset_manager, 1887 adev->need_swiotlb, 1888 dma_addressing_limited(adev->dev)); 1889 #endif 1890 if (r) { 1891 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1892 return r; 1893 } 1894 1895 r = amdgpu_ttm_pools_init(adev); 1896 if (r) { 1897 DRM_ERROR("failed to init ttm pools(%d).\n", r); 1898 return r; 1899 } 1900 adev->mman.bdev.iot = adev->iot; 1901 adev->mman.bdev.memt = adev->memt; 1902 adev->mman.bdev.dmat = adev->dmat; 1903 adev->mman.initialized = true; 1904 1905 /* Initialize VRAM pool with all of VRAM divided into pages */ 1906 r = amdgpu_vram_mgr_init(adev); 1907 if (r) { 1908 DRM_ERROR("Failed initializing VRAM heap.\n"); 1909 return r; 1910 } 1911 1912 /* Change the size here instead of the init above so only lpfn is affected */ 1913 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1914 #if defined(CONFIG_64BIT) && defined(__linux__) 1915 #ifdef CONFIG_X86 1916 if (adev->gmc.xgmi.connected_to_cpu) 1917 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1918 adev->gmc.visible_vram_size); 1919 1920 else if (adev->gmc.is_app_apu) 1921 DRM_DEBUG_DRIVER( 1922 "No need to ioremap when real vram size is 0\n"); 1923 else 1924 #endif 1925 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1926 adev->gmc.visible_vram_size); 1927 #else 1928 if (bus_space_map(adev->memt, adev->gmc.aper_base, 1929 adev->gmc.visible_vram_size, 1930 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE, 1931 &adev->mman.aper_bsh)) { 1932 adev->mman.aper_base_kaddr = NULL; 1933 } else { 1934 adev->mman.aper_base_kaddr = bus_space_vaddr(adev->memt, 1935 adev->mman.aper_bsh); 1936 } 1937 #endif 1938 1939 /* 1940 *The reserved vram for firmware must be pinned to the specified 1941 *place on the VRAM, so reserve it early. 1942 */ 1943 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1944 if (r) 1945 return r; 1946 1947 /* 1948 *The reserved vram for driver must be pinned to the specified 1949 *place on the VRAM, so reserve it early. 1950 */ 1951 r = amdgpu_ttm_drv_reserve_vram_init(adev); 1952 if (r) 1953 return r; 1954 1955 /* 1956 * only NAVI10 and onwards ASIC support for IP discovery. 1957 * If IP discovery enabled, a block of memory should be 1958 * reserved for IP discovey. 1959 */ 1960 if (adev->mman.discovery_bin) { 1961 r = amdgpu_ttm_reserve_tmr(adev); 1962 if (r) 1963 return r; 1964 } 1965 1966 /* allocate memory as required for VGA 1967 * This is used for VGA emulation and pre-OS scanout buffers to 1968 * avoid display artifacts while transitioning between pre-OS 1969 * and driver. 1970 */ 1971 if (!adev->gmc.is_app_apu) { 1972 r = amdgpu_bo_create_kernel_at(adev, 0, 1973 adev->mman.stolen_vga_size, 1974 &adev->mman.stolen_vga_memory, 1975 NULL); 1976 if (r) 1977 return r; 1978 1979 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1980 adev->mman.stolen_extended_size, 1981 &adev->mman.stolen_extended_memory, 1982 NULL); 1983 1984 if (r) 1985 return r; 1986 1987 r = amdgpu_bo_create_kernel_at(adev, 1988 adev->mman.stolen_reserved_offset, 1989 adev->mman.stolen_reserved_size, 1990 &adev->mman.stolen_reserved_memory, 1991 NULL); 1992 if (r) 1993 return r; 1994 } else { 1995 DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n"); 1996 } 1997 1998 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1999 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024))); 2000 2001 /* Compute GTT size, either based on TTM limit 2002 * or whatever the user passed on module init. 2003 */ 2004 if (amdgpu_gtt_size == -1) 2005 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; 2006 else 2007 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 2008 2009 /* Initialize GTT memory pool */ 2010 r = amdgpu_gtt_mgr_init(adev, gtt_size); 2011 if (r) { 2012 DRM_ERROR("Failed initializing GTT heap.\n"); 2013 return r; 2014 } 2015 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 2016 (unsigned int)(gtt_size / (1024 * 1024))); 2017 2018 /* Initiailize doorbell pool on PCI BAR */ 2019 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); 2020 if (r) { 2021 DRM_ERROR("Failed initializing doorbell heap.\n"); 2022 return r; 2023 } 2024 2025 /* Create a boorbell page for kernel usages */ 2026 r = amdgpu_doorbell_create_kernel_doorbells(adev); 2027 if (r) { 2028 DRM_ERROR("Failed to initialize kernel doorbells.\n"); 2029 return r; 2030 } 2031 2032 /* Initialize preemptible memory pool */ 2033 r = amdgpu_preempt_mgr_init(adev); 2034 if (r) { 2035 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 2036 return r; 2037 } 2038 2039 /* Initialize various on-chip memory pools */ 2040 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 2041 if (r) { 2042 DRM_ERROR("Failed initializing GDS heap.\n"); 2043 return r; 2044 } 2045 2046 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 2047 if (r) { 2048 DRM_ERROR("Failed initializing gws heap.\n"); 2049 return r; 2050 } 2051 2052 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 2053 if (r) { 2054 DRM_ERROR("Failed initializing oa heap.\n"); 2055 return r; 2056 } 2057 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 2058 AMDGPU_GEM_DOMAIN_GTT, 2059 &adev->mman.sdma_access_bo, NULL, 2060 &adev->mman.sdma_access_ptr)) 2061 DRM_WARN("Debug VRAM access will use slowpath MM access\n"); 2062 2063 return 0; 2064 } 2065 2066 /* 2067 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2068 */ 2069 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2070 { 2071 int idx; 2072 2073 if (!adev->mman.initialized) 2074 return; 2075 2076 amdgpu_ttm_pools_fini(adev); 2077 2078 amdgpu_ttm_training_reserve_vram_fini(adev); 2079 /* return the stolen vga memory back to VRAM */ 2080 if (!adev->gmc.is_app_apu) { 2081 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 2082 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 2083 /* return the FW reserved memory back to VRAM */ 2084 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, 2085 NULL); 2086 if (adev->mman.stolen_reserved_size) 2087 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 2088 NULL, NULL); 2089 } 2090 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 2091 &adev->mman.sdma_access_ptr); 2092 amdgpu_ttm_fw_reserve_vram_fini(adev); 2093 amdgpu_ttm_drv_reserve_vram_fini(adev); 2094 2095 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 2096 2097 #ifdef __linux__ 2098 if (adev->mman.aper_base_kaddr) 2099 iounmap(adev->mman.aper_base_kaddr); 2100 #else 2101 if (adev->mman.aper_base_kaddr) 2102 bus_space_unmap(adev->memt, adev->mman.aper_bsh, 2103 adev->gmc.visible_vram_size); 2104 #endif 2105 adev->mman.aper_base_kaddr = NULL; 2106 2107 drm_dev_exit(idx); 2108 } 2109 2110 amdgpu_vram_mgr_fini(adev); 2111 amdgpu_gtt_mgr_fini(adev); 2112 amdgpu_preempt_mgr_fini(adev); 2113 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2114 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2115 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2116 ttm_device_fini(&adev->mman.bdev); 2117 adev->mman.initialized = false; 2118 DRM_INFO("amdgpu: ttm finalized\n"); 2119 } 2120 2121 /** 2122 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2123 * 2124 * @adev: amdgpu_device pointer 2125 * @enable: true when we can use buffer functions. 2126 * 2127 * Enable/disable use of buffer functions during suspend/resume. This should 2128 * only be called at bootup or when userspace isn't running. 2129 */ 2130 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2131 { 2132 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2133 uint64_t size; 2134 int r; 2135 2136 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 2137 adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu) 2138 return; 2139 2140 if (enable) { 2141 struct amdgpu_ring *ring; 2142 struct drm_gpu_scheduler *sched; 2143 2144 ring = adev->mman.buffer_funcs_ring; 2145 sched = &ring->sched; 2146 r = drm_sched_entity_init(&adev->mman.high_pr, 2147 DRM_SCHED_PRIORITY_KERNEL, &sched, 2148 1, NULL); 2149 if (r) { 2150 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2151 r); 2152 return; 2153 } 2154 2155 r = drm_sched_entity_init(&adev->mman.low_pr, 2156 DRM_SCHED_PRIORITY_NORMAL, &sched, 2157 1, NULL); 2158 if (r) { 2159 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2160 r); 2161 goto error_free_entity; 2162 } 2163 } else { 2164 drm_sched_entity_destroy(&adev->mman.high_pr); 2165 drm_sched_entity_destroy(&adev->mman.low_pr); 2166 dma_fence_put(man->move); 2167 man->move = NULL; 2168 } 2169 2170 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2171 if (enable) 2172 size = adev->gmc.real_vram_size; 2173 else 2174 size = adev->gmc.visible_vram_size; 2175 man->size = size; 2176 adev->mman.buffer_funcs_enabled = enable; 2177 2178 return; 2179 2180 error_free_entity: 2181 drm_sched_entity_destroy(&adev->mman.high_pr); 2182 } 2183 2184 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 2185 bool direct_submit, 2186 unsigned int num_dw, 2187 struct dma_resv *resv, 2188 bool vm_needs_flush, 2189 struct amdgpu_job **job, 2190 bool delayed) 2191 { 2192 enum amdgpu_ib_pool_type pool = direct_submit ? 2193 AMDGPU_IB_POOL_DIRECT : 2194 AMDGPU_IB_POOL_DELAYED; 2195 int r; 2196 struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr : 2197 &adev->mman.high_pr; 2198 r = amdgpu_job_alloc_with_ib(adev, entity, 2199 AMDGPU_FENCE_OWNER_UNDEFINED, 2200 num_dw * 4, pool, job); 2201 if (r) 2202 return r; 2203 2204 if (vm_needs_flush) { 2205 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 2206 adev->gmc.pdb0_bo : 2207 adev->gart.bo); 2208 (*job)->vm_needs_flush = true; 2209 } 2210 if (!resv) 2211 return 0; 2212 2213 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, 2214 DMA_RESV_USAGE_BOOKKEEP); 2215 } 2216 2217 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2218 uint64_t dst_offset, uint32_t byte_count, 2219 struct dma_resv *resv, 2220 struct dma_fence **fence, bool direct_submit, 2221 bool vm_needs_flush, bool tmz) 2222 { 2223 struct amdgpu_device *adev = ring->adev; 2224 unsigned int num_loops, num_dw; 2225 struct amdgpu_job *job; 2226 uint32_t max_bytes; 2227 unsigned int i; 2228 int r; 2229 2230 if (!direct_submit && !ring->sched.ready) { 2231 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2232 return -EINVAL; 2233 } 2234 2235 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2236 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2237 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2238 r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, 2239 resv, vm_needs_flush, &job, false); 2240 if (r) 2241 return r; 2242 2243 for (i = 0; i < num_loops; i++) { 2244 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2245 2246 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2247 dst_offset, cur_size_in_bytes, tmz); 2248 2249 src_offset += cur_size_in_bytes; 2250 dst_offset += cur_size_in_bytes; 2251 byte_count -= cur_size_in_bytes; 2252 } 2253 2254 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2255 WARN_ON(job->ibs[0].length_dw > num_dw); 2256 if (direct_submit) 2257 r = amdgpu_job_submit_direct(job, ring, fence); 2258 else 2259 *fence = amdgpu_job_submit(job); 2260 if (r) 2261 goto error_free; 2262 2263 return r; 2264 2265 error_free: 2266 amdgpu_job_free(job); 2267 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2268 return r; 2269 } 2270 2271 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, 2272 uint64_t dst_addr, uint32_t byte_count, 2273 struct dma_resv *resv, 2274 struct dma_fence **fence, 2275 bool vm_needs_flush, bool delayed) 2276 { 2277 struct amdgpu_device *adev = ring->adev; 2278 unsigned int num_loops, num_dw; 2279 struct amdgpu_job *job; 2280 uint32_t max_bytes; 2281 unsigned int i; 2282 int r; 2283 2284 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2285 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2286 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2287 r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, 2288 &job, delayed); 2289 if (r) 2290 return r; 2291 2292 for (i = 0; i < num_loops; i++) { 2293 uint32_t cur_size = min(byte_count, max_bytes); 2294 2295 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2296 cur_size); 2297 2298 dst_addr += cur_size; 2299 byte_count -= cur_size; 2300 } 2301 2302 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2303 WARN_ON(job->ibs[0].length_dw > num_dw); 2304 *fence = amdgpu_job_submit(job); 2305 return 0; 2306 } 2307 2308 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2309 uint32_t src_data, 2310 struct dma_resv *resv, 2311 struct dma_fence **f, 2312 bool delayed) 2313 { 2314 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2315 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2316 struct dma_fence *fence = NULL; 2317 struct amdgpu_res_cursor dst; 2318 int r; 2319 2320 if (!adev->mman.buffer_funcs_enabled) { 2321 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2322 return -EINVAL; 2323 } 2324 2325 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2326 2327 mutex_lock(&adev->mman.gtt_window_lock); 2328 while (dst.remaining) { 2329 struct dma_fence *next; 2330 uint64_t cur_size, to; 2331 2332 /* Never fill more than 256MiB at once to avoid timeouts */ 2333 cur_size = min(dst.size, 256ULL << 20); 2334 2335 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, 2336 1, ring, false, &cur_size, &to); 2337 if (r) 2338 goto error; 2339 2340 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, 2341 &next, true, delayed); 2342 if (r) 2343 goto error; 2344 2345 dma_fence_put(fence); 2346 fence = next; 2347 2348 amdgpu_res_next(&dst, cur_size); 2349 } 2350 error: 2351 mutex_unlock(&adev->mman.gtt_window_lock); 2352 if (f) 2353 *f = dma_fence_get(fence); 2354 dma_fence_put(fence); 2355 return r; 2356 } 2357 2358 /** 2359 * amdgpu_ttm_evict_resources - evict memory buffers 2360 * @adev: amdgpu device object 2361 * @mem_type: evicted BO's memory type 2362 * 2363 * Evicts all @mem_type buffers on the lru list of the memory type. 2364 * 2365 * Returns: 2366 * 0 for success or a negative error code on failure. 2367 */ 2368 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2369 { 2370 struct ttm_resource_manager *man; 2371 2372 switch (mem_type) { 2373 case TTM_PL_VRAM: 2374 case TTM_PL_TT: 2375 case AMDGPU_PL_GWS: 2376 case AMDGPU_PL_GDS: 2377 case AMDGPU_PL_OA: 2378 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2379 break; 2380 default: 2381 DRM_ERROR("Trying to evict invalid memory type\n"); 2382 return -EINVAL; 2383 } 2384 2385 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2386 } 2387 2388 #if defined(CONFIG_DEBUG_FS) 2389 2390 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2391 { 2392 struct amdgpu_device *adev = m->private; 2393 2394 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2395 } 2396 2397 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2398 2399 /* 2400 * amdgpu_ttm_vram_read - Linear read access to VRAM 2401 * 2402 * Accesses VRAM via MMIO for debugging purposes. 2403 */ 2404 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2405 size_t size, loff_t *pos) 2406 { 2407 struct amdgpu_device *adev = file_inode(f)->i_private; 2408 ssize_t result = 0; 2409 2410 if (size & 0x3 || *pos & 0x3) 2411 return -EINVAL; 2412 2413 if (*pos >= adev->gmc.mc_vram_size) 2414 return -ENXIO; 2415 2416 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2417 while (size) { 2418 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2419 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2420 2421 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2422 if (copy_to_user(buf, value, bytes)) 2423 return -EFAULT; 2424 2425 result += bytes; 2426 buf += bytes; 2427 *pos += bytes; 2428 size -= bytes; 2429 } 2430 2431 return result; 2432 } 2433 2434 /* 2435 * amdgpu_ttm_vram_write - Linear write access to VRAM 2436 * 2437 * Accesses VRAM via MMIO for debugging purposes. 2438 */ 2439 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2440 size_t size, loff_t *pos) 2441 { 2442 struct amdgpu_device *adev = file_inode(f)->i_private; 2443 ssize_t result = 0; 2444 int r; 2445 2446 if (size & 0x3 || *pos & 0x3) 2447 return -EINVAL; 2448 2449 if (*pos >= adev->gmc.mc_vram_size) 2450 return -ENXIO; 2451 2452 while (size) { 2453 uint32_t value; 2454 2455 if (*pos >= adev->gmc.mc_vram_size) 2456 return result; 2457 2458 r = get_user(value, (uint32_t *)buf); 2459 if (r) 2460 return r; 2461 2462 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2463 2464 result += 4; 2465 buf += 4; 2466 *pos += 4; 2467 size -= 4; 2468 } 2469 2470 return result; 2471 } 2472 2473 static const struct file_operations amdgpu_ttm_vram_fops = { 2474 .owner = THIS_MODULE, 2475 .read = amdgpu_ttm_vram_read, 2476 .write = amdgpu_ttm_vram_write, 2477 .llseek = default_llseek, 2478 }; 2479 2480 /* 2481 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2482 * 2483 * This function is used to read memory that has been mapped to the 2484 * GPU and the known addresses are not physical addresses but instead 2485 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2486 */ 2487 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2488 size_t size, loff_t *pos) 2489 { 2490 struct amdgpu_device *adev = file_inode(f)->i_private; 2491 struct iommu_domain *dom; 2492 ssize_t result = 0; 2493 int r; 2494 2495 /* retrieve the IOMMU domain if any for this device */ 2496 dom = iommu_get_domain_for_dev(adev->dev); 2497 2498 while (size) { 2499 phys_addr_t addr = *pos & LINUX_PAGE_MASK; 2500 loff_t off = *pos & ~LINUX_PAGE_MASK; 2501 size_t bytes = PAGE_SIZE - off; 2502 unsigned long pfn; 2503 struct vm_page *p; 2504 void *ptr; 2505 2506 bytes = min(bytes, size); 2507 2508 /* Translate the bus address to a physical address. If 2509 * the domain is NULL it means there is no IOMMU active 2510 * and the address translation is the identity 2511 */ 2512 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2513 2514 pfn = addr >> PAGE_SHIFT; 2515 if (!pfn_valid(pfn)) 2516 return -EPERM; 2517 2518 p = pfn_to_page(pfn); 2519 #ifdef notyet 2520 if (p->mapping != adev->mman.bdev.dev_mapping) 2521 return -EPERM; 2522 #else 2523 STUB(); 2524 #endif 2525 2526 ptr = kmap_local_page(p); 2527 r = copy_to_user(buf, ptr + off, bytes); 2528 kunmap_local(ptr); 2529 if (r) 2530 return -EFAULT; 2531 2532 size -= bytes; 2533 *pos += bytes; 2534 result += bytes; 2535 } 2536 2537 return result; 2538 } 2539 2540 /* 2541 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2542 * 2543 * This function is used to write memory that has been mapped to the 2544 * GPU and the known addresses are not physical addresses but instead 2545 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2546 */ 2547 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2548 size_t size, loff_t *pos) 2549 { 2550 struct amdgpu_device *adev = file_inode(f)->i_private; 2551 struct iommu_domain *dom; 2552 ssize_t result = 0; 2553 int r; 2554 2555 dom = iommu_get_domain_for_dev(adev->dev); 2556 2557 while (size) { 2558 phys_addr_t addr = *pos & LINUX_PAGE_MASK; 2559 loff_t off = *pos & ~LINUX_PAGE_MASK; 2560 size_t bytes = PAGE_SIZE - off; 2561 unsigned long pfn; 2562 struct vm_page *p; 2563 void *ptr; 2564 2565 bytes = min(bytes, size); 2566 2567 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2568 2569 pfn = addr >> PAGE_SHIFT; 2570 if (!pfn_valid(pfn)) 2571 return -EPERM; 2572 2573 p = pfn_to_page(pfn); 2574 #ifdef notyet 2575 if (p->mapping != adev->mman.bdev.dev_mapping) 2576 return -EPERM; 2577 #else 2578 STUB(); 2579 #endif 2580 2581 ptr = kmap_local_page(p); 2582 r = copy_from_user(ptr + off, buf, bytes); 2583 kunmap_local(ptr); 2584 if (r) 2585 return -EFAULT; 2586 2587 size -= bytes; 2588 *pos += bytes; 2589 result += bytes; 2590 } 2591 2592 return result; 2593 } 2594 2595 static const struct file_operations amdgpu_ttm_iomem_fops = { 2596 .owner = THIS_MODULE, 2597 .read = amdgpu_iomem_read, 2598 .write = amdgpu_iomem_write, 2599 .llseek = default_llseek 2600 }; 2601 2602 #endif 2603 2604 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2605 { 2606 #if defined(CONFIG_DEBUG_FS) 2607 struct drm_minor *minor = adev_to_drm(adev)->primary; 2608 struct dentry *root = minor->debugfs_root; 2609 2610 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2611 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2612 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2613 &amdgpu_ttm_iomem_fops); 2614 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2615 &amdgpu_ttm_page_pool_fops); 2616 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2617 TTM_PL_VRAM), 2618 root, "amdgpu_vram_mm"); 2619 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2620 TTM_PL_TT), 2621 root, "amdgpu_gtt_mm"); 2622 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2623 AMDGPU_PL_GDS), 2624 root, "amdgpu_gds_mm"); 2625 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2626 AMDGPU_PL_GWS), 2627 root, "amdgpu_gws_mm"); 2628 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2629 AMDGPU_PL_OA), 2630 root, "amdgpu_oa_mm"); 2631 2632 #endif 2633 } 2634