1 /* $OpenBSD: rlphy.c,v 1.34 2022/04/06 18:59:29 naddy Exp $ */
2
3 /*
4 * Copyright (c) 1998, 1999 Jason L. Wright (jason@thought.net)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Driver for the internal PHY found on RTL8139 based nics, based
31 * on drivers for the 'exphy' (Internal 3Com phys) and 'nsphy'
32 * (National Semiconductor DP83840).
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/device.h>
39 #include <sys/socket.h>
40 #include <sys/errno.h>
41
42 #include <machine/bus.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <netinet/in.h>
48 #include <netinet/if_ether.h>
49
50 #include <dev/mii/mii.h>
51 #include <dev/mii/miivar.h>
52 #include <dev/mii/miidevs.h>
53
54 #include <dev/ic/rtl81x9reg.h>
55
56 int rlphymatch(struct device *, void *, void *);
57 void rlphyattach(struct device *, struct device *, void *);
58
59 const struct cfattach rlphy_ca = {
60 sizeof(struct mii_softc), rlphymatch, rlphyattach, mii_phy_detach
61 };
62
63 struct cfdriver rlphy_cd = {
64 NULL, "rlphy", DV_DULL
65 };
66
67 int rlphy_service(struct mii_softc *, struct mii_data *, int);
68 void rlphy_status(struct mii_softc *);
69
70 const struct mii_phy_funcs rlphy_funcs = {
71 rlphy_service, rlphy_status, mii_phy_reset,
72 };
73
74 static const struct mii_phydesc rlphys[] = {
75 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8201L,
76 MII_STR_REALTEK_RTL8201L },
77 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8201E,
78 MII_STR_xxREALTEK_RTL8201E },
79 { MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP101,
80 MII_STR_ICPLUS_IP101 },
81
82 { 0, 0,
83 NULL },
84 };
85 int
rlphymatch(struct device * parent,void * match,void * aux)86 rlphymatch(struct device *parent, void *match, void *aux)
87 {
88 struct mii_attach_args *ma = aux;
89 char *devname;
90
91 devname = parent->dv_cfdata->cf_driver->cd_name;
92
93 if (mii_phy_match(ma, rlphys) != NULL)
94 return (10);
95
96 if (MII_OUI(ma->mii_id1, ma->mii_id2) != 0 ||
97 MII_MODEL(ma->mii_id2) != 0)
98 return (0);
99
100 if ((strcmp(devname, "re") != 0) &&
101 (strcmp(devname, "rl") != 0))
102 return (0);
103
104 /*
105 * A "real" phy should get preference, but on the 8139 there
106 * is no phyid register.
107 */
108 return (5);
109 }
110
111 void
rlphyattach(struct device * parent,struct device * self,void * aux)112 rlphyattach(struct device *parent, struct device *self, void *aux)
113 {
114 struct mii_softc *sc = (struct mii_softc *)self;
115 struct mii_attach_args *ma = aux;
116 struct mii_data *mii = ma->mii_data;
117 const struct mii_phydesc *mpd;
118
119 mpd = mii_phy_match(ma, rlphys);
120 if (mpd != NULL) {
121 printf(": %s, rev. %d\n", mpd->mpd_name,
122 MII_REV(ma->mii_id2));
123 } else
124 printf(": RTL internal PHY\n");
125
126 sc->mii_inst = mii->mii_instance;
127 sc->mii_phy = ma->mii_phyno;
128 sc->mii_funcs = &rlphy_funcs;
129 sc->mii_pdata = mii;
130 sc->mii_flags = ma->mii_flags;
131
132 sc->mii_flags |= MIIF_NOISOLATE;
133
134 PHY_RESET(sc);
135
136 sc->mii_capabilities =
137 PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
138 if (sc->mii_capabilities & BMSR_MEDIAMASK)
139 mii_phy_add_media(sc);
140 }
141
142 int
rlphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)143 rlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
144 {
145 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
146
147 if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
148 return (ENXIO);
149
150 /*
151 * Can't isolate the RTL8139 phy, so it has to be the only one.
152 */
153 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
154 panic("rlphy_service: attempt to isolate phy");
155
156 switch (cmd) {
157 case MII_POLLSTAT:
158 break;
159
160 case MII_MEDIACHG:
161 /*
162 * If the interface is not up, don't do anything.
163 */
164 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
165 break;
166
167 switch (IFM_SUBTYPE(ife->ifm_media)) {
168 case IFM_AUTO:
169 /*
170 * If we're already in auto mode, just return.
171 */
172 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
173 return (0);
174 (void) mii_phy_auto(sc, 0);
175 break;
176 case IFM_100_T4:
177 /*
178 * XXX Not supported as a manual setting right now.
179 */
180 return (EINVAL);
181 default:
182 /*
183 * BMCR data is stored in the ifmedia entry.
184 */
185 PHY_WRITE(sc, MII_ANAR,
186 mii_anar(ife->ifm_media));
187 PHY_WRITE(sc, MII_BMCR, ife->ifm_data);
188 }
189 break;
190
191 case MII_TICK:
192 /*
193 * Is the interface even up?
194 */
195 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
196 return (0);
197
198 /*
199 * The Realtek PHY's autonegotiation doesn't need to be
200 * kicked; it continues in the background.
201 */
202 break;
203
204 case MII_DOWN:
205 mii_phy_down(sc);
206 return (0);
207 }
208
209 /* Update the media status. */
210 mii_phy_status(sc);
211
212 /* Callback if something changed. */
213 mii_phy_update(sc, cmd);
214 return (0);
215 }
216
217 void
rlphy_status(struct mii_softc * sc)218 rlphy_status(struct mii_softc *sc)
219 {
220 struct mii_data *mii = sc->mii_pdata;
221 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
222 int bmsr, bmcr, anlpar;
223 char *devname;
224
225 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
226
227 mii->mii_media_status = IFM_AVALID;
228 mii->mii_media_active = IFM_ETHER;
229
230 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
231 if (bmsr & BMSR_LINK)
232 mii->mii_media_status |= IFM_ACTIVE;
233
234 bmcr = PHY_READ(sc, MII_BMCR);
235 if (bmcr & BMCR_ISO) {
236 mii->mii_media_active |= IFM_NONE;
237 mii->mii_media_status = 0;
238 return;
239 }
240
241 if (bmcr & BMCR_LOOP)
242 mii->mii_media_active |= IFM_LOOP;
243
244 if (bmcr & BMCR_AUTOEN) {
245 /*
246 * NWay autonegotiation takes the highest-order common
247 * bit of the ANAR and ANLPAR (i.e. best media advertised
248 * both by us and our link partner).
249 */
250 if ((bmsr & BMSR_ACOMP) == 0) {
251 /* Erg, still trying, I guess... */
252 mii->mii_media_active |= IFM_NONE;
253 return;
254 }
255
256 if ((anlpar = PHY_READ(sc, MII_ANAR) &
257 PHY_READ(sc, MII_ANLPAR))) {
258 if (anlpar & ANLPAR_TX_FD)
259 mii->mii_media_active |= IFM_100_TX|IFM_FDX;
260 else if (anlpar & ANLPAR_T4)
261 mii->mii_media_active |= IFM_100_T4|IFM_HDX;
262 else if (anlpar & ANLPAR_TX)
263 mii->mii_media_active |= IFM_100_TX|IFM_HDX;
264 else if (anlpar & ANLPAR_10_FD)
265 mii->mii_media_active |= IFM_10_T|IFM_FDX;
266 else if (anlpar & ANLPAR_10)
267 mii->mii_media_active |= IFM_10_T|IFM_HDX;
268 else
269 mii->mii_media_active |= IFM_NONE;
270 return;
271 }
272
273 /*
274 * If the other side doesn't support NWAY, then the
275 * best we can do is determine if we have a 10Mbps or
276 * 100Mbps link. There's no way to know if the link
277 * is full or half duplex, so we default to half duplex
278 * and hope that the user is clever enough to manually
279 * change the media settings if we're wrong.
280 */
281
282 /*
283 * The Realtek PHY supports non-NWAY link speed
284 * detection, however it does not report the link
285 * detection results via the ANLPAR or BMSR registers.
286 * (What? Realtek doesn't do things the way everyone
287 * else does? I'm just shocked, shocked I tell you.)
288 * To determine the link speed, we have to do one
289 * of two things:
290 *
291 * - If this is a standalone Realtek RTL8201(L) PHY,
292 * we can determine the link speed by testing bit 0
293 * in the magic, vendor-specific register at offset
294 * 0x19.
295 *
296 * - If this is a Realtek MAC with integrated PHY, we
297 * can test the 'SPEED10' bit of the MAC's media status
298 * register.
299 */
300 if (strcmp("rl", devname) == 0 ||
301 strcmp("re", devname) == 0) {
302 if (PHY_READ(sc, RL_MEDIASTAT) & RL_MEDIASTAT_SPEED10)
303 mii->mii_media_active |= IFM_10_T;
304 else
305 mii->mii_media_active |= IFM_100_TX;
306 } else {
307 if (PHY_READ(sc, 0x0019) & 0x01)
308 mii->mii_media_active |= IFM_100_TX;
309 else
310 mii->mii_media_active |= IFM_10_T;
311 }
312 mii->mii_media_active |= IFM_HDX;
313 } else
314 mii->mii_media_active = ife->ifm_media;
315 }
316