1 /* $OpenBSD: qwzvar.h,v 1.11 2024/12/22 23:30:27 patrick Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2019 The Linux Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted (subject to the limitations in the disclaimer 9 * below) provided that the following conditions are met: 10 * 11 * * Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * * Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * * Neither the name of [Owner Organization] nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY 23 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 24 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT 25 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 26 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 27 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifdef QWZ_DEBUG 37 #define DPRINTF(x...) do { if (qwz_debug) printf(x); } while(0) 38 #define DNPRINTF(n,x...) do { if (qwz_debug & n) printf(x); } while(0) 39 #define QWZ_D_MISC 0x00000001 40 #define QWZ_D_MHI 0x00000002 41 #define QWZ_D_QMI 0x00000004 42 #define QWZ_D_WMI 0x00000008 43 #define QWZ_D_HTC 0x00000010 44 #define QWZ_D_HTT 0x00000020 45 #define QWZ_D_MAC 0x00000040 46 #define QWZ_D_MGMT 0x00000080 47 #define QWZ_D_CE 0x00000100 48 extern uint32_t qwz_debug; 49 #else 50 #define DPRINTF(x...) 51 #define DNPRINTF(n,x...) 52 #endif 53 54 struct qwz_softc; 55 56 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 57 58 struct ath12k_hw_ring_mask { 59 uint8_t tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 60 uint8_t rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 61 uint8_t rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 62 uint8_t rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 63 uint8_t rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 64 uint8_t reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 65 uint8_t host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 66 uint8_t tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 67 }; 68 69 #define ATH12K_FW_DIR "qwz" 70 71 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" 72 #define ATH12K_BOARD_API2_FILE "board-2" 73 #define ATH12K_DEFAULT_BOARD_FILE "board" 74 #define ATH12K_DEFAULT_CAL_FILE "caldata" 75 #define ATH12K_AMSS_FILE "amss" 76 #define ATH12K_M3_FILE "m3" 77 78 #define QWZ_FW_BUILD_ID_MASK "QC_IMAGE_VERSION_STRING=" 79 80 struct ath12k_hal_tcl_to_wbm_rbm_map { 81 uint8_t wbm_ring_num; 82 uint8_t rbm_id; 83 }; 84 85 /** 86 * enum hal_rx_buf_return_buf_manager 87 * 88 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 89 * @HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST: Descriptor returned to WBM idle 90 * descriptor list, where the chip 0 WBM is chosen in case of a 91 * multi-chip config 92 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 93 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 94 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 95 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 96 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 97 * @HAL_RX_BUF_RBM_SW4_BM: For Tx completion -- returned to host 98 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host 99 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host 100 */ 101 102 enum hal_rx_buf_return_buf_manager { 103 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 104 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST, 105 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST, 106 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST, 107 HAL_RX_BUF_RBM_FW_BM, 108 HAL_RX_BUF_RBM_SW0_BM, 109 HAL_RX_BUF_RBM_SW1_BM, 110 HAL_RX_BUF_RBM_SW2_BM, 111 HAL_RX_BUF_RBM_SW3_BM, 112 HAL_RX_BUF_RBM_SW4_BM, 113 HAL_RX_BUF_RBM_SW5_BM, 114 HAL_RX_BUF_RBM_SW6_BM, 115 }; 116 117 struct ath12k_hw_hal_params { 118 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 119 const struct ath12k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map; 120 uint32_t wbm2sw_cc_enable; 121 }; 122 123 struct hal_tx_info { 124 uint16_t meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */ 125 uint8_t ring_id; 126 uint32_t desc_id; 127 enum hal_tcl_desc_type type; 128 enum hal_tcl_encap_type encap_type; 129 uint64_t paddr; 130 uint32_t data_len; 131 uint32_t pkt_offset; 132 enum hal_encrypt_type encrypt_type; 133 uint32_t flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */ 134 uint32_t flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */ 135 uint16_t addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */ 136 uint16_t bss_ast_hash; 137 uint16_t bss_ast_idx; 138 uint8_t tid; 139 uint8_t search_type; /* %HAL_TX_ADDR_SEARCH_ */ 140 uint8_t lmac_id; 141 uint8_t dscp_tid_tbl_idx; 142 bool enable_mesh; 143 uint8_t rbm_id; 144 }; 145 146 /* TODO: Check if the actual desc macros can be used instead */ 147 #define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0) 148 #define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1) 149 #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2) 150 #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3) 151 #define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4) 152 #define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5) 153 #define HAL_TX_STATUS_FLAGS_OFDMA BIT(6) 154 155 #define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring) 156 157 /* Tx status parsed from srng desc */ 158 struct hal_tx_status { 159 enum hal_wbm_rel_src_module buf_rel_source; 160 enum hal_wbm_tqm_rel_reason status; 161 uint8_t ack_rssi; 162 uint32_t flags; /* %HAL_TX_STATUS_FLAGS_ */ 163 uint32_t ppdu_id; 164 uint8_t try_cnt; 165 uint8_t tid; 166 uint16_t peer_id; 167 uint32_t rate_stats; 168 }; 169 170 struct hal_ops { 171 int (*create_srng_config)(struct qwz_softc *); 172 uint16_t (*rxdma_ring_wmask_rx_mpdu_start)(void); 173 uint32_t (*rxdma_ring_wmask_rx_msdu_end)(void); 174 const struct hal_rx_ops *(*get_hal_rx_compact_ops)(void); 175 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 176 }; 177 178 struct ath12k_hw_params { 179 const char *name; 180 uint16_t hw_rev; 181 uint8_t max_radios; 182 uint32_t bdf_addr; 183 184 struct { 185 const char *dir; 186 size_t board_size; 187 size_t cal_offset; 188 } fw; 189 190 const struct ath12k_hw_ops *hw_ops; 191 const struct ath12k_hw_ring_mask *ring_mask; 192 193 bool internal_sleep_clock; 194 195 const struct ath12k_hw_regs *regs; 196 uint32_t qmi_service_ins_id; 197 const struct ce_attr *host_ce_config; 198 uint32_t ce_count; 199 const struct ce_pipe_config *target_ce_config; 200 uint32_t target_ce_count; 201 const struct service_to_pipe *svc_to_ce_map; 202 uint32_t svc_to_ce_map_len; 203 204 bool single_pdev_only; 205 206 bool rxdma1_enable; 207 int num_rxmda_per_pdev; 208 int num_rxdma_dst_ring; 209 bool rx_mac_buf_ring; 210 bool vdev_start_delay; 211 bool htt_peer_map_v2; 212 #if notyet 213 struct { 214 uint8_t fft_sz; 215 uint8_t fft_pad_sz; 216 uint8_t summary_pad_sz; 217 uint8_t fft_hdr_len; 218 uint16_t max_fft_bins; 219 bool fragment_160mhz; 220 } spectral; 221 222 uint16_t interface_modes; 223 bool supports_monitor; 224 bool full_monitor_mode; 225 #endif 226 bool reoq_lut_support; 227 bool supports_shadow_regs; 228 bool idle_ps; 229 bool supports_sta_ps; 230 bool supports_suspend; 231 uint32_t hal_desc_sz; 232 bool fix_l1ss; 233 uint32_t num_tcl_banks; 234 uint32_t max_tx_ring; 235 const struct ath12k_hw_hal_params *hal_params; 236 void (*wmi_init)(struct qwz_softc *sc, 237 struct wmi_resource_config_arg *config); 238 const struct hal_ops *hal_ops; 239 uint64_t qmi_cnss_feature_bitmap; 240 #if notyet 241 bool supports_dynamic_smps_6ghz; 242 bool alloc_cacheable_memory; 243 bool supports_rssi_stats; 244 #endif 245 bool current_cc_support; 246 bool dbr_debug_support; 247 #ifdef notyet 248 const struct cfg80211_sar_capa *bios_sar_capa; 249 bool support_off_channel_tx; 250 bool supports_multi_bssid; 251 252 struct { 253 uint32_t start; 254 uint32_t end; 255 } sram_dump; 256 257 bool tcl_ring_retry; 258 #endif 259 uint32_t tx_ring_size; 260 bool smp2p_wow_exit; 261 }; 262 263 struct ath12k_hw_ops { 264 uint8_t (*get_hw_mac_from_pdev_id)(int pdev_id); 265 int (*mac_id_to_pdev_id)(struct ath12k_hw_params *hw, int mac_id); 266 int (*mac_id_to_srng_id)(struct ath12k_hw_params *hw, int mac_id); 267 bool (*dp_srng_is_tx_comp_ring)(int ring_num); 268 }; 269 270 struct hal_rx_ops { 271 int (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc); 272 #if notyet 273 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc); 274 #endif 275 uint8_t (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 276 uint8_t *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc); 277 int (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc); 278 uint32_t (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc); 279 uint8_t (*rx_desc_get_decap_type)(struct hal_rx_desc *desc); 280 #ifdef notyet 281 uint8_t (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc); 282 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc); 283 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc); 284 uint16_t (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc); 285 #endif 286 uint16_t (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc); 287 #ifdef notyet 288 uint8_t (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc); 289 uint8_t (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc); 290 uint8_t (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc); 291 #endif 292 uint32_t (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc); 293 uint8_t (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc); 294 uint8_t (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc); 295 uint8_t (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc); 296 uint16_t (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc); 297 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc, 298 struct hal_rx_desc *ldesc); 299 uint32_t (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 300 uint32_t (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 301 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, uint16_t len); 302 #ifdef notyet 303 uint8_t *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 304 uint32_t (*rx_desc_get_mpdu_start_offset)(void); 305 uint32_t (*rx_desc_get_msdu_end_offset)(void); 306 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); 307 uint8_t* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); 308 #endif 309 int (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc); 310 #ifdef notyet 311 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, 312 struct ieee80211_hdr *hdr); 313 uint16_t (*rx_desc_get_mpdu_frame_ctl)(struct hal_rx_desc *desc); 314 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, 315 uint8_t *crypto_hdr, 316 enum hal_encrypt_type enctype); 317 #endif 318 bool (*dp_rx_h_msdu_done)(struct hal_rx_desc *desc); 319 #ifdef notyet 320 bool (*dp_rx_h_l4_cksum_fail)(struct hal_rx_desc *desc); 321 bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc); 322 #endif 323 int (*dp_rx_h_is_decrypted)(struct hal_rx_desc *desc); 324 uint32_t (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc); 325 uint32_t (*rx_desc_get_desc_size)(void); 326 #ifdef notyet 327 uint8_t (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); 328 #endif 329 }; 330 331 extern const struct hal_rx_ops hal_rx_wcn7850_ops; 332 333 extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850; 334 335 struct ath12k_hw_regs { 336 uint32_t hal_tcl1_ring_id; 337 uint32_t hal_tcl1_ring_misc; 338 uint32_t hal_tcl1_ring_tp_addr_lsb; 339 uint32_t hal_tcl1_ring_tp_addr_msb; 340 uint32_t hal_tcl1_ring_consumer_int_setup_ix0; 341 uint32_t hal_tcl1_ring_consumer_int_setup_ix1; 342 uint32_t hal_tcl1_ring_msi1_base_lsb; 343 uint32_t hal_tcl1_ring_msi1_base_msb; 344 uint32_t hal_tcl1_ring_msi1_data; 345 uint32_t hal_tcl_ring_base_lsb; 346 347 uint32_t hal_tcl_status_ring_base_lsb; 348 349 uint32_t hal_wbm_idle_ring_base_lsb; 350 uint32_t hal_wbm_idle_ring_misc_addr; 351 uint32_t hal_wbm_r0_idle_list_cntl_addr; 352 uint32_t hal_wbm_r0_idle_list_size_addr; 353 uint32_t hal_wbm_scattered_ring_base_lsb; 354 uint32_t hal_wbm_scattered_ring_base_msb; 355 uint32_t hal_wbm_scattered_desc_head_info_ix0; 356 uint32_t hal_wbm_scattered_desc_head_info_ix1; 357 uint32_t hal_wbm_scattered_desc_tail_info_ix0; 358 uint32_t hal_wbm_scattered_desc_tail_info_ix1; 359 uint32_t hal_wbm_scattered_desc_ptr_hp_addr; 360 361 uint32_t hal_wbm_sw_release_ring_base_lsb; 362 uint32_t hal_wbm_sw1_release_ring_base_lsb; 363 uint32_t hal_wbm0_release_ring_base_lsb; 364 uint32_t hal_wbm1_release_ring_base_lsb; 365 366 uint32_t pcie_qserdes_sysclk_en_sel; 367 uint32_t pcie_pcs_osc_dtct_config_base; 368 369 uint32_t hal_ppe_rel_ring_base; 370 371 uint32_t hal_reo2_ring_base; 372 uint32_t hal_reo1_misc_ctrl_addr; 373 uint32_t hal_reo1_sw_cookie_cfg0; 374 uint32_t hal_reo1_sw_cookie_cfg1; 375 uint32_t hal_reo1_qdesc_lut_base0; 376 uint32_t hal_reo1_qdesc_lut_base1; 377 uint32_t hal_reo1_ring_base_lsb; 378 uint32_t hal_reo1_ring_base_msb; 379 uint32_t hal_reo1_ring_id; 380 uint32_t hal_reo1_ring_misc; 381 uint32_t hal_reo1_ring_hp_addr_lsb; 382 uint32_t hal_reo1_ring_hp_addr_msb; 383 uint32_t hal_reo1_ring_producer_int_setup; 384 uint32_t hal_reo1_ring_msi1_base_lsb; 385 uint32_t hal_reo1_ring_msi1_base_msb; 386 uint32_t hal_reo1_ring_msi1_data; 387 uint32_t hal_reo1_aging_thres_ix0; 388 uint32_t hal_reo1_aging_thres_ix1; 389 uint32_t hal_reo1_aging_thres_ix2; 390 uint32_t hal_reo1_aging_thres_ix3; 391 392 uint32_t hal_reo2_sw0_ring_base; 393 394 uint32_t hal_sw2reo_ring_base; 395 uint32_t hal_sw2reo1_ring_base; 396 397 uint32_t hal_reo_cmd_ring_base; 398 399 uint32_t hal_reo_status_ring_base; 400 }; 401 402 extern const struct ath12k_hw_regs wcn7850_regs; 403 404 enum ath12k_dev_flags { 405 ATH12K_CAC_RUNNING, 406 ATH12K_FLAG_CORE_REGISTERED, 407 ATH12K_FLAG_CRASH_FLUSH, 408 ATH12K_FLAG_RAW_MODE, 409 ATH12K_FLAG_HW_CRYPTO_DISABLED, 410 ATH12K_FLAG_BTCOEX, 411 ATH12K_FLAG_RECOVERY, 412 ATH12K_FLAG_UNREGISTERING, 413 ATH12K_FLAG_REGISTERED, 414 ATH12K_FLAG_QMI_FAIL, 415 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 416 ATH12K_FLAG_CE_IRQ_ENABLED, 417 ATH12K_FLAG_EXT_IRQ_ENABLED, 418 ATH12K_FLAG_FIXED_MEM_RGN, 419 ATH12K_FLAG_DEVICE_INIT_DONE, 420 ATH12K_FLAG_MULTI_MSI_VECTORS, 421 }; 422 423 enum ath12k_scan_state { 424 ATH12K_SCAN_IDLE, 425 ATH12K_SCAN_STARTING, 426 ATH12K_SCAN_RUNNING, 427 ATH12K_SCAN_ABORTING, 428 }; 429 430 enum ath12k_11d_state { 431 ATH12K_11D_IDLE, 432 ATH12K_11D_PREPARING, 433 ATH12K_11D_RUNNING, 434 }; 435 436 /* enum ath12k_spectral_mode: 437 * 438 * @SPECTRAL_DISABLED: spectral mode is disabled 439 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with 440 * something else. 441 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples 442 * is performed manually. 443 */ 444 enum ath12k_spectral_mode { 445 ATH12K_SPECTRAL_DISABLED = 0, 446 ATH12K_SPECTRAL_BACKGROUND, 447 ATH12K_SPECTRAL_MANUAL, 448 }; 449 450 #define QWZ_SCAN_11D_INTERVAL 600000 451 #define QWZ_11D_INVALID_VDEV_ID 0xFFFF 452 453 struct qwz_ops { 454 uint32_t (*read32)(struct qwz_softc *, uint32_t); 455 void (*write32)(struct qwz_softc *, uint32_t, uint32_t); 456 int (*start)(struct qwz_softc *); 457 void (*stop)(struct qwz_softc *); 458 int (*power_up)(struct qwz_softc *); 459 void (*power_down)(struct qwz_softc *); 460 int (*submit_xfer)(struct qwz_softc *, struct mbuf *); 461 void (*irq_enable)(struct qwz_softc *sc); 462 void (*irq_disable)(struct qwz_softc *sc); 463 int (*map_service_to_pipe)(struct qwz_softc *, uint16_t, 464 uint8_t *, uint8_t *); 465 int (*get_user_msi_vector)(struct qwz_softc *, char *, 466 int *, uint32_t *, uint32_t *); 467 }; 468 469 struct qwz_dmamem { 470 bus_dmamap_t map; 471 bus_dma_segment_t seg; 472 size_t size; 473 caddr_t kva; 474 }; 475 476 struct qwz_dmamem *qwz_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t); 477 void qwz_dmamem_free(bus_dma_tag_t, struct qwz_dmamem *); 478 479 #define QWZ_DMA_MAP(_adm) ((_adm)->map) 480 #define QWZ_DMA_LEN(_adm) ((_adm)->size) 481 #define QWZ_DMA_DVA(_adm) ((_adm)->map->dm_segs[0].ds_addr) 482 #define QWZ_DMA_KVA(_adm) ((void *)(_adm)->kva) 483 484 struct hal_srng_params { 485 bus_addr_t ring_base_paddr; 486 uint32_t *ring_base_vaddr; 487 int num_entries; 488 uint32_t intr_batch_cntr_thres_entries; 489 uint32_t intr_timer_thres_us; 490 uint32_t flags; 491 uint32_t max_buffer_len; 492 uint32_t low_threshold; 493 uint64_t msi_addr; 494 uint32_t msi_data; 495 496 /* Add more params as needed */ 497 }; 498 499 enum hal_srng_dir { 500 HAL_SRNG_DIR_SRC, 501 HAL_SRNG_DIR_DST 502 }; 503 504 /* srng flags */ 505 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 506 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 507 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 508 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 509 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 510 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 511 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 512 513 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 514 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 515 516 /* Common SRNG ring structure for source and destination rings */ 517 struct hal_srng { 518 /* Unique SRNG ring ID */ 519 uint8_t ring_id; 520 521 /* Ring initialization done */ 522 uint8_t initialized; 523 524 /* Interrupt/MSI value assigned to this ring */ 525 int irq; 526 527 /* Physical base address of the ring */ 528 bus_addr_t ring_base_paddr; 529 530 /* Virtual base address of the ring */ 531 uint32_t *ring_base_vaddr; 532 533 /* Number of entries in ring */ 534 uint32_t num_entries; 535 536 /* Ring size */ 537 uint32_t ring_size; 538 539 /* Ring size mask */ 540 uint32_t ring_size_mask; 541 542 /* Size of ring entry */ 543 uint32_t entry_size; 544 545 /* Interrupt timer threshold - in micro seconds */ 546 uint32_t intr_timer_thres_us; 547 548 /* Interrupt batch counter threshold - in number of ring entries */ 549 uint32_t intr_batch_cntr_thres_entries; 550 551 /* MSI Address */ 552 bus_addr_t msi_addr; 553 554 /* MSI data */ 555 uint32_t msi_data; 556 557 /* Misc flags */ 558 uint32_t flags; 559 #ifdef notyet 560 /* Lock for serializing ring index updates */ 561 spinlock_t lock; 562 #endif 563 /* Start offset of SRNG register groups for this ring 564 * TBD: See if this is required - register address can be derived 565 * from ring ID 566 */ 567 uint32_t hwreg_base[HAL_SRNG_NUM_REG_GRP]; 568 569 uint64_t timestamp; 570 571 /* Source or Destination ring */ 572 enum hal_srng_dir ring_dir; 573 574 union { 575 struct { 576 /* SW tail pointer */ 577 uint32_t tp; 578 579 /* Shadow head pointer location to be updated by HW */ 580 volatile uint32_t *hp_addr; 581 582 /* Cached head pointer */ 583 uint32_t cached_hp; 584 585 /* Tail pointer location to be updated by SW - This 586 * will be a register address and need not be 587 * accessed through SW structure 588 */ 589 uint32_t *tp_addr; 590 591 /* Current SW loop cnt */ 592 uint32_t loop_cnt; 593 594 /* max transfer size */ 595 uint16_t max_buffer_length; 596 597 /* head pointer at access end */ 598 uint32_t last_hp; 599 } dst_ring; 600 601 struct { 602 /* SW head pointer */ 603 uint32_t hp; 604 605 /* SW reap head pointer */ 606 uint32_t reap_hp; 607 608 /* Shadow tail pointer location to be updated by HW */ 609 uint32_t *tp_addr; 610 611 /* Cached tail pointer */ 612 uint32_t cached_tp; 613 614 /* Head pointer location to be updated by SW - This 615 * will be a register address and need not be accessed 616 * through SW structure 617 */ 618 uint32_t *hp_addr; 619 620 /* Low threshold - in number of ring entries */ 621 uint32_t low_threshold; 622 623 /* tail pointer at access end */ 624 uint32_t last_tp; 625 } src_ring; 626 } u; 627 }; 628 629 enum hal_ring_type { 630 HAL_REO_DST, 631 HAL_REO_EXCEPTION, 632 HAL_REO_REINJECT, 633 HAL_REO_CMD, 634 HAL_REO_STATUS, 635 HAL_TCL_DATA, 636 HAL_TCL_CMD, 637 HAL_TCL_STATUS, 638 HAL_CE_SRC, 639 HAL_CE_DST, 640 HAL_CE_DST_STATUS, 641 HAL_WBM_IDLE_LINK, 642 HAL_SW2WBM_RELEASE, 643 HAL_WBM2SW_RELEASE, 644 HAL_RXDMA_BUF, 645 HAL_RXDMA_DST, 646 HAL_RXDMA_MONITOR_BUF, 647 HAL_RXDMA_MONITOR_STATUS, 648 HAL_RXDMA_MONITOR_DST, 649 HAL_RXDMA_MONITOR_DESC, 650 HAL_RXDMA_DIR_BUF, 651 HAL_PPE2TCL, 652 HAL_PPE_RELEASE, 653 HAL_TX_MONITOR_BUF, 654 HAL_TX_MONITOR_DST, 655 HAL_MAX_RING_TYPES, 656 }; 657 658 enum hal_srng_mac_type { 659 ATH12K_HAL_SRNG_UMAC, 660 ATH12K_HAL_SRNG_DMAC, 661 ATH12K_HAL_SRNG_PMAC 662 }; 663 664 /* HW SRNG configuration table */ 665 struct hal_srng_config { 666 int start_ring_id; 667 uint16_t max_rings; 668 uint16_t entry_size; 669 uint32_t reg_start[HAL_SRNG_NUM_REG_GRP]; 670 uint16_t reg_size[HAL_SRNG_NUM_REG_GRP]; 671 enum hal_srng_mac_type mac_type; 672 enum hal_srng_dir ring_dir; 673 uint32_t max_size; 674 }; 675 676 #define QWZ_NUM_SRNG_CFG 21 677 678 struct hal_reo_status_header { 679 uint16_t cmd_num; 680 enum hal_reo_cmd_status cmd_status; 681 uint16_t cmd_exe_time; 682 uint32_t timestamp; 683 }; 684 685 struct hal_reo_status_queue_stats { 686 uint16_t ssn; 687 uint16_t curr_idx; 688 uint32_t pn[4]; 689 uint32_t last_rx_queue_ts; 690 uint32_t last_rx_dequeue_ts; 691 uint32_t rx_bitmap[8]; /* Bitmap from 0-255 */ 692 uint32_t curr_mpdu_cnt; 693 uint32_t curr_msdu_cnt; 694 uint16_t fwd_due_to_bar_cnt; 695 uint16_t dup_cnt; 696 uint32_t frames_in_order_cnt; 697 uint32_t num_mpdu_processed_cnt; 698 uint32_t num_msdu_processed_cnt; 699 uint32_t total_num_processed_byte_cnt; 700 uint32_t late_rx_mpdu_cnt; 701 uint32_t reorder_hole_cnt; 702 uint8_t timeout_cnt; 703 uint8_t bar_rx_cnt; 704 uint8_t num_window_2k_jump_cnt; 705 }; 706 707 struct hal_reo_status_flush_queue { 708 bool err_detected; 709 }; 710 711 enum hal_reo_status_flush_cache_err_code { 712 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 713 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 714 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 715 }; 716 717 struct hal_reo_status_flush_cache { 718 bool err_detected; 719 enum hal_reo_status_flush_cache_err_code err_code; 720 bool cache_controller_flush_status_hit; 721 uint8_t cache_controller_flush_status_desc_type; 722 uint8_t cache_controller_flush_status_client_id; 723 uint8_t cache_controller_flush_status_err; 724 uint8_t cache_controller_flush_status_cnt; 725 }; 726 727 enum hal_reo_status_unblock_cache_type { 728 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 729 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 730 }; 731 732 struct hal_reo_status_unblock_cache { 733 bool err_detected; 734 enum hal_reo_status_unblock_cache_type unblock_type; 735 }; 736 737 struct hal_reo_status_flush_timeout_list { 738 bool err_detected; 739 bool list_empty; 740 uint16_t release_desc_cnt; 741 uint16_t fwd_buf_cnt; 742 }; 743 744 enum hal_reo_threshold_idx { 745 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 746 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 747 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 748 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 749 }; 750 751 struct hal_reo_status_desc_thresh_reached { 752 enum hal_reo_threshold_idx threshold_idx; 753 uint32_t link_desc_counter0; 754 uint32_t link_desc_counter1; 755 uint32_t link_desc_counter2; 756 uint32_t link_desc_counter_sum; 757 }; 758 759 struct hal_reo_status { 760 struct hal_reo_status_header uniform_hdr; 761 uint8_t loop_cnt; 762 union { 763 struct hal_reo_status_queue_stats queue_stats; 764 struct hal_reo_status_flush_queue flush_queue; 765 struct hal_reo_status_flush_cache flush_cache; 766 struct hal_reo_status_unblock_cache unblock_cache; 767 struct hal_reo_status_flush_timeout_list timeout_list; 768 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 769 } u; 770 }; 771 772 /* HAL context to be used to access SRNG APIs (currently used by data path 773 * and transport (CE) modules) 774 */ 775 struct ath12k_hal { 776 /* HAL internal state for all SRNG rings. 777 */ 778 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 779 780 /* SRNG configuration table */ 781 struct hal_srng_config *srng_config; 782 783 /* Remote pointer memory for HW/FW updates */ 784 struct qwz_dmamem *rdpmem; 785 struct { 786 uint32_t *vaddr; 787 bus_addr_t paddr; 788 } rdp; 789 790 /* Shared memory for ring pointer updates from host to FW */ 791 struct qwz_dmamem *wrpmem; 792 struct { 793 uint32_t *vaddr; 794 bus_addr_t paddr; 795 } wrp; 796 797 /* Available REO blocking resources bitmap */ 798 uint8_t avail_blk_resource; 799 800 uint8_t current_blk_index; 801 802 /* shadow register configuration */ 803 uint32_t shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 804 int num_shadow_reg_configured; 805 #ifdef notyet 806 struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX]; 807 #endif 808 809 uint32_t hal_desc_sz; 810 }; 811 812 enum hal_pn_type { 813 HAL_PN_TYPE_NONE, 814 HAL_PN_TYPE_WPA, 815 HAL_PN_TYPE_WAPI_EVEN, 816 HAL_PN_TYPE_WAPI_UNEVEN, 817 }; 818 819 enum hal_ce_desc { 820 HAL_CE_DESC_SRC, 821 HAL_CE_DESC_DST, 822 HAL_CE_DESC_DST_STATUS, 823 }; 824 825 struct ce_ie_addr { 826 uint32_t ie1_reg_addr; 827 uint32_t ie2_reg_addr; 828 uint32_t ie3_reg_addr; 829 }; 830 831 struct ce_remap { 832 uint32_t base; 833 uint32_t size; 834 }; 835 836 struct ce_attr { 837 /* CE_ATTR_* values */ 838 unsigned int flags; 839 840 /* #entries in source ring - Must be a power of 2 */ 841 unsigned int src_nentries; 842 843 /* 844 * Max source send size for this CE. 845 * This is also the minimum size of a destination buffer. 846 */ 847 unsigned int src_sz_max; 848 849 /* #entries in destination ring - Must be a power of 2 */ 850 unsigned int dest_nentries; 851 852 void (*recv_cb)(struct qwz_softc *, struct mbuf *); 853 }; 854 855 #define CE_DESC_RING_ALIGN 8 856 857 struct qwz_rx_msdu { 858 TAILQ_ENTRY(qwz_rx_msdu) entry; 859 struct mbuf *m; 860 struct ieee80211_rxinfo rxi; 861 int is_first_msdu; 862 int is_last_msdu; 863 int is_continuation; 864 int is_mcbc; 865 int is_eapol; 866 struct hal_rx_desc *rx_desc; 867 uint8_t err_rel_src; 868 uint8_t err_code; 869 uint8_t mac_id; 870 uint8_t unmapped; 871 uint8_t is_frag; 872 uint8_t tid; 873 uint16_t peer_id; 874 uint16_t seq_no; 875 }; 876 877 TAILQ_HEAD(qwz_rx_msdu_list, qwz_rx_msdu); 878 879 struct qwz_rx_data { 880 struct mbuf *m; 881 bus_dmamap_t map; 882 struct qwz_rx_msdu rx_msdu; 883 }; 884 885 struct qwz_tx_data { 886 struct ieee80211_node *ni; 887 struct mbuf *m; 888 bus_dmamap_t map; 889 uint8_t eid; 890 uint8_t flags; 891 uint32_t cipher; 892 }; 893 894 struct qwz_ce_ring { 895 /* Number of entries in this ring; must be power of 2 */ 896 unsigned int nentries; 897 unsigned int nentries_mask; 898 899 /* For dest ring, this is the next index to be processed 900 * by software after it was/is received into. 901 * 902 * For src ring, this is the last descriptor that was sent 903 * and completion processed by software. 904 * 905 * Regardless of src or dest ring, this is an invariant 906 * (modulo ring size): 907 * write index >= read index >= sw_index 908 */ 909 unsigned int sw_index; 910 /* cached copy */ 911 unsigned int write_index; 912 913 /* Start of DMA-coherent area reserved for descriptors */ 914 /* Host address space */ 915 caddr_t base_addr; 916 917 /* DMA map for Tx/Rx descriptors. */ 918 bus_dmamap_t dmap; 919 bus_dma_segment_t dsegs; 920 int nsegs; 921 size_t desc_sz; 922 923 /* HAL ring id */ 924 uint32_t hal_ring_id; 925 926 /* 927 * Per-transfer data. 928 * Size and type of this data depends on how the ring is used. 929 * 930 * For transfers using DMA, the context contains pointers to 931 * struct qwz_rx_data if this ring is a dest ring, or struct 932 * qwz_tx_data if this ring is a src ring. DMA maps are allocated 933 * when the device is started via sc->ops.start, and will be used 934 * to load mbufs for DMA transfers. 935 * In this case, the pointers MUST NOT be cleared until the device 936 * is stopped. Otherwise we'd lose track of our DMA mappings! 937 * The Linux ath12k driver works differently because it can store 938 * DMA mapping information in a Linux socket buffer structure, which 939 * is not possible with mbufs. 940 * 941 * Keep last. 942 */ 943 void *per_transfer_context[0]; 944 }; 945 946 void qwz_htc_tx_completion_handler(struct qwz_softc *, struct mbuf *); 947 void qwz_htc_rx_completion_handler(struct qwz_softc *, struct mbuf *); 948 void qwz_dp_htt_htc_t2h_msg_handler(struct qwz_softc *, struct mbuf *); 949 950 struct qwz_dp; 951 952 struct qwz_dp_htt_wbm_tx_status { 953 uint32_t msdu_id; 954 int acked; 955 int ack_rssi; 956 uint16_t peer_id; 957 }; 958 959 #define DP_NUM_CLIENTS_MAX 64 960 #define DP_AVG_TIDS_PER_CLIENT 2 961 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 962 #define DP_AVG_MSDUS_PER_FLOW 128 963 #define DP_AVG_FLOWS_PER_TID 2 964 #define DP_AVG_MPDUS_PER_TID_MAX 128 965 #define DP_AVG_MSDUS_PER_MPDU 4 966 967 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 968 969 #define DP_BA_WIN_SZ_MAX 256 970 971 #define DP_TCL_NUM_RING_MAX 4 972 973 #define DP_IDLE_SCATTER_BUFS_MAX 16 974 975 #define DP_WBM_RELEASE_RING_SIZE 64 976 #define DP_TCL_DATA_RING_SIZE 512 977 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048 978 #define DP_TX_COMP_RING_SIZE 32768 979 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 980 #define DP_TCL_CMD_RING_SIZE 32 981 #define DP_TCL_STATUS_RING_SIZE 32 982 #define DP_REO_DST_RING_MAX 4 983 #define DP_REO_DST_RING_SIZE 2048 984 #define DP_REO_REINJECT_RING_SIZE 32 985 #define DP_RX_RELEASE_RING_SIZE 1024 986 #define DP_REO_EXCEPTION_RING_SIZE 128 987 #define DP_REO_CMD_RING_SIZE 256 988 #define DP_REO_STATUS_RING_SIZE 2048 989 #define DP_RXDMA_BUF_RING_SIZE 4096 990 #define DP_RXDMA_REFILL_RING_SIZE 2048 991 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 992 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 993 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 994 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 995 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 996 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 997 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 998 999 #define DP_TX_MONITOR_BUF_SIZE 2048 1000 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 1001 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 1002 1003 #define DP_RX_RELEASE_RING_NUM 3 1004 1005 #define DP_RX_BUFFER_SIZE 2048 1006 #define DP_RX_BUFFER_SIZE_LITE 1024 1007 #define DP_RX_BUFFER_ALIGN_SIZE 128 1008 1009 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 1010 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 1011 1012 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 1013 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 1014 1015 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 1016 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 1017 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 1018 1019 #define ATH12K_NUM_POOL_TX_DESC 32768 1020 1021 /* TODO: revisit this count during testing */ 1022 #define ATH12K_RX_DESC_COUNT (12288) 1023 1024 #define ATH12K_PAGE_SIZE PAGE_SIZE 1025 1026 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 1027 * SPT pages which makes lower 12bits 0 1028 */ 1029 #define ATH12K_MAX_PPT_ENTRIES 1024 1030 1031 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 1032 #define ATH12K_MAX_SPT_ENTRIES 512 1033 1034 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 1035 1036 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 1037 ATH12K_MAX_SPT_ENTRIES) 1038 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 1039 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 1040 1041 #define ATH12K_TX_SPT_PAGE_OFFSET 0 1042 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES 1043 1044 /* The SPT pages are divided for RX and TX, first block for RX 1045 * and remaining for TX 1046 */ 1047 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 1048 1049 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 1050 1051 /* 4K aligned address have last 12 bits set to 0, this check is done 1052 * so that two spt pages address can be stored per 8bytes 1053 * of CMEM (PPT) 1054 */ 1055 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 1056 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 1057 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 1058 1059 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 1060 #define ATH12K_CMEM_ADDR_MSB 0x10 1061 1062 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 1063 #define ATH12K_CC_SPT_MSB 8 1064 #define ATH12K_CC_PPT_MSB 19 1065 #define ATH12K_CC_PPT_SHIFT 9 1066 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 1067 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 1068 1069 #define DP_REO_QREF_NUM GENMASK(31, 16) 1070 #define DP_MAX_PEER_ID 2047 1071 1072 /* Total size of the LUT is based on 2K peers, each having reference 1073 * for 17tids, note each entry is of type ath12k_reo_queue_ref 1074 * hence total size is 2048 * 17 * 8 = 278528 1075 */ 1076 #define DP_REOQ_LUT_SIZE 278528 1077 1078 /* Invalid TX Bank ID value */ 1079 #define DP_INVALID_BANK_ID -1 1080 1081 struct ath12k_dp_tx_bank_profile { 1082 uint8_t is_configured; 1083 uint32_t num_users; 1084 uint32_t bank_config; 1085 }; 1086 1087 struct qwz_hp_update_timer { 1088 struct timeout timer; 1089 int started; 1090 int init; 1091 uint32_t tx_num; 1092 uint32_t timer_tx_num; 1093 uint32_t ring_id; 1094 uint32_t interval; 1095 struct qwz_softc *sc; 1096 }; 1097 1098 struct ath12k_rx_desc_info { 1099 TAILQ_ENTRY(ath12k_rx_desc_info) entry; 1100 struct mbuf *m; 1101 bus_dmamap_t map; 1102 uint32_t cookie; 1103 uint32_t magic; 1104 uint8_t in_use : 1, 1105 reserved : 7; 1106 }; 1107 1108 struct ath12k_tx_desc_info { 1109 TAILQ_ENTRY(ath12k_tx_desc_info) entry; 1110 struct mbuf *m; 1111 bus_dmamap_t map; 1112 uint32_t desc_id; /* Cookie */ 1113 uint8_t mac_id; 1114 uint8_t pool_id; 1115 }; 1116 1117 struct ath12k_spt_info { 1118 struct qwz_dmamem *mem; 1119 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 1120 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 1121 }; 1122 1123 struct dp_rx_tid { 1124 uint8_t tid; 1125 struct qwz_dmamem *mem; 1126 uint32_t *vaddr; 1127 uint64_t paddr; 1128 uint32_t size; 1129 uint32_t ba_win_sz; 1130 int active; 1131 1132 /* Info related to rx fragments */ 1133 uint32_t cur_sn; 1134 uint16_t last_frag_no; 1135 uint16_t rx_frag_bitmap; 1136 #if 0 1137 struct sk_buff_head rx_frags; 1138 struct hal_reo_dest_ring *dst_ring_desc; 1139 1140 /* Timer info related to fragments */ 1141 struct timer_list frag_timer; 1142 struct ath12k_base *ab; 1143 #endif 1144 }; 1145 1146 #define DP_REO_DESC_FREE_THRESHOLD 64 1147 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 1148 #define DP_MON_PURGE_TIMEOUT_MS 100 1149 #define DP_MON_SERVICE_BUDGET 128 1150 1151 struct dp_reo_cache_flush_elem { 1152 TAILQ_ENTRY(dp_reo_cache_flush_elem) entry; 1153 struct dp_rx_tid data; 1154 uint64_t ts; 1155 }; 1156 1157 TAILQ_HEAD(dp_reo_cmd_cache_flush_head, dp_reo_cache_flush_elem); 1158 1159 struct dp_reo_cmd { 1160 TAILQ_ENTRY(dp_reo_cmd) entry; 1161 struct dp_rx_tid data; 1162 int cmd_num; 1163 void (*handler)(struct qwz_dp *, void *, 1164 enum hal_reo_cmd_status status); 1165 }; 1166 1167 TAILQ_HEAD(dp_reo_cmd_head, dp_reo_cmd); 1168 1169 struct dp_srng { 1170 struct qwz_dmamem *mem; 1171 uint32_t *vaddr; 1172 bus_addr_t paddr; 1173 int size; 1174 uint32_t ring_id; 1175 }; 1176 1177 struct dp_tx_ring { 1178 uint8_t tcl_data_ring_id; 1179 struct dp_srng tcl_data_ring; 1180 struct dp_srng tcl_comp_ring; 1181 int cur; 1182 int queued; 1183 struct qwz_tx_data *data; 1184 struct hal_wbm_release_ring *tx_status; 1185 int tx_status_head; 1186 int tx_status_tail; 1187 }; 1188 1189 1190 struct dp_link_desc_bank { 1191 struct qwz_dmamem *mem; 1192 caddr_t *vaddr; 1193 bus_addr_t paddr; 1194 uint32_t size; 1195 }; 1196 1197 /* Size to enforce scatter idle list mode */ 1198 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 1199 #define DP_LINK_DESC_BANKS_MAX 8 1200 1201 #define DP_LINK_DESC_START 0x4000 1202 #define DP_LINK_DESC_SHIFT 3 1203 1204 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 1205 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 1206 1207 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 1208 1209 struct hal_wbm_idle_scatter_list { 1210 struct qwz_dmamem *mem; 1211 bus_addr_t paddr; 1212 struct hal_wbm_link_desc *vaddr; 1213 }; 1214 1215 struct dp_rxdma_mon_ring { 1216 struct dp_srng refill_buf_ring; 1217 #if 0 1218 struct idr bufs_idr; 1219 /* Protects bufs_idr */ 1220 spinlock_t idr_lock; 1221 #else 1222 struct qwz_rx_data *rx_data; 1223 #endif 1224 int bufs_max; 1225 uint8_t freemap[howmany(DP_RXDMA_BUF_RING_SIZE, 8)]; 1226 }; 1227 1228 struct dp_rxdma_ring { 1229 struct dp_srng refill_buf_ring; 1230 struct qwz_rx_data *rx_data; 1231 int bufs_max; 1232 }; 1233 1234 #define MAX_RXDMA_PER_PDEV 2 1235 1236 struct qwz_dp { 1237 struct qwz_softc *sc; 1238 uint8_t num_bank_profiles; 1239 struct ath12k_dp_tx_bank_profile *bank_profiles; 1240 enum ath12k_htc_ep_id eid; 1241 int htt_tgt_version_received; 1242 uint8_t htt_tgt_ver_major; 1243 uint8_t htt_tgt_ver_minor; 1244 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 1245 struct dp_srng wbm_idle_ring; 1246 struct dp_srng wbm_desc_rel_ring; 1247 struct dp_srng reo_reinject_ring; 1248 struct dp_srng rx_rel_ring; 1249 struct dp_srng reo_except_ring; 1250 struct dp_srng reo_cmd_ring; 1251 struct dp_srng reo_status_ring; 1252 enum peer_metadata_version peer_metadata_ver; 1253 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 1254 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 1255 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 1256 struct dp_reo_cmd_head reo_cmd_list; 1257 struct dp_reo_cmd_cache_flush_head reo_cmd_cache_flush_list; 1258 #if 0 1259 struct list_head dp_full_mon_mpdu_list; 1260 #endif 1261 uint32_t reo_cmd_cache_flush_count; 1262 enum hal_rx_buf_return_buf_manager idle_link_rbm; 1263 #if 0 1264 /** 1265 * protects access to below fields, 1266 * - reo_cmd_list 1267 * - reo_cmd_cache_flush_list 1268 * - reo_cmd_cache_flush_count 1269 */ 1270 spinlock_t reo_cmd_lock; 1271 #endif 1272 struct qwz_hp_update_timer reo_cmd_timer; 1273 struct qwz_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 1274 struct ath12k_spt_info *spt_info; 1275 uint32_t num_spt_pages; 1276 TAILQ_HEAD(,ath12k_rx_desc_info) rx_desc_free_list; 1277 #ifdef notyet 1278 /* protects the free desc list */ 1279 spinlock_t rx_desc_lock; 1280 #endif 1281 TAILQ_HEAD(,ath12k_tx_desc_info) tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 1282 TAILQ_HEAD(,ath12k_tx_desc_info) tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 1283 #ifdef notyet 1284 /* protects the free and used desc lists */ 1285 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 1286 #endif 1287 struct dp_rxdma_ring rx_refill_buf_ring; 1288 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 1289 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 1290 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 1291 }; 1292 1293 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 1294 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 1295 1296 struct qwz_ce_pipe { 1297 struct qwz_softc *sc; 1298 uint16_t pipe_num; 1299 unsigned int attr_flags; 1300 unsigned int buf_sz; 1301 unsigned int rx_buf_needed; 1302 1303 int (*send_cb)(struct qwz_ce_pipe *pipe); 1304 void (*recv_cb)(struct qwz_softc *, struct mbuf *); 1305 1306 #ifdef notyet 1307 struct tasklet_struct intr_tq; 1308 #endif 1309 struct qwz_ce_ring *src_ring; 1310 struct qwz_ce_ring *dest_ring; 1311 struct qwz_ce_ring *status_ring; 1312 uint64_t timestamp; 1313 }; 1314 1315 struct qwz_ce { 1316 struct qwz_ce_pipe ce_pipe[CE_COUNT_MAX]; 1317 #ifdef notyet 1318 /* Protects rings of all ce pipes */ 1319 spinlock_t ce_lock; 1320 #endif 1321 }; 1322 1323 1324 /* XXX This may be non-zero on AHB but is always zero on PCI. */ 1325 #define ATH12K_CE_OFFSET(sc) (0) 1326 1327 struct qwz_qmi_ce_cfg { 1328 const uint8_t *shadow_reg; 1329 int shadow_reg_len; 1330 uint32_t *shadow_reg_v3; 1331 uint32_t shadow_reg_v3_len; 1332 }; 1333 1334 struct qwz_qmi_target_info { 1335 uint32_t chip_id; 1336 uint32_t chip_family; 1337 uint32_t board_id; 1338 uint32_t soc_id; 1339 uint32_t fw_version; 1340 uint32_t eeprom_caldata; 1341 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 1342 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 1343 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 1344 }; 1345 1346 struct qwz_qmi_dev_mem_info { 1347 uint64_t start; 1348 uint64_t size; 1349 }; 1350 1351 enum ath12k_bdf_search { 1352 ATH12K_BDF_SEARCH_DEFAULT, 1353 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 1354 }; 1355 1356 struct qwz_device_id { 1357 enum ath12k_bdf_search bdf_search; 1358 uint32_t vendor; 1359 uint32_t device; 1360 uint32_t subsystem_vendor; 1361 uint32_t subsystem_device; 1362 }; 1363 1364 struct qwz_wmi_base; 1365 1366 struct qwz_pdev_wmi { 1367 struct qwz_wmi_base *wmi; 1368 enum ath12k_htc_ep_id eid; 1369 const struct wmi_peer_flags_map *peer_flags; 1370 uint32_t rx_decap_mode; 1371 }; 1372 1373 #define QWZ_MAX_RADIOS 3 1374 1375 struct qwz_wmi_base { 1376 struct qwz_softc *sc; 1377 struct qwz_pdev_wmi wmi[QWZ_MAX_RADIOS]; 1378 enum ath12k_htc_ep_id wmi_endpoint_id[QWZ_MAX_RADIOS]; 1379 uint32_t max_msg_len[QWZ_MAX_RADIOS]; 1380 int service_ready; 1381 int unified_ready; 1382 uint8_t svc_map[howmany(WMI_MAX_EXT2_SERVICE, 8)]; 1383 int tx_credits; 1384 const struct wmi_peer_flags_map *peer_flags; 1385 uint32_t num_mem_chunks; 1386 uint32_t rx_decap_mode; 1387 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; 1388 enum wmi_host_hw_mode_config_type preferred_hw_mode; 1389 struct target_resource_config wlan_resource_config; 1390 struct ath12k_targ_cap *targ_cap; 1391 }; 1392 1393 struct wmi_tlv_policy { 1394 size_t min_len; 1395 }; 1396 1397 struct wmi_tlv_svc_ready_parse { 1398 int wmi_svc_bitmap_done; 1399 }; 1400 1401 struct wmi_tlv_dma_ring_caps_parse { 1402 struct wmi_dma_ring_capabilities *dma_ring_caps; 1403 uint32_t n_dma_ring_caps; 1404 }; 1405 1406 struct wmi_tlv_svc_rdy_ext_parse { 1407 struct ath12k_service_ext_param param; 1408 struct wmi_soc_mac_phy_hw_mode_caps *hw_caps; 1409 struct wmi_hw_mode_capabilities *hw_mode_caps; 1410 uint32_t n_hw_mode_caps; 1411 uint32_t tot_phy_id; 1412 struct wmi_hw_mode_capabilities pref_hw_mode_caps; 1413 struct wmi_mac_phy_capabilities *mac_phy_caps; 1414 size_t mac_phy_caps_size; 1415 uint32_t n_mac_phy_caps; 1416 struct wmi_soc_hal_reg_capabilities *soc_hal_reg_caps; 1417 struct wmi_hal_reg_capabilities_ext *ext_hal_reg_caps; 1418 uint32_t n_ext_hal_reg_caps; 1419 struct wmi_tlv_dma_ring_caps_parse dma_caps_parse; 1420 int hw_mode_done; 1421 int mac_phy_done; 1422 int ext_hal_reg_done; 1423 int mac_phy_chainmask_combo_done; 1424 int mac_phy_chainmask_cap_done; 1425 int oem_dma_ring_cap_done; 1426 int dma_ring_cap_done; 1427 }; 1428 1429 struct wmi_tlv_svc_rdy_ext2_parse { 1430 struct wmi_tlv_dma_ring_caps_parse dma_caps_parse; 1431 bool dma_ring_cap_done; 1432 }; 1433 1434 struct wmi_tlv_rdy_parse { 1435 uint32_t num_extra_mac_addr; 1436 }; 1437 1438 struct wmi_tlv_dma_buf_release_parse { 1439 struct ath12k_wmi_dma_buf_release_fixed_param fixed; 1440 struct wmi_dma_buf_release_entry *buf_entry; 1441 struct wmi_dma_buf_release_meta_data *meta_data; 1442 uint32_t num_buf_entry; 1443 uint32_t num_meta; 1444 bool buf_entry_done; 1445 bool meta_data_done; 1446 }; 1447 1448 struct wmi_tlv_fw_stats_parse { 1449 const struct wmi_stats_event *ev; 1450 const struct wmi_per_chain_rssi_stats *rssi; 1451 struct ath12k_fw_stats *stats; 1452 int rssi_num; 1453 bool chain_rssi_done; 1454 }; 1455 1456 struct wmi_tlv_mgmt_rx_parse { 1457 const struct wmi_mgmt_rx_hdr *fixed; 1458 const uint8_t *frame_buf; 1459 bool frame_buf_done; 1460 }; 1461 1462 struct qwz_htc; 1463 1464 struct qwz_htc_ep_ops { 1465 void (*ep_tx_complete)(struct qwz_softc *, struct mbuf *); 1466 void (*ep_rx_complete)(struct qwz_softc *, struct mbuf *); 1467 void (*ep_tx_credits)(struct qwz_softc *); 1468 }; 1469 1470 /* service connection information */ 1471 struct qwz_htc_svc_conn_req { 1472 uint16_t service_id; 1473 struct qwz_htc_ep_ops ep_ops; 1474 int max_send_queue_depth; 1475 }; 1476 1477 /* service connection response information */ 1478 struct qwz_htc_svc_conn_resp { 1479 uint8_t buffer_len; 1480 uint8_t actual_len; 1481 enum ath12k_htc_ep_id eid; 1482 unsigned int max_msg_len; 1483 uint8_t connect_resp_code; 1484 }; 1485 1486 #define ATH12K_NUM_CONTROL_TX_BUFFERS 2 1487 #define ATH12K_HTC_MAX_LEN 4096 1488 #define ATH12K_HTC_MAX_CTRL_MSG_LEN 256 1489 #define ATH12K_HTC_WAIT_TIMEOUT_HZ (1 * HZ) 1490 #define ATH12K_HTC_CONTROL_BUFFER_SIZE (ATH12K_HTC_MAX_CTRL_MSG_LEN + \ 1491 sizeof(struct ath12k_htc_hdr)) 1492 #define ATH12K_HTC_CONN_SVC_TIMEOUT_HZ (1 * HZ) 1493 #define ATH12K_HTC_MAX_SERVICE_ALLOC_ENTRIES 8 1494 1495 struct qwz_htc_ep { 1496 struct qwz_htc *htc; 1497 enum ath12k_htc_ep_id eid; 1498 enum ath12k_htc_svc_id service_id; 1499 struct qwz_htc_ep_ops ep_ops; 1500 1501 int max_tx_queue_depth; 1502 int max_ep_message_len; 1503 uint8_t ul_pipe_id; 1504 uint8_t dl_pipe_id; 1505 1506 uint8_t seq_no; /* for debugging */ 1507 int tx_credits; 1508 bool tx_credit_flow_enabled; 1509 }; 1510 1511 struct qwz_htc_svc_tx_credits { 1512 uint16_t service_id; 1513 uint8_t credit_allocation; 1514 }; 1515 1516 struct qwz_htc { 1517 struct qwz_softc *sc; 1518 struct qwz_htc_ep endpoint[ATH12K_HTC_EP_COUNT]; 1519 #ifdef notyet 1520 /* protects endpoints */ 1521 spinlock_t tx_lock; 1522 #endif 1523 uint8_t control_resp_buffer[ATH12K_HTC_MAX_CTRL_MSG_LEN]; 1524 int control_resp_len; 1525 1526 int ctl_resp; 1527 1528 int total_transmit_credits; 1529 struct qwz_htc_svc_tx_credits 1530 service_alloc_table[ATH12K_HTC_MAX_SERVICE_ALLOC_ENTRIES]; 1531 int target_credit_size; 1532 uint8_t wmi_ep_count; 1533 }; 1534 1535 struct qwz_msi_user { 1536 char *name; 1537 int num_vectors; 1538 uint32_t base_vector; 1539 }; 1540 1541 struct qwz_msi_config { 1542 int total_vectors; 1543 int total_users; 1544 struct qwz_msi_user *users; 1545 uint16_t hw_rev; 1546 }; 1547 1548 struct ath12k_band_cap { 1549 uint32_t phy_id; 1550 uint32_t max_bw_supported; 1551 uint32_t ht_cap_info; 1552 uint32_t he_cap_info[2]; 1553 uint32_t he_mcs; 1554 uint32_t he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 1555 struct ath12k_ppe_threshold he_ppet; 1556 uint16_t he_6ghz_capa; 1557 }; 1558 1559 struct ath12k_pdev_cap { 1560 uint32_t supported_bands; 1561 uint32_t ampdu_density; 1562 uint32_t vht_cap; 1563 uint32_t vht_mcs; 1564 uint32_t he_mcs; 1565 uint32_t tx_chain_mask; 1566 uint32_t rx_chain_mask; 1567 uint32_t tx_chain_mask_shift; 1568 uint32_t rx_chain_mask_shift; 1569 struct ath12k_band_cap band[WMI_NUM_SUPPORTED_BAND_MAX]; 1570 int nss_ratio_enabled; 1571 uint8_t nss_ratio_info; 1572 }; 1573 1574 struct qwz_pdev { 1575 struct qwz_softc *sc; 1576 uint32_t pdev_id; 1577 struct ath12k_pdev_cap cap; 1578 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 1579 }; 1580 1581 struct qwz_dbring_cap { 1582 uint32_t pdev_id; 1583 enum wmi_direct_buffer_module id; 1584 uint32_t min_elem; 1585 uint32_t min_buf_sz; 1586 uint32_t min_buf_align; 1587 }; 1588 1589 enum hal_rx_mon_status { 1590 HAL_RX_MON_STATUS_PPDU_NOT_DONE, 1591 HAL_RX_MON_STATUS_PPDU_DONE, 1592 HAL_RX_MON_STATUS_BUF_DONE, 1593 }; 1594 1595 struct hal_rx_user_status { 1596 uint32_t mcs:4, 1597 nss:3, 1598 ofdma_info_valid:1, 1599 dl_ofdma_ru_start_index:7, 1600 dl_ofdma_ru_width:7, 1601 dl_ofdma_ru_size:8; 1602 uint32_t ul_ofdma_user_v0_word0; 1603 uint32_t ul_ofdma_user_v0_word1; 1604 uint32_t ast_index; 1605 uint32_t tid; 1606 uint16_t tcp_msdu_count; 1607 uint16_t udp_msdu_count; 1608 uint16_t other_msdu_count; 1609 uint16_t frame_control; 1610 uint8_t frame_control_info_valid; 1611 uint8_t data_sequence_control_info_valid; 1612 uint16_t first_data_seq_ctrl; 1613 uint32_t preamble_type; 1614 uint16_t ht_flags; 1615 uint16_t vht_flags; 1616 uint16_t he_flags; 1617 uint8_t rs_flags; 1618 uint32_t mpdu_cnt_fcs_ok; 1619 uint32_t mpdu_cnt_fcs_err; 1620 uint32_t mpdu_fcs_ok_bitmap[8]; 1621 uint32_t mpdu_ok_byte_count; 1622 uint32_t mpdu_err_byte_count; 1623 }; 1624 1625 struct hal_rx_wbm_rel_info { 1626 uint32_t cookie; 1627 enum hal_wbm_rel_src_module err_rel_src; 1628 enum hal_reo_dest_ring_push_reason push_reason; 1629 uint32_t err_code; 1630 int first_msdu; 1631 int last_msdu; 1632 }; 1633 1634 #define HAL_INVALID_PEERID 0xffff 1635 #define VHT_SIG_SU_NSS_MASK 0x7 1636 1637 #define HAL_RX_MAX_MCS 12 1638 #define HAL_RX_MAX_NSS 8 1639 1640 #define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE 1641 #define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE 1642 #define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE 1643 1644 struct hal_rx_mon_ppdu_info { 1645 uint32_t ppdu_id; 1646 uint32_t ppdu_ts; 1647 uint32_t num_mpdu_fcs_ok; 1648 uint32_t num_mpdu_fcs_err; 1649 uint32_t preamble_type; 1650 uint16_t chan_num; 1651 uint16_t tcp_msdu_count; 1652 uint16_t tcp_ack_msdu_count; 1653 uint16_t udp_msdu_count; 1654 uint16_t other_msdu_count; 1655 uint16_t peer_id; 1656 uint8_t rate; 1657 uint8_t mcs; 1658 uint8_t nss; 1659 uint8_t bw; 1660 uint8_t vht_flag_values1; 1661 uint8_t vht_flag_values2; 1662 uint8_t vht_flag_values3[4]; 1663 uint8_t vht_flag_values4; 1664 uint8_t vht_flag_values5; 1665 uint16_t vht_flag_values6; 1666 uint8_t is_stbc; 1667 uint8_t gi; 1668 uint8_t ldpc; 1669 uint8_t beamformed; 1670 uint8_t rssi_comb; 1671 uint8_t rssi_chain_pri20[HAL_RX_MAX_NSS]; 1672 uint8_t tid; 1673 uint16_t ht_flags; 1674 uint16_t vht_flags; 1675 uint16_t he_flags; 1676 uint16_t he_mu_flags; 1677 uint8_t dcm; 1678 uint8_t ru_alloc; 1679 uint8_t reception_type; 1680 uint64_t tsft; 1681 uint64_t rx_duration; 1682 uint16_t frame_control; 1683 uint32_t ast_index; 1684 uint8_t rs_fcs_err; 1685 uint8_t rs_flags; 1686 uint8_t cck_flag; 1687 uint8_t ofdm_flag; 1688 uint8_t ulofdma_flag; 1689 uint8_t frame_control_info_valid; 1690 uint16_t he_per_user_1; 1691 uint16_t he_per_user_2; 1692 uint8_t he_per_user_position; 1693 uint8_t he_per_user_known; 1694 uint16_t he_flags1; 1695 uint16_t he_flags2; 1696 uint8_t he_RU[4]; 1697 uint16_t he_data1; 1698 uint16_t he_data2; 1699 uint16_t he_data3; 1700 uint16_t he_data4; 1701 uint16_t he_data5; 1702 uint16_t he_data6; 1703 uint32_t ppdu_len; 1704 uint32_t prev_ppdu_id; 1705 uint32_t device_id; 1706 uint16_t first_data_seq_ctrl; 1707 uint8_t monitor_direct_used; 1708 uint8_t data_sequence_control_info_valid; 1709 uint8_t ltf_size; 1710 uint8_t rxpcu_filter_pass; 1711 char rssi_chain[8][8]; 1712 struct hal_rx_user_status userstats; 1713 }; 1714 1715 enum dp_mon_status_buf_state { 1716 /* PPDU id matches in dst ring and status ring */ 1717 DP_MON_STATUS_MATCH, 1718 /* status ring dma is not done */ 1719 DP_MON_STATUS_NO_DMA, 1720 /* status ring is lagging, reap status ring */ 1721 DP_MON_STATUS_LAG, 1722 /* status ring is leading, reap dst ring and drop */ 1723 DP_MON_STATUS_LEAD, 1724 /* replinish monitor status ring */ 1725 DP_MON_STATUS_REPLINISH, 1726 }; 1727 1728 struct qwz_pdev_mon_stats { 1729 uint32_t status_ppdu_state; 1730 uint32_t status_ppdu_start; 1731 uint32_t status_ppdu_end; 1732 uint32_t status_ppdu_compl; 1733 uint32_t status_ppdu_start_mis; 1734 uint32_t status_ppdu_end_mis; 1735 uint32_t status_ppdu_done; 1736 uint32_t dest_ppdu_done; 1737 uint32_t dest_mpdu_done; 1738 uint32_t dest_mpdu_drop; 1739 uint32_t dup_mon_linkdesc_cnt; 1740 uint32_t dup_mon_buf_cnt; 1741 uint32_t dest_mon_stuck; 1742 uint32_t dest_mon_not_reaped; 1743 }; 1744 1745 struct qwz_mon_data { 1746 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 1747 struct hal_rx_mon_ppdu_info mon_ppdu_info; 1748 1749 uint32_t mon_ppdu_status; 1750 uint32_t mon_last_buf_cookie; 1751 uint64_t mon_last_linkdesc_paddr; 1752 uint16_t chan_noise_floor; 1753 bool hold_mon_dst_ring; 1754 enum dp_mon_status_buf_state buf_state; 1755 bus_addr_t mon_status_paddr; 1756 struct dp_full_mon_mpdu *mon_mpdu; 1757 #ifdef notyet 1758 struct hal_sw_mon_ring_entries sw_mon_entries; 1759 #endif 1760 struct qwz_pdev_mon_stats rx_mon_stats; 1761 #ifdef notyet 1762 /* lock for monitor data */ 1763 spinlock_t mon_lock; 1764 struct sk_buff_head rx_status_q; 1765 #endif 1766 }; 1767 1768 1769 struct qwz_pdev_dp { 1770 uint32_t mac_id; 1771 #if 0 1772 atomic_t num_tx_pending; 1773 wait_queue_head_t tx_empty_waitq; 1774 #endif 1775 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 1776 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 1777 #if 0 1778 struct ieee80211_rx_status rx_status; 1779 #endif 1780 struct qwz_mon_data mon_data; 1781 }; 1782 1783 struct qwz_txmgmt_queue { 1784 struct qwz_tx_data data[8]; 1785 int cur; 1786 int queued; 1787 }; 1788 1789 struct qwz_vif { 1790 uint32_t vdev_id; 1791 enum wmi_vdev_type vdev_type; 1792 enum wmi_vdev_subtype vdev_subtype; 1793 uint32_t beacon_interval; 1794 uint32_t dtim_period; 1795 uint16_t ast_hash; 1796 uint16_t ast_idx; 1797 uint16_t tcl_metadata; 1798 uint8_t hal_addr_search_flags; 1799 uint8_t search_type; 1800 1801 struct qwz_softc *sc; 1802 1803 uint16_t tx_seq_no; 1804 struct wmi_wmm_params_all_arg wmm_params; 1805 TAILQ_ENTRY(qwz_vif) entry; 1806 union { 1807 struct { 1808 uint32_t uapsd; 1809 } sta; 1810 struct { 1811 /* 127 stations; wmi limit */ 1812 uint8_t tim_bitmap[16]; 1813 uint8_t tim_len; 1814 uint32_t ssid_len; 1815 uint8_t ssid[IEEE80211_NWID_LEN]; 1816 bool hidden_ssid; 1817 /* P2P_IE with NoA attribute for P2P_GO case */ 1818 uint32_t noa_len; 1819 uint8_t *noa_data; 1820 } ap; 1821 } u; 1822 1823 bool is_started; 1824 bool is_up; 1825 bool ftm_responder; 1826 bool spectral_enabled; 1827 bool ps; 1828 uint32_t aid; 1829 uint8_t bssid[IEEE80211_ADDR_LEN]; 1830 #if 0 1831 struct cfg80211_bitrate_mask bitrate_mask; 1832 struct delayed_work connection_loss_work; 1833 #endif 1834 int num_legacy_stations; 1835 int rtscts_prot_mode; 1836 int txpower; 1837 bool rsnie_present; 1838 bool wpaie_present; 1839 bool bcca_zero_sent; 1840 bool do_not_send_tmpl; 1841 struct ieee80211_channel *chan; 1842 #if 0 1843 struct ath12k_arp_ns_offload arp_ns_offload; 1844 struct ath12k_rekey_data rekey_data; 1845 #endif 1846 #ifdef CONFIG_ATH12K_DEBUGFS 1847 struct dentry *debugfs_twt; 1848 #endif /* CONFIG_ATH12K_DEBUGFS */ 1849 1850 struct qwz_txmgmt_queue txmgmt; 1851 }; 1852 1853 TAILQ_HEAD(qwz_vif_list, qwz_vif); 1854 1855 struct qwz_survey_info { 1856 int8_t noise; 1857 uint64_t time; 1858 uint64_t time_busy; 1859 }; 1860 1861 #define ATH12K_IRQ_NUM_MAX 52 1862 #define ATH12K_EXT_IRQ_NUM_MAX 16 1863 1864 struct qwz_ext_irq_grp { 1865 struct qwz_softc *sc; 1866 uint32_t irqs[ATH12K_EXT_IRQ_NUM_MAX]; 1867 uint32_t num_irq; 1868 uint32_t grp_id; 1869 uint64_t timestamp; 1870 #if 0 1871 bool napi_enabled; 1872 struct napi_struct napi; 1873 struct net_device napi_ndev; 1874 #endif 1875 }; 1876 1877 struct qwz_rx_radiotap_header { 1878 struct ieee80211_radiotap_header wr_ihdr; 1879 } __packed; 1880 1881 #define IWX_RX_RADIOTAP_PRESENT 0 /* TODO add more information */ 1882 1883 struct qwz_tx_radiotap_header { 1884 struct ieee80211_radiotap_header wt_ihdr; 1885 } __packed; 1886 1887 #define IWX_TX_RADIOTAP_PRESENT 0 /* TODO add more information */ 1888 1889 struct qwz_setkey_task_arg { 1890 struct ieee80211_node *ni; 1891 struct ieee80211_key *k; 1892 int cmd; 1893 #define QWZ_ADD_KEY 1 1894 #define QWZ_DEL_KEY 2 1895 }; 1896 1897 struct qwz_softc { 1898 struct device sc_dev; 1899 struct ieee80211com sc_ic; 1900 uint32_t sc_flags; 1901 int sc_node; 1902 1903 int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); 1904 1905 struct rwlock ioctl_rwl; 1906 1907 struct task init_task; /* NB: not reference-counted */ 1908 struct refcnt task_refs; 1909 struct taskq *sc_nswq; 1910 struct task newstate_task; 1911 enum ieee80211_state ns_nstate; 1912 int ns_arg; 1913 1914 /* Task for setting encryption keys and its arguments. */ 1915 struct task setkey_task; 1916 /* 1917 * At present we need to process at most two keys at once: 1918 * Our pairwise key and a group key. 1919 * When hostap mode is implemented this array needs to grow or 1920 * it might become a bottleneck for associations that occur at 1921 * roughly the same time. 1922 */ 1923 struct qwz_setkey_task_arg setkey_arg[2]; 1924 int setkey_cur; 1925 int setkey_tail; 1926 int setkey_nkeys; 1927 1928 int install_key_done; 1929 int install_key_status; 1930 1931 enum ath12k_11d_state state_11d; 1932 int completed_11d_scan; 1933 uint32_t vdev_id_11d_scan; 1934 struct { 1935 int started; 1936 int completed; 1937 int on_channel; 1938 struct timeout timeout; 1939 enum ath12k_scan_state state; 1940 int vdev_id; 1941 int is_roc; 1942 int roc_freq; 1943 int roc_notify; 1944 } scan; 1945 u_int scan_channel; 1946 struct qwz_survey_info survey[IEEE80211_CHAN_MAX]; 1947 1948 int attached; 1949 struct { 1950 u_char *data; 1951 size_t size; 1952 } fw_img[3]; 1953 #define QWZ_FW_AMSS 0 1954 #define QWZ_FW_BOARD 1 1955 #define QWZ_FW_M3 2 1956 1957 int sc_tx_timer; 1958 uint32_t qfullmsk; 1959 #define QWZ_MGMT_QUEUE_ID 31 1960 1961 bus_addr_t mem; 1962 struct ath12k_hw_params hw_params; 1963 struct ath12k_hal hal; 1964 struct qwz_ce ce; 1965 struct qwz_dp dp; 1966 struct qwz_pdev_dp pdev_dp; 1967 struct qwz_wmi_base wmi; 1968 struct qwz_htc htc; 1969 const struct hal_rx_ops *hal_rx_ops; 1970 uint32_t wmi_conf_rx_decap_mode; 1971 1972 enum ath12k_firmware_mode fw_mode; 1973 enum ath12k_crypt_mode crypto_mode; 1974 enum ath12k_hw_txrx_mode frame_mode; 1975 1976 struct qwz_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 1977 1978 uint16_t qmi_txn_id; 1979 int qmi_cal_done; 1980 struct qwz_qmi_ce_cfg qmi_ce_cfg; 1981 struct qwz_qmi_target_info qmi_target; 1982 struct qwz_qmi_dev_mem_info qmi_dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 1983 struct ath12k_targ_cap target_caps; 1984 int num_radios; 1985 uint8_t device_id; 1986 uint32_t cc_freq_hz; 1987 uint32_t cfg_tx_chainmask; 1988 uint32_t cfg_rx_chainmask; 1989 int num_tx_chains; 1990 int num_rx_chains; 1991 int num_created_vdevs; 1992 int num_started_vdevs; 1993 uint32_t allocated_vdev_map; 1994 uint32_t free_vdev_map; 1995 int num_peers; 1996 int peer_mapped; 1997 int peer_delete_done; 1998 int vdev_setup_done; 1999 int peer_assoc_done; 2000 2001 struct qwz_dbring_cap *db_caps; 2002 uint32_t num_db_cap; 2003 2004 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 2005 int wmi_ready; 2006 uint32_t wlan_init_status; 2007 2008 uint32_t pktlog_defs_checksum; 2009 2010 struct qwz_vif_list vif_list; 2011 struct qwz_pdev pdevs[MAX_RADIOS]; 2012 struct { 2013 enum WMI_HOST_WLAN_BAND supported_bands; 2014 uint32_t pdev_id; 2015 } target_pdev_ids[MAX_RADIOS]; 2016 uint8_t target_pdev_count; 2017 uint32_t pdevs_active; 2018 int pdevs_macaddr_valid; 2019 struct ath12k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS]; 2020 2021 struct { 2022 uint32_t service; 2023 uint32_t instance; 2024 uint32_t node; 2025 uint32_t port; 2026 } qrtr_server; 2027 2028 struct qmi_response_type_v01 qmi_resp; 2029 2030 struct qwz_dmamem *fwmem; 2031 int expect_fwmem_req; 2032 int fwmem_ready; 2033 int fw_ready; 2034 2035 int ctl_resp; 2036 2037 struct qwz_dmamem *m3_mem; 2038 2039 struct timeout mon_reap_timer; 2040 #define ATH12K_MON_TIMER_INTERVAL 10 2041 2042 /* Provided by attachment driver: */ 2043 struct qwz_ops ops; 2044 bus_dma_tag_t sc_dmat; 2045 enum ath12k_hw_rev sc_hw_rev; 2046 int static_window_map; 2047 struct qwz_device_id id; 2048 char sc_bus_str[4]; /* "pci" or "ahb" */ 2049 int num_msivec; 2050 uint32_t msi_addr_lo; 2051 uint32_t msi_addr_hi; 2052 uint32_t msi_data_start; 2053 const struct qwz_msi_config *msi_cfg; 2054 uint32_t msi_ce_irqmask; 2055 2056 struct qmi_wlanfw_request_mem_ind_msg_v01 *sc_req_mem_ind; 2057 2058 caddr_t sc_drvbpf; 2059 2060 union { 2061 struct qwz_rx_radiotap_header th; 2062 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 2063 } sc_rxtapu; 2064 #define sc_rxtap sc_rxtapu.th 2065 int sc_rxtap_len; 2066 2067 union { 2068 struct qwz_tx_radiotap_header th; 2069 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 2070 } sc_txtapu; 2071 #define sc_txtap sc_txtapu.th 2072 int sc_txtap_len; 2073 }; 2074 2075 int qwz_ce_intr(void *); 2076 int qwz_ext_intr(void *); 2077 int qwz_dp_service_srng(struct qwz_softc *, int); 2078 2079 int qwz_init_hw_params(struct qwz_softc *); 2080 int qwz_attach(struct qwz_softc *); 2081 void qwz_detach(struct qwz_softc *); 2082 int qwz_activate(struct device *, int); 2083 2084 void qwz_core_deinit(struct qwz_softc *); 2085 void qwz_ce_cleanup_pipes(struct qwz_softc *); 2086 2087 int qwz_ioctl(struct ifnet *, u_long, caddr_t); 2088 void qwz_start(struct ifnet *); 2089 void qwz_watchdog(struct ifnet *); 2090 int qwz_media_change(struct ifnet *); 2091 void qwz_init_task(void *); 2092 int qwz_newstate(struct ieee80211com *, enum ieee80211_state, int); 2093 void qwz_newstate_task(void *); 2094 2095 struct ath12k_peer { 2096 #if 0 2097 struct list_head list; 2098 struct ieee80211_sta *sta; 2099 #endif 2100 int vdev_id; 2101 #if 0 2102 u8 addr[ETH_ALEN]; 2103 #endif 2104 int peer_id; 2105 uint16_t ast_hash; 2106 uint8_t pdev_id; 2107 uint16_t hw_peer_id; 2108 #if 0 2109 /* protected by ab->data_lock */ 2110 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; 2111 #endif 2112 struct dp_rx_tid rx_tid[IEEE80211_NUM_TID + 1]; 2113 #if 0 2114 /* peer id based rhashtable list pointer */ 2115 struct rhash_head rhash_id; 2116 /* peer addr based rhashtable list pointer */ 2117 struct rhash_head rhash_addr; 2118 2119 /* Info used in MMIC verification of 2120 * RX fragments 2121 */ 2122 struct crypto_shash *tfm_mmic; 2123 u8 mcast_keyidx; 2124 u8 ucast_keyidx; 2125 u16 sec_type; 2126 u16 sec_type_grp; 2127 bool is_authorized; 2128 bool dp_setup_done; 2129 #endif 2130 }; 2131 2132 struct qwz_node { 2133 struct ieee80211_node ni; 2134 struct ath12k_peer peer; 2135 unsigned int flags; 2136 #define QWZ_NODE_FLAG_HAVE_PAIRWISE_KEY 0x01 2137 #define QWZ_NODE_FLAG_HAVE_GROUP_KEY 0x02 2138 }; 2139 2140 struct ieee80211_node *qwz_node_alloc(struct ieee80211com *); 2141 int qwz_set_key(struct ieee80211com *, struct ieee80211_node *, 2142 struct ieee80211_key *); 2143 void qwz_delete_key(struct ieee80211com *, struct ieee80211_node *, 2144 struct ieee80211_key *); 2145 2146 void qwz_qrtr_recv_msg(struct qwz_softc *, struct mbuf *); 2147 2148 int qwz_hal_srng_init(struct qwz_softc *); 2149 2150 int qwz_ce_alloc_pipes(struct qwz_softc *); 2151 void qwz_ce_free_pipes(struct qwz_softc *); 2152 void qwz_ce_rx_post_buf(struct qwz_softc *); 2153 void qwz_ce_get_shadow_config(struct qwz_softc *, uint32_t **, uint32_t *); 2154 2155 static inline unsigned int 2156 qwz_roundup_pow_of_two(unsigned int i) 2157 { 2158 return (powerof2(i) ? i : (1 << (fls(i) - 1))); 2159 } 2160 2161 static inline unsigned int 2162 qwz_ce_get_attr_flags(struct qwz_softc *sc, int ce_id) 2163 { 2164 KASSERT(ce_id < sc->hw_params.ce_count); 2165 return sc->hw_params.host_ce_config[ce_id].flags; 2166 } 2167 2168 static inline enum ieee80211_edca_ac qwz_tid_to_ac(uint32_t tid) 2169 { 2170 return (((tid == 0) || (tid == 3)) ? EDCA_AC_BE : 2171 ((tid == 1) || (tid == 2)) ? EDCA_AC_BK : 2172 ((tid == 4) || (tid == 5)) ? EDCA_AC_VI : 2173 EDCA_AC_VO); 2174 } 2175