1 /* $OpenBSD: qwzreg.h,v 1.11 2024/12/23 00:12:44 patrick Exp $ */ 2 3 /* 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. 5 * Copyright (c) 2018-2021 The Linux Foundation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted (subject to the limitations in the disclaimer 10 * below) provided that the following conditions are met: 11 * 12 * * Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * * Neither the name of [Owner Organization] nor the names of its 20 * contributors may be used to endorse or promote products derived from 21 * this software without specific prior written permission. 22 * 23 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY 24 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 25 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT 26 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 28 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * core.h 39 */ 40 41 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 42 43 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 44 45 /* Pending management packets threshold for dropping probe responses */ 46 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 47 48 #define ATH12K_INVALID_HW_MAC_ID 0xFF 49 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 50 51 enum ath12k_hw_rev { 52 ATH12K_HW_QCN9274_HW10, 53 ATH12K_HW_QCN9274_HW20, 54 ATH12K_HW_WCN7850_HW20 55 }; 56 57 enum ath12k_firmware_mode { 58 /* the default mode, standard 802.11 functionality */ 59 ATH12K_FIRMWARE_MODE_NORMAL, 60 61 /* factory tests etc */ 62 ATH12K_FIRMWARE_MODE_FTM, 63 64 /* Cold boot calibration */ 65 ATH12K_FIRMWARE_MODE_COLD_BOOT = 7, 66 }; 67 68 enum ath12k_crypt_mode { 69 /* Only use hardware crypto engine */ 70 ATH12K_CRYPT_MODE_HW, 71 /* Only use software crypto */ 72 ATH12K_CRYPT_MODE_SW, 73 }; 74 75 /* IPQ8074 HW channel counters frequency value in hertz */ 76 #define IPQ8074_CC_FREQ_HERTZ 320000 77 78 #define ATH12K_MIN_5G_FREQ 4150 79 #define ATH12K_MIN_6G_FREQ 5925 80 #define ATH12K_MAX_6G_FREQ 7115 81 #define ATH12K_NUM_CHANS 102 82 #define ATH12K_MAX_5G_CHAN 177 83 84 /* Antenna noise floor */ 85 #define ATH12K_DEFAULT_NOISE_FLOOR -95 86 87 /* 88 * wmi.h 89 */ 90 91 #define PSOC_HOST_MAX_NUM_SS (8) 92 93 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 94 #define MAX_HE_NSS 8 95 #define MAX_HE_MODULATION 8 96 #define MAX_HE_RU 4 97 #define HE_MODULATION_NONE 7 98 #define HE_PET_0_USEC 0 99 #define HE_PET_8_USEC 1 100 #define HE_PET_16_USEC 2 101 102 #define WMI_MAX_CHAINS 8 103 104 #define WMI_MAX_NUM_SS MAX_HE_NSS 105 #define WMI_MAX_NUM_RU MAX_HE_RU 106 107 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 108 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 109 #define WMI_TLV_CMD_UNSUPPORTED 0 110 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 111 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 112 113 struct wmi_cmd_hdr { 114 uint32_t cmd_id; 115 } __packed; 116 117 struct wmi_tlv { 118 uint32_t header; 119 uint8_t value[]; 120 } __packed; 121 122 #define WMI_TLV_LEN GENMASK(15, 0) 123 #define WMI_TLV_TAG GENMASK(31, 16) 124 #define TLV_HDR_SIZE sizeof(uint32_t) /* wmi_tlv.header */ 125 126 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 127 #define WMI_MAX_MEM_REQS 32 128 #define ATH12K_MAX_HW_LISTEN_INTERVAL 5 129 130 #define WLAN_SCAN_MAX_HINT_S_SSID 10 131 #define WLAN_SCAN_MAX_HINT_BSSID 10 132 #define MAX_RNR_BSS 5 133 134 #define WLAN_SCAN_MAX_HINT_S_SSID 10 135 #define WLAN_SCAN_MAX_HINT_BSSID 10 136 #define MAX_RNR_BSS 5 137 138 #define WLAN_SCAN_PARAMS_MAX_SSID 16 139 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 140 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 141 142 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 143 144 #define MAX_WMI_UTF_LEN 252 145 #define WMI_BA_MODE_BUFFER_SIZE_256 3 146 147 /* 148 * HW mode config type replicated from FW header 149 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 150 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 151 * one in 2G and another in 5G. 152 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 153 * same band; no tx allowed. 154 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 155 * Support for both PHYs within one band is planned 156 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 157 * but could be extended to other bands in the future. 158 * The separation of the band between the two PHYs needs 159 * to be communicated separately. 160 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 161 * as in WMI_HW_MODE_SBS, and 3rd on the other band 162 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capable of both 2G and 163 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 164 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 165 */ 166 enum wmi_host_hw_mode_config_type { 167 WMI_HOST_HW_MODE_SINGLE = 0, 168 WMI_HOST_HW_MODE_DBS = 1, 169 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 170 WMI_HOST_HW_MODE_SBS = 3, 171 WMI_HOST_HW_MODE_DBS_SBS = 4, 172 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 173 174 /* keep last */ 175 WMI_HOST_HW_MODE_MAX 176 }; 177 178 /* HW mode priority values used to detect the preferred HW mode 179 * on the available modes. 180 */ 181 enum wmi_host_hw_mode_priority { 182 WMI_HOST_HW_MODE_DBS_SBS_PRI, 183 WMI_HOST_HW_MODE_DBS_PRI, 184 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 185 WMI_HOST_HW_MODE_SBS_PRI, 186 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 187 WMI_HOST_HW_MODE_SINGLE_PRI, 188 189 /* keep last the lowest priority */ 190 WMI_HOST_HW_MODE_MAX_PRI 191 }; 192 193 enum WMI_HOST_WLAN_BAND { 194 WMI_HOST_WLAN_2G_CAP = 0x1, 195 WMI_HOST_WLAN_5G_CAP = 0x2, 196 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 197 }; 198 199 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 200 * Used only for HE auto rate mode. 201 */ 202 enum { 203 /* HE LTF related configuration */ 204 WMI_HE_AUTORATE_LTF_1X = BIT(0), 205 WMI_HE_AUTORATE_LTF_2X = BIT(1), 206 WMI_HE_AUTORATE_LTF_4X = BIT(2), 207 208 /* HE GI related configuration */ 209 WMI_AUTORATE_400NS_GI = BIT(8), 210 WMI_AUTORATE_800NS_GI = BIT(9), 211 WMI_AUTORATE_1600NS_GI = BIT(10), 212 WMI_AUTORATE_3200NS_GI = BIT(11), 213 }; 214 215 enum { 216 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, 217 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, 218 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, 219 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, 220 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, 221 }; 222 223 /* 224 * wmi command groups. 225 */ 226 enum wmi_cmd_group { 227 /* 0 to 2 are reserved */ 228 WMI_GRP_START = 0x3, 229 WMI_GRP_SCAN = WMI_GRP_START, 230 WMI_GRP_PDEV = 0x4, 231 WMI_GRP_VDEV = 0x5, 232 WMI_GRP_PEER = 0x6, 233 WMI_GRP_MGMT = 0x7, 234 WMI_GRP_BA_NEG = 0x8, 235 WMI_GRP_STA_PS = 0x9, 236 WMI_GRP_DFS = 0xa, 237 WMI_GRP_ROAM = 0xb, 238 WMI_GRP_OFL_SCAN = 0xc, 239 WMI_GRP_P2P = 0xd, 240 WMI_GRP_AP_PS = 0xe, 241 WMI_GRP_RATE_CTRL = 0xf, 242 WMI_GRP_PROFILE = 0x10, 243 WMI_GRP_SUSPEND = 0x11, 244 WMI_GRP_BCN_FILTER = 0x12, 245 WMI_GRP_WOW = 0x13, 246 WMI_GRP_RTT = 0x14, 247 WMI_GRP_SPECTRAL = 0x15, 248 WMI_GRP_STATS = 0x16, 249 WMI_GRP_ARP_NS_OFL = 0x17, 250 WMI_GRP_NLO_OFL = 0x18, 251 WMI_GRP_GTK_OFL = 0x19, 252 WMI_GRP_CSA_OFL = 0x1a, 253 WMI_GRP_CHATTER = 0x1b, 254 WMI_GRP_TID_ADDBA = 0x1c, 255 WMI_GRP_MISC = 0x1d, 256 WMI_GRP_GPIO = 0x1e, 257 WMI_GRP_FWTEST = 0x1f, 258 WMI_GRP_TDLS = 0x20, 259 WMI_GRP_RESMGR = 0x21, 260 WMI_GRP_STA_SMPS = 0x22, 261 WMI_GRP_WLAN_HB = 0x23, 262 WMI_GRP_RMC = 0x24, 263 WMI_GRP_MHF_OFL = 0x25, 264 WMI_GRP_LOCATION_SCAN = 0x26, 265 WMI_GRP_OEM = 0x27, 266 WMI_GRP_NAN = 0x28, 267 WMI_GRP_COEX = 0x29, 268 WMI_GRP_OBSS_OFL = 0x2a, 269 WMI_GRP_LPI = 0x2b, 270 WMI_GRP_EXTSCAN = 0x2c, 271 WMI_GRP_DHCP_OFL = 0x2d, 272 WMI_GRP_IPA = 0x2e, 273 WMI_GRP_MDNS_OFL = 0x2f, 274 WMI_GRP_SAP_OFL = 0x30, 275 WMI_GRP_OCB = 0x31, 276 WMI_GRP_SOC = 0x32, 277 WMI_GRP_PKT_FILTER = 0x33, 278 WMI_GRP_MAWC = 0x34, 279 WMI_GRP_PMF_OFFLOAD = 0x35, 280 WMI_GRP_BPF_OFFLOAD = 0x36, 281 WMI_GRP_NAN_DATA = 0x37, 282 WMI_GRP_PROTOTYPE = 0x38, 283 WMI_GRP_MONITOR = 0x39, 284 WMI_GRP_REGULATORY = 0x3a, 285 WMI_GRP_HW_DATA_FILTER = 0x3b, 286 WMI_GRP_WLM = 0x3c, 287 WMI_GRP_11K_OFFLOAD = 0x3d, 288 WMI_GRP_TWT = 0x3e, 289 WMI_GRP_MOTION_DET = 0x3f, 290 WMI_GRP_SPATIAL_REUSE = 0x40, 291 }; 292 293 294 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 295 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 296 297 #define WMI_CMD_UNSUPPORTED 0 298 299 enum wmi_tlv_cmd_id { 300 WMI_INIT_CMDID = 0x1, 301 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 302 WMI_STOP_SCAN_CMDID, 303 WMI_SCAN_CHAN_LIST_CMDID, 304 WMI_SCAN_SCH_PRIO_TBL_CMDID, 305 WMI_SCAN_UPDATE_REQUEST_CMDID, 306 WMI_SCAN_PROB_REQ_OUI_CMDID, 307 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 308 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 309 WMI_PDEV_SET_CHANNEL_CMDID, 310 WMI_PDEV_SET_PARAM_CMDID, 311 WMI_PDEV_PKTLOG_ENABLE_CMDID, 312 WMI_PDEV_PKTLOG_DISABLE_CMDID, 313 WMI_PDEV_SET_WMM_PARAMS_CMDID, 314 WMI_PDEV_SET_HT_CAP_IE_CMDID, 315 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 316 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 317 WMI_PDEV_SET_QUIET_MODE_CMDID, 318 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 319 WMI_PDEV_GET_TPC_CONFIG_CMDID, 320 WMI_PDEV_SET_BASE_MACADDR_CMDID, 321 WMI_PDEV_DUMP_CMDID, 322 WMI_PDEV_SET_LED_CONFIG_CMDID, 323 WMI_PDEV_GET_TEMPERATURE_CMDID, 324 WMI_PDEV_SET_LED_FLASHING_CMDID, 325 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 326 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 327 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 328 WMI_PDEV_SET_CTL_TABLE_CMDID, 329 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 330 WMI_PDEV_FIPS_CMDID, 331 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 332 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 333 WMI_PDEV_GET_NFCAL_POWER_CMDID, 334 WMI_PDEV_GET_TPC_CMDID, 335 WMI_MIB_STATS_ENABLE_CMDID, 336 WMI_PDEV_SET_PCL_CMDID, 337 WMI_PDEV_SET_HW_MODE_CMDID, 338 WMI_PDEV_SET_MAC_CONFIG_CMDID, 339 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 340 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 341 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 342 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 343 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 344 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 345 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 346 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 347 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 348 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 349 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 350 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 351 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 352 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 353 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 354 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 355 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 356 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 357 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 358 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 359 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 360 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 361 WMI_PDEV_PKTLOG_FILTER_CMDID, 362 WMI_PDEV_SET_RAP_CONFIG_CMDID, 363 WMI_PDEV_DSM_FILTER_CMDID, 364 WMI_PDEV_FRAME_INJECT_CMDID, 365 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 366 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 367 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 368 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 369 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 370 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 371 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 372 WMI_PDEV_GET_TPC_STATS_CMDID, 373 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 374 WMI_PDEV_GET_DPD_STATUS_CMDID, 375 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 376 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 377 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 378 WMI_VDEV_DELETE_CMDID, 379 WMI_VDEV_START_REQUEST_CMDID, 380 WMI_VDEV_RESTART_REQUEST_CMDID, 381 WMI_VDEV_UP_CMDID, 382 WMI_VDEV_STOP_CMDID, 383 WMI_VDEV_DOWN_CMDID, 384 WMI_VDEV_SET_PARAM_CMDID, 385 WMI_VDEV_INSTALL_KEY_CMDID, 386 WMI_VDEV_WNM_SLEEPMODE_CMDID, 387 WMI_VDEV_WMM_ADDTS_CMDID, 388 WMI_VDEV_WMM_DELTS_CMDID, 389 WMI_VDEV_SET_WMM_PARAMS_CMDID, 390 WMI_VDEV_SET_GTX_PARAMS_CMDID, 391 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 392 WMI_VDEV_PLMREQ_START_CMDID, 393 WMI_VDEV_PLMREQ_STOP_CMDID, 394 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 395 WMI_VDEV_SET_IE_CMDID, 396 WMI_VDEV_RATEMASK_CMDID, 397 WMI_VDEV_ATF_REQUEST_CMDID, 398 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 399 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 400 WMI_VDEV_SET_QUIET_MODE_CMDID, 401 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 402 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 403 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 404 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 405 WMI_PEER_DELETE_CMDID, 406 WMI_PEER_FLUSH_TIDS_CMDID, 407 WMI_PEER_SET_PARAM_CMDID, 408 WMI_PEER_ASSOC_CMDID, 409 WMI_PEER_ADD_WDS_ENTRY_CMDID, 410 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 411 WMI_PEER_MCAST_GROUP_CMDID, 412 WMI_PEER_INFO_REQ_CMDID, 413 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 414 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 415 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 416 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 417 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 418 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 419 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 420 WMI_PEER_ATF_REQUEST_CMDID, 421 WMI_PEER_BWF_REQUEST_CMDID, 422 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 423 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 424 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 425 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 426 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 427 WMI_PDEV_SEND_BCN_CMDID, 428 WMI_BCN_TMPL_CMDID, 429 WMI_BCN_FILTER_RX_CMDID, 430 WMI_PRB_REQ_FILTER_RX_CMDID, 431 WMI_MGMT_TX_CMDID, 432 WMI_PRB_TMPL_CMDID, 433 WMI_MGMT_TX_SEND_CMDID, 434 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 435 WMI_PDEV_SEND_FD_CMDID, 436 WMI_BCN_OFFLOAD_CTRL_CMDID, 437 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 438 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 439 WMI_FILS_DISCOVERY_TMPL_CMDID, 440 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 441 WMI_ADDBA_SEND_CMDID, 442 WMI_ADDBA_STATUS_CMDID, 443 WMI_DELBA_SEND_CMDID, 444 WMI_ADDBA_SET_RESP_CMDID, 445 WMI_SEND_SINGLEAMSDU_CMDID, 446 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 447 WMI_STA_POWERSAVE_PARAM_CMDID, 448 WMI_STA_MIMO_PS_MODE_CMDID, 449 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 450 WMI_PDEV_DFS_DISABLE_CMDID, 451 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 452 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 453 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 454 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 455 WMI_VDEV_ADFS_CH_CFG_CMDID, 456 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 457 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 458 WMI_ROAM_SCAN_RSSI_THRESHOLD, 459 WMI_ROAM_SCAN_PERIOD, 460 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 461 WMI_ROAM_AP_PROFILE, 462 WMI_ROAM_CHAN_LIST, 463 WMI_ROAM_SCAN_CMD, 464 WMI_ROAM_SYNCH_COMPLETE, 465 WMI_ROAM_SET_RIC_REQUEST_CMDID, 466 WMI_ROAM_INVOKE_CMDID, 467 WMI_ROAM_FILTER_CMDID, 468 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 469 WMI_ROAM_CONFIGURE_MAWC_CMDID, 470 WMI_ROAM_SET_MBO_PARAM_CMDID, 471 WMI_ROAM_PER_CONFIG_CMDID, 472 WMI_ROAM_BTM_CONFIG_CMDID, 473 WMI_ENABLE_FILS_CMDID, 474 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 475 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 476 WMI_OFL_SCAN_PERIOD, 477 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 478 WMI_P2P_DEV_SET_DISCOVERABILITY, 479 WMI_P2P_GO_SET_BEACON_IE, 480 WMI_P2P_GO_SET_PROBE_RESP_IE, 481 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 482 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 483 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 484 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 485 WMI_P2P_SET_OPPPS_PARAM_CMDID, 486 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 487 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 488 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 489 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 490 WMI_AP_PS_EGAP_PARAM_CMDID, 491 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 492 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 493 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 494 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 495 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 496 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 497 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 498 WMI_PDEV_RESUME_CMDID, 499 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 500 WMI_RMV_BCN_FILTER_CMDID, 501 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 502 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 503 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 504 WMI_WOW_ENABLE_CMDID, 505 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 506 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 507 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 508 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 509 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 510 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 511 WMI_EXTWOW_ENABLE_CMDID, 512 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 513 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 514 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 515 WMI_WOW_UDP_SVC_OFLD_CMDID, 516 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 517 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 518 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 519 WMI_RTT_TSF_CMDID, 520 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 521 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 522 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 523 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 524 WMI_REQUEST_STATS_EXT_CMDID, 525 WMI_REQUEST_LINK_STATS_CMDID, 526 WMI_START_LINK_STATS_CMDID, 527 WMI_CLEAR_LINK_STATS_CMDID, 528 WMI_GET_FW_MEM_DUMP_CMDID, 529 WMI_DEBUG_MESG_FLUSH_CMDID, 530 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 531 WMI_REQUEST_WLAN_STATS_CMDID, 532 WMI_REQUEST_RCPI_CMDID, 533 WMI_REQUEST_PEER_STATS_INFO_CMDID, 534 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 535 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 536 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 537 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 538 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 539 WMI_APFIND_CMDID, 540 WMI_PASSPOINT_LIST_CONFIG_CMDID, 541 WMI_NLO_CONFIGURE_MAWC_CMDID, 542 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 543 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 544 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 545 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 546 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 547 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 548 WMI_CHATTER_COALESCING_QUERY_CMDID, 549 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 550 WMI_PEER_TID_DELBA_CMDID, 551 WMI_STA_DTIM_PS_METHOD_CMDID, 552 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 553 WMI_STA_KEEPALIVE_CMDID, 554 WMI_BA_REQ_SSN_CMDID, 555 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 556 WMI_PDEV_UTF_CMDID, 557 WMI_DBGLOG_CFG_CMDID, 558 WMI_PDEV_QVIT_CMDID, 559 WMI_PDEV_FTM_INTG_CMDID, 560 WMI_VDEV_SET_KEEPALIVE_CMDID, 561 WMI_VDEV_GET_KEEPALIVE_CMDID, 562 WMI_FORCE_FW_HANG_CMDID, 563 WMI_SET_MCASTBCAST_FILTER_CMDID, 564 WMI_THERMAL_MGMT_CMDID, 565 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 566 WMI_TPC_CHAINMASK_CONFIG_CMDID, 567 WMI_SET_ANTENNA_DIVERSITY_CMDID, 568 WMI_OCB_SET_SCHED_CMDID, 569 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 570 WMI_LRO_CONFIG_CMDID, 571 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 572 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 573 WMI_VDEV_WISA_CMDID, 574 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 575 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 576 WMI_READ_DATA_FROM_FLASH_CMDID, 577 WMI_THERM_THROT_SET_CONF_CMDID, 578 WMI_RUNTIME_DPD_RECAL_CMDID, 579 WMI_GET_TPC_POWER_CMDID, 580 WMI_IDLE_TRIGGER_MONITOR_CMDID, 581 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 582 WMI_GPIO_OUTPUT_CMDID, 583 WMI_TXBF_CMDID, 584 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 585 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 586 WMI_UNIT_TEST_CMDID, 587 WMI_FWTEST_CMDID, 588 WMI_QBOOST_CFG_CMDID, 589 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 590 WMI_TDLS_PEER_UPDATE_CMDID, 591 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 592 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 593 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 594 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 595 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 596 WMI_STA_SMPS_PARAM_CMDID, 597 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 598 WMI_HB_SET_TCP_PARAMS_CMDID, 599 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 600 WMI_HB_SET_UDP_PARAMS_CMDID, 601 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 602 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 603 WMI_RMC_SET_ACTION_PERIOD_CMDID, 604 WMI_RMC_CONFIG_CMDID, 605 WMI_RMC_SET_MANUAL_LEADER_CMDID, 606 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 607 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 608 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 609 WMI_BATCH_SCAN_DISABLE_CMDID, 610 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 611 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 612 WMI_OEM_REQUEST_CMDID, 613 WMI_LPI_OEM_REQ_CMDID, 614 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 615 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 616 WMI_CHAN_AVOID_UPDATE_CMDID, 617 WMI_COEX_CONFIG_CMDID, 618 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 619 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 620 WMI_SAR_LIMITS_CMDID, 621 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 622 WMI_OBSS_SCAN_DISABLE_CMDID, 623 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 624 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 625 WMI_LPI_START_SCAN_CMDID, 626 WMI_LPI_STOP_SCAN_CMDID, 627 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 628 WMI_EXTSCAN_STOP_CMDID, 629 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 630 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 631 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 632 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 633 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 634 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 635 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 636 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 637 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 638 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 639 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 640 WMI_MDNS_SET_FQDN_CMDID, 641 WMI_MDNS_SET_RESPONSE_CMDID, 642 WMI_MDNS_GET_STATS_CMDID, 643 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 644 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 645 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 646 WMI_OCB_SET_UTC_TIME_CMDID, 647 WMI_OCB_START_TIMING_ADVERT_CMDID, 648 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 649 WMI_OCB_GET_TSF_TIMER_CMDID, 650 WMI_DCC_GET_STATS_CMDID, 651 WMI_DCC_CLEAR_STATS_CMDID, 652 WMI_DCC_UPDATE_NDL_CMDID, 653 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 654 WMI_SOC_SET_HW_MODE_CMDID, 655 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 656 WMI_SOC_SET_ANTENNA_MODE_CMDID, 657 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 658 WMI_PACKET_FILTER_ENABLE_CMDID, 659 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 660 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 661 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 662 WMI_BPF_GET_VDEV_STATS_CMDID, 663 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 664 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 665 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 666 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 667 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 668 WMI_11D_SCAN_START_CMDID, 669 WMI_11D_SCAN_STOP_CMDID, 670 WMI_SET_INIT_COUNTRY_CMDID, 671 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 672 WMI_NDP_INITIATOR_REQ_CMDID, 673 WMI_NDP_RESPONDER_REQ_CMDID, 674 WMI_NDP_END_REQ_CMDID, 675 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 676 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 677 WMI_TWT_DISABLE_CMDID, 678 WMI_TWT_ADD_DIALOG_CMDID, 679 WMI_TWT_DEL_DIALOG_CMDID, 680 WMI_TWT_PAUSE_DIALOG_CMDID, 681 WMI_TWT_RESUME_DIALOG_CMDID, 682 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 683 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 684 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 685 }; 686 687 enum wmi_tlv_event_id { 688 WMI_SERVICE_READY_EVENTID = 0x1, 689 WMI_READY_EVENTID, 690 WMI_SERVICE_AVAILABLE_EVENTID, 691 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 692 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 693 WMI_CHAN_INFO_EVENTID, 694 WMI_PHYERR_EVENTID, 695 WMI_PDEV_DUMP_EVENTID, 696 WMI_TX_PAUSE_EVENTID, 697 WMI_DFS_RADAR_EVENTID, 698 WMI_PDEV_L1SS_TRACK_EVENTID, 699 WMI_PDEV_TEMPERATURE_EVENTID, 700 WMI_SERVICE_READY_EXT_EVENTID, 701 WMI_PDEV_FIPS_EVENTID, 702 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 703 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 704 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 705 WMI_PDEV_TPC_EVENTID, 706 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 707 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 708 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 709 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 710 WMI_PDEV_ANTDIV_STATUS_EVENTID, 711 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 712 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 713 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 714 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 715 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 716 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 717 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 718 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 719 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 720 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 721 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 722 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 723 WMI_PDEV_RAP_INFO_EVENTID, 724 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 725 WMI_SERVICE_READY_EXT2_EVENTID, 726 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 727 WMI_VDEV_STOPPED_EVENTID, 728 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 729 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 730 WMI_VDEV_TSF_REPORT_EVENTID, 731 WMI_VDEV_DELETE_RESP_EVENTID, 732 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 733 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 734 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 735 WMI_PEER_INFO_EVENTID, 736 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 737 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 738 WMI_PEER_STATE_EVENTID, 739 WMI_PEER_ASSOC_CONF_EVENTID, 740 WMI_PEER_DELETE_RESP_EVENTID, 741 WMI_PEER_RATECODE_LIST_EVENTID, 742 WMI_WDS_PEER_EVENTID, 743 WMI_PEER_STA_PS_STATECHG_EVENTID, 744 WMI_PEER_ANTDIV_INFO_EVENTID, 745 WMI_PEER_RESERVED0_EVENTID, 746 WMI_PEER_RESERVED1_EVENTID, 747 WMI_PEER_RESERVED2_EVENTID, 748 WMI_PEER_RESERVED3_EVENTID, 749 WMI_PEER_RESERVED4_EVENTID, 750 WMI_PEER_RESERVED5_EVENTID, 751 WMI_PEER_RESERVED6_EVENTID, 752 WMI_PEER_RESERVED7_EVENTID, 753 WMI_PEER_RESERVED8_EVENTID, 754 WMI_PEER_RESERVED9_EVENTID, 755 WMI_PEER_RESERVED10_EVENTID, 756 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 757 WMI_PEER_TX_PN_RESPONSE_EVENTID, 758 WMI_PEER_CFR_CAPTURE_EVENTID, 759 WMI_PEER_CREATE_CONF_EVENTID, 760 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 761 WMI_HOST_SWBA_EVENTID, 762 WMI_TBTTOFFSET_UPDATE_EVENTID, 763 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 764 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 765 WMI_MGMT_TX_COMPLETION_EVENTID, 766 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 767 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 768 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 769 WMI_HOST_FILS_DISCOVERY_EVENTID, 770 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 771 WMI_TX_ADDBA_COMPLETE_EVENTID, 772 WMI_BA_RSP_SSN_EVENTID, 773 WMI_AGGR_STATE_TRIG_EVENTID, 774 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 775 WMI_PROFILE_MATCH, 776 WMI_ROAM_SYNCH_EVENTID, 777 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 778 WMI_P2P_NOA_EVENTID, 779 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 780 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 781 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 782 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 783 WMI_D0_WOW_DISABLE_ACK_EVENTID, 784 WMI_WOW_INITIAL_WAKEUP_EVENTID, 785 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 786 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 787 WMI_RTT_ERROR_REPORT_EVENTID, 788 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 789 WMI_IFACE_LINK_STATS_EVENTID, 790 WMI_PEER_LINK_STATS_EVENTID, 791 WMI_RADIO_LINK_STATS_EVENTID, 792 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 793 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 794 WMI_INST_RSSI_STATS_EVENTID, 795 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 796 WMI_REPORT_STATS_EVENTID, 797 WMI_UPDATE_RCPI_EVENTID, 798 WMI_PEER_STATS_INFO_EVENTID, 799 WMI_RADIO_CHAN_STATS_EVENTID, 800 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 801 WMI_NLO_SCAN_COMPLETE_EVENTID, 802 WMI_APFIND_EVENTID, 803 WMI_PASSPOINT_MATCH_EVENTID, 804 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 805 WMI_GTK_REKEY_FAIL_EVENTID, 806 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 807 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 808 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 809 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 810 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 811 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 812 WMI_PDEV_UTF_EVENTID, 813 WMI_DEBUG_MESG_EVENTID, 814 WMI_UPDATE_STATS_EVENTID, 815 WMI_DEBUG_PRINT_EVENTID, 816 WMI_DCS_INTERFERENCE_EVENTID, 817 WMI_PDEV_QVIT_EVENTID, 818 WMI_WLAN_PROFILE_DATA_EVENTID, 819 WMI_PDEV_FTM_INTG_EVENTID, 820 WMI_WLAN_FREQ_AVOID_EVENTID, 821 WMI_VDEV_GET_KEEPALIVE_EVENTID, 822 WMI_THERMAL_MGMT_EVENTID, 823 WMI_DIAG_DATA_CONTAINER_EVENTID, 824 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 825 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 826 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 827 WMI_DIAG_EVENTID, 828 WMI_OCB_SET_SCHED_EVENTID, 829 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 830 WMI_RSSI_BREACH_EVENTID, 831 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 832 WMI_PDEV_UTF_SCPC_EVENTID, 833 WMI_READ_DATA_FROM_FLASH_EVENTID, 834 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 835 WMI_PKGID_EVENTID, 836 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 837 WMI_UPLOADH_EVENTID, 838 WMI_CAPTUREH_EVENTID, 839 WMI_RFKILL_STATE_CHANGE_EVENTID, 840 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 841 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 842 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 843 WMI_BATCH_SCAN_RESULT_EVENTID, 844 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 845 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 846 WMI_OEM_ERROR_REPORT_EVENTID, 847 WMI_OEM_RESPONSE_EVENTID, 848 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 849 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 850 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 851 WMI_NAN_STARTED_CLUSTER_EVENTID, 852 WMI_NAN_JOINED_CLUSTER_EVENTID, 853 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 854 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 855 WMI_LPI_STATUS_EVENTID, 856 WMI_LPI_HANDOFF_EVENTID, 857 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 858 WMI_EXTSCAN_OPERATION_EVENTID, 859 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 860 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 861 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 862 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 863 WMI_EXTSCAN_CAPABILITIES_EVENTID, 864 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 865 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 866 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 867 WMI_SAP_OFL_DEL_STA_EVENTID, 868 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 869 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 870 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 871 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 872 WMI_DCC_GET_STATS_RESP_EVENTID, 873 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 874 WMI_DCC_STATS_EVENTID, 875 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 876 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 877 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 878 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 879 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 880 WMI_BPF_VDEV_STATS_INFO_EVENTID, 881 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 882 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 883 WMI_11D_NEW_COUNTRY_EVENTID, 884 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 885 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 886 WMI_NDP_INITIATOR_RSP_EVENTID, 887 WMI_NDP_RESPONDER_RSP_EVENTID, 888 WMI_NDP_END_RSP_EVENTID, 889 WMI_NDP_INDICATION_EVENTID, 890 WMI_NDP_CONFIRM_EVENTID, 891 WMI_NDP_END_INDICATION_EVENTID, 892 893 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 894 WMI_TWT_DISABLE_EVENTID, 895 WMI_TWT_ADD_DIALOG_EVENTID, 896 WMI_TWT_DEL_DIALOG_EVENTID, 897 WMI_TWT_PAUSE_DIALOG_EVENTID, 898 WMI_TWT_RESUME_DIALOG_EVENTID, 899 }; 900 901 enum wmi_tlv_pdev_param { 902 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 903 WMI_PDEV_PARAM_RX_CHAIN_MASK, 904 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 905 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 906 WMI_PDEV_PARAM_TXPOWER_SCALE, 907 WMI_PDEV_PARAM_BEACON_GEN_MODE, 908 WMI_PDEV_PARAM_BEACON_TX_MODE, 909 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 910 WMI_PDEV_PARAM_PROTECTION_MODE, 911 WMI_PDEV_PARAM_DYNAMIC_BW, 912 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 913 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 914 WMI_PDEV_PARAM_STA_KICKOUT_TH, 915 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 916 WMI_PDEV_PARAM_LTR_ENABLE, 917 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 918 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 919 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 920 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 921 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 922 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 923 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 924 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 925 WMI_PDEV_PARAM_L1SS_ENABLE, 926 WMI_PDEV_PARAM_DSLEEP_ENABLE, 927 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 928 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 929 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 930 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 931 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 932 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 933 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 934 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 935 WMI_PDEV_PARAM_PMF_QOS, 936 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 937 WMI_PDEV_PARAM_DCS, 938 WMI_PDEV_PARAM_ANI_ENABLE, 939 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 940 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 941 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 942 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 943 WMI_PDEV_PARAM_DYNTXCHAIN, 944 WMI_PDEV_PARAM_PROXY_STA, 945 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 946 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 947 WMI_PDEV_PARAM_RFKILL_ENABLE, 948 WMI_PDEV_PARAM_BURST_DUR, 949 WMI_PDEV_PARAM_BURST_ENABLE, 950 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 951 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 952 WMI_PDEV_PARAM_L1SS_TRACK, 953 WMI_PDEV_PARAM_HYST_EN, 954 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 955 WMI_PDEV_PARAM_LED_SYS_STATE, 956 WMI_PDEV_PARAM_LED_ENABLE, 957 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 958 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 959 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 960 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 961 WMI_PDEV_PARAM_CTS_CBW, 962 WMI_PDEV_PARAM_WNTS_CONFIG, 963 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 964 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 965 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 966 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 967 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 968 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 969 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 970 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 971 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 972 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 973 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 974 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 975 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 976 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 977 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 978 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 979 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 980 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 981 WMI_PDEV_PARAM_AGGR_BURST, 982 WMI_PDEV_PARAM_RX_DECAP_MODE, 983 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 984 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 985 WMI_PDEV_PARAM_ANTENNA_GAIN, 986 WMI_PDEV_PARAM_RX_FILTER, 987 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 988 WMI_PDEV_PARAM_PROXY_STA_MODE, 989 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 990 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 991 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 992 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 993 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 994 WMI_PDEV_PARAM_BLOCK_INTERBSS, 995 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 996 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 997 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 998 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 999 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 1000 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 1001 WMI_PDEV_PARAM_EN_STATS, 1002 WMI_PDEV_PARAM_MU_GROUP_POLICY, 1003 WMI_PDEV_PARAM_NOISE_DETECTION, 1004 WMI_PDEV_PARAM_NOISE_THRESHOLD, 1005 WMI_PDEV_PARAM_DPD_ENABLE, 1006 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 1007 WMI_PDEV_PARAM_ATF_STRICT_SCH, 1008 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 1009 WMI_PDEV_PARAM_ANT_PLZN, 1010 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 1011 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 1012 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 1013 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 1014 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 1015 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 1016 WMI_PDEV_PARAM_CCA_THRESHOLD, 1017 WMI_PDEV_PARAM_RTS_FIXED_RATE, 1018 WMI_PDEV_PARAM_PDEV_RESET, 1019 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 1020 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 1021 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 1022 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 1023 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 1024 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 1025 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 1026 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 1027 WMI_PDEV_PARAM_PROPAGATION_DELAY, 1028 WMI_PDEV_PARAM_ENA_ANT_DIV, 1029 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 1030 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 1031 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 1032 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 1033 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 1034 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 1035 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 1036 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 1037 WMI_PDEV_PARAM_TX_SCH_DELAY, 1038 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 1039 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 1040 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 1041 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 1042 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 1043 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 1044 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 1045 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 1046 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 1047 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 1048 }; 1049 1050 enum wmi_tlv_vdev_param { 1051 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 1052 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 1053 WMI_VDEV_PARAM_BEACON_INTERVAL, 1054 WMI_VDEV_PARAM_LISTEN_INTERVAL, 1055 WMI_VDEV_PARAM_MULTICAST_RATE, 1056 WMI_VDEV_PARAM_MGMT_TX_RATE, 1057 WMI_VDEV_PARAM_SLOT_TIME, 1058 WMI_VDEV_PARAM_PREAMBLE, 1059 WMI_VDEV_PARAM_SWBA_TIME, 1060 WMI_VDEV_STATS_UPDATE_PERIOD, 1061 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 1062 WMI_VDEV_HOST_SWBA_INTERVAL, 1063 WMI_VDEV_PARAM_DTIM_PERIOD, 1064 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 1065 WMI_VDEV_PARAM_WDS, 1066 WMI_VDEV_PARAM_ATIM_WINDOW, 1067 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 1068 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 1069 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 1070 WMI_VDEV_PARAM_FEATURE_WMM, 1071 WMI_VDEV_PARAM_CHWIDTH, 1072 WMI_VDEV_PARAM_CHEXTOFFSET, 1073 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1074 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1075 WMI_VDEV_PARAM_MGMT_RATE, 1076 WMI_VDEV_PARAM_PROTECTION_MODE, 1077 WMI_VDEV_PARAM_FIXED_RATE, 1078 WMI_VDEV_PARAM_SGI, 1079 WMI_VDEV_PARAM_LDPC, 1080 WMI_VDEV_PARAM_TX_STBC, 1081 WMI_VDEV_PARAM_RX_STBC, 1082 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1083 WMI_VDEV_PARAM_DEF_KEYID, 1084 WMI_VDEV_PARAM_NSS, 1085 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1086 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1087 WMI_VDEV_PARAM_MCAST_INDICATE, 1088 WMI_VDEV_PARAM_DHCP_INDICATE, 1089 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1090 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1091 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1092 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1093 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1094 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1095 WMI_VDEV_PARAM_TXBF, 1096 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1097 WMI_VDEV_PARAM_DROP_UNENCRY, 1098 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1099 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1100 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1101 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1102 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1103 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1104 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1105 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1106 WMI_VDEV_PARAM_TX_PWRLIMIT, 1107 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1108 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1109 WMI_VDEV_PARAM_ENABLE_RMC, 1110 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1111 WMI_VDEV_PARAM_MAX_RATE, 1112 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1113 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1114 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1115 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1116 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1117 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1118 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1119 WMI_VDEV_PARAM_INACTIVITY_CNT, 1120 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1121 WMI_VDEV_PARAM_DTIM_POLICY, 1122 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1123 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1124 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1125 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1126 WMI_VDEV_PARAM_DISCONNECT_TH, 1127 WMI_VDEV_PARAM_RTSCTS_RATE, 1128 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1129 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1130 WMI_VDEV_PARAM_TXPOWER_SCALE, 1131 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1132 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1133 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1134 WMI_VDEV_PARAM_CABQ_MAXDUR, 1135 WMI_VDEV_PARAM_MFPTEST_SET, 1136 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1137 WMI_VDEV_PARAM_VHT_SGIMASK, 1138 WMI_VDEV_PARAM_VHT80_RATEMASK, 1139 WMI_VDEV_PARAM_PROXY_STA, 1140 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1141 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1142 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1143 WMI_VDEV_PARAM_SENSOR_AP, 1144 WMI_VDEV_PARAM_BEACON_RATE, 1145 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1146 WMI_VDEV_PARAM_STA_KICKOUT, 1147 WMI_VDEV_PARAM_CAPABILITIES, 1148 WMI_VDEV_PARAM_TSF_INCREMENT, 1149 WMI_VDEV_PARAM_AMPDU_PER_AC, 1150 WMI_VDEV_PARAM_RX_FILTER, 1151 WMI_VDEV_PARAM_MGMT_TX_POWER, 1152 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1153 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1154 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1155 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1156 WMI_VDEV_PARAM_HE_DCM, 1157 WMI_VDEV_PARAM_HE_RANGE_EXT, 1158 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1159 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1160 WMI_VDEV_PARAM_HE_LTF = 0x74, 1161 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1162 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1163 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1164 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1165 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1166 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1167 WMI_VDEV_PARAM_BSS_COLOR, 1168 WMI_VDEV_PARAM_SET_HEMU_MODE, 1169 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1170 }; 1171 1172 enum wmi_tlv_peer_flags { 1173 WMI_TLV_PEER_AUTH = 0x00000001, 1174 WMI_TLV_PEER_QOS = 0x00000002, 1175 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1176 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1177 WMI_TLV_PEER_APSD = 0x00000800, 1178 WMI_TLV_PEER_HT = 0x00001000, 1179 WMI_TLV_PEER_40MHZ = 0x00002000, 1180 WMI_TLV_PEER_STBC = 0x00008000, 1181 WMI_TLV_PEER_LDPC = 0x00010000, 1182 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1183 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1184 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1185 WMI_TLV_PEER_VHT = 0x02000000, 1186 WMI_TLV_PEER_80MHZ = 0x04000000, 1187 WMI_TLV_PEER_PMF = 0x08000000, 1188 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1189 WMI_PEER_160MHZ = 0x40000000, 1190 WMI_PEER_SAFEMODE_EN = 0x80000000, 1191 1192 }; 1193 1194 /** Enum list of TLV Tags for each parameter structure type. */ 1195 enum wmi_tlv_tag { 1196 WMI_TAG_LAST_RESERVED = 15, 1197 WMI_TAG_FIRST_ARRAY_ENUM, 1198 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1199 WMI_TAG_ARRAY_BYTE, 1200 WMI_TAG_ARRAY_STRUCT, 1201 WMI_TAG_ARRAY_FIXED_STRUCT, 1202 WMI_TAG_LAST_ARRAY_ENUM = 31, 1203 WMI_TAG_SERVICE_READY_EVENT, 1204 WMI_TAG_HAL_REG_CAPABILITIES, 1205 WMI_TAG_WLAN_HOST_MEM_REQ, 1206 WMI_TAG_READY_EVENT, 1207 WMI_TAG_SCAN_EVENT, 1208 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1209 WMI_TAG_CHAN_INFO_EVENT, 1210 WMI_TAG_COMB_PHYERR_RX_HDR, 1211 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1212 WMI_TAG_VDEV_STOPPED_EVENT, 1213 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1214 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1215 WMI_TAG_MGMT_RX_HDR, 1216 WMI_TAG_TBTT_OFFSET_EVENT, 1217 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1218 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1219 WMI_TAG_ROAM_EVENT, 1220 WMI_TAG_WOW_EVENT_INFO, 1221 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1222 WMI_TAG_RTT_EVENT_HEADER, 1223 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1224 WMI_TAG_RTT_MEAS_EVENT, 1225 WMI_TAG_ECHO_EVENT, 1226 WMI_TAG_FTM_INTG_EVENT, 1227 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1228 WMI_TAG_GPIO_INPUT_EVENT, 1229 WMI_TAG_CSA_EVENT, 1230 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1231 WMI_TAG_IGTK_INFO, 1232 WMI_TAG_DCS_INTERFERENCE_EVENT, 1233 WMI_TAG_ATH_DCS_CW_INT, 1234 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1235 WMI_TAG_ATH_DCS_CW_INT, 1236 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1237 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1238 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1239 WMI_TAG_WLAN_PROFILE_CTX_T, 1240 WMI_TAG_WLAN_PROFILE_T, 1241 WMI_TAG_PDEV_QVIT_EVENT, 1242 WMI_TAG_HOST_SWBA_EVENT, 1243 WMI_TAG_TIM_INFO, 1244 WMI_TAG_P2P_NOA_INFO, 1245 WMI_TAG_STATS_EVENT, 1246 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1247 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1248 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1249 WMI_TAG_INIT_CMD, 1250 WMI_TAG_RESOURCE_CONFIG, 1251 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1252 WMI_TAG_START_SCAN_CMD, 1253 WMI_TAG_STOP_SCAN_CMD, 1254 WMI_TAG_SCAN_CHAN_LIST_CMD, 1255 WMI_TAG_CHANNEL, 1256 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1257 WMI_TAG_PDEV_SET_PARAM_CMD, 1258 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1259 WMI_TAG_WMM_PARAMS, 1260 WMI_TAG_PDEV_SET_QUIET_CMD, 1261 WMI_TAG_VDEV_CREATE_CMD, 1262 WMI_TAG_VDEV_DELETE_CMD, 1263 WMI_TAG_VDEV_START_REQUEST_CMD, 1264 WMI_TAG_P2P_NOA_DESCRIPTOR, 1265 WMI_TAG_P2P_GO_SET_BEACON_IE, 1266 WMI_TAG_GTK_OFFLOAD_CMD, 1267 WMI_TAG_VDEV_UP_CMD, 1268 WMI_TAG_VDEV_STOP_CMD, 1269 WMI_TAG_VDEV_DOWN_CMD, 1270 WMI_TAG_VDEV_SET_PARAM_CMD, 1271 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1272 WMI_TAG_PEER_CREATE_CMD, 1273 WMI_TAG_PEER_DELETE_CMD, 1274 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1275 WMI_TAG_PEER_SET_PARAM_CMD, 1276 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1277 WMI_TAG_VHT_RATE_SET, 1278 WMI_TAG_BCN_TMPL_CMD, 1279 WMI_TAG_PRB_TMPL_CMD, 1280 WMI_TAG_BCN_PRB_INFO, 1281 WMI_TAG_PEER_TID_ADDBA_CMD, 1282 WMI_TAG_PEER_TID_DELBA_CMD, 1283 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1284 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1285 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1286 WMI_TAG_ROAM_SCAN_MODE, 1287 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1288 WMI_TAG_ROAM_SCAN_PERIOD, 1289 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1290 WMI_TAG_PDEV_SUSPEND_CMD, 1291 WMI_TAG_PDEV_RESUME_CMD, 1292 WMI_TAG_ADD_BCN_FILTER_CMD, 1293 WMI_TAG_RMV_BCN_FILTER_CMD, 1294 WMI_TAG_WOW_ENABLE_CMD, 1295 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1296 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1297 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1298 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1299 WMI_TAG_ARP_OFFLOAD_TUPLE, 1300 WMI_TAG_NS_OFFLOAD_TUPLE, 1301 WMI_TAG_FTM_INTG_CMD, 1302 WMI_TAG_STA_KEEPALIVE_CMD, 1303 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1304 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1305 WMI_TAG_AP_PS_PEER_CMD, 1306 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1307 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1308 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1309 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1310 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1311 WMI_TAG_WOW_DEL_PATTERN_CMD, 1312 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1313 WMI_TAG_RTT_MEASREQ_HEAD, 1314 WMI_TAG_RTT_MEASREQ_BODY, 1315 WMI_TAG_RTT_TSF_CMD, 1316 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1317 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1318 WMI_TAG_REQUEST_STATS_CMD, 1319 WMI_TAG_NLO_CONFIG_CMD, 1320 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1321 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1322 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1323 WMI_TAG_CHATTER_SET_MODE_CMD, 1324 WMI_TAG_ECHO_CMD, 1325 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1326 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1327 WMI_TAG_FORCE_FW_HANG_CMD, 1328 WMI_TAG_GPIO_CONFIG_CMD, 1329 WMI_TAG_GPIO_OUTPUT_CMD, 1330 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1331 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1332 WMI_TAG_BCN_TX_HDR, 1333 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1334 WMI_TAG_MGMT_TX_HDR, 1335 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1336 WMI_TAG_ADDBA_SEND_CMD, 1337 WMI_TAG_DELBA_SEND_CMD, 1338 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1339 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1340 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1341 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1342 WMI_TAG_PDEV_SET_HT_IE_CMD, 1343 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1344 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1345 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1346 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1347 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1348 WMI_TAG_PEER_MCAST_GROUP_CMD, 1349 WMI_TAG_ROAM_AP_PROFILE, 1350 WMI_TAG_AP_PROFILE, 1351 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1352 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1353 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1354 WMI_TAG_WOW_ADD_PATTERN_CMD, 1355 WMI_TAG_WOW_BITMAP_PATTERN_T, 1356 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1357 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1358 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1359 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1360 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1361 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1362 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1363 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1364 WMI_TAG_TXBF_CMD, 1365 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1366 WMI_TAG_NLO_EVENT, 1367 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1368 WMI_TAG_UPLOAD_H_HDR, 1369 WMI_TAG_CAPTURE_H_EVENT_HDR, 1370 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1371 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1372 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1373 WMI_TAG_VDEV_WMM_DELTS_CMD, 1374 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1375 WMI_TAG_TDLS_SET_STATE_CMD, 1376 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1377 WMI_TAG_TDLS_PEER_EVENT, 1378 WMI_TAG_TDLS_PEER_CAPABILITIES, 1379 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1380 WMI_TAG_ROAM_CHAN_LIST, 1381 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1382 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1383 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1384 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1385 WMI_TAG_BA_REQ_SSN_CMD, 1386 WMI_TAG_BA_RSP_SSN_EVENT, 1387 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1388 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1389 WMI_TAG_P2P_SET_OPPPS_CMD, 1390 WMI_TAG_P2P_SET_NOA_CMD, 1391 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1392 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1393 WMI_TAG_STA_SMPS_PARAM_CMD, 1394 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1395 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1396 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1397 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1398 WMI_TAG_P2P_NOA_EVENT, 1399 WMI_TAG_HB_SET_ENABLE_CMD, 1400 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1401 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1402 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1403 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1404 WMI_TAG_HB_IND_EVENT, 1405 WMI_TAG_TX_PAUSE_EVENT, 1406 WMI_TAG_RFKILL_EVENT, 1407 WMI_TAG_DFS_RADAR_EVENT, 1408 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1409 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1410 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1411 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1412 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1413 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1414 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1415 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1416 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1417 WMI_TAG_VDEV_PLMREQ_START_CMD, 1418 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1419 WMI_TAG_THERMAL_MGMT_CMD, 1420 WMI_TAG_THERMAL_MGMT_EVENT, 1421 WMI_TAG_PEER_INFO_REQ_CMD, 1422 WMI_TAG_PEER_INFO_EVENT, 1423 WMI_TAG_PEER_INFO, 1424 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1425 WMI_TAG_RMC_SET_MODE_CMD, 1426 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1427 WMI_TAG_RMC_CONFIG_CMD, 1428 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1429 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1430 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1431 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1432 WMI_TAG_NAN_CMD_PARAM, 1433 WMI_TAG_NAN_EVENT_HDR, 1434 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1435 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1436 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1437 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1438 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1439 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1440 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1441 WMI_TAG_ROAM_SCAN_CMD, 1442 WMI_TAG_REQ_STATS_EXT_CMD, 1443 WMI_TAG_STATS_EXT_EVENT, 1444 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1445 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1446 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1447 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1448 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1449 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1450 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1451 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1452 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1453 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1454 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1455 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1456 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1457 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1458 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1459 WMI_TAG_START_LINK_STATS_CMD, 1460 WMI_TAG_CLEAR_LINK_STATS_CMD, 1461 WMI_TAG_REQUEST_LINK_STATS_CMD, 1462 WMI_TAG_IFACE_LINK_STATS_EVENT, 1463 WMI_TAG_RADIO_LINK_STATS_EVENT, 1464 WMI_TAG_PEER_STATS_EVENT, 1465 WMI_TAG_CHANNEL_STATS, 1466 WMI_TAG_RADIO_LINK_STATS, 1467 WMI_TAG_RATE_STATS, 1468 WMI_TAG_PEER_LINK_STATS, 1469 WMI_TAG_WMM_AC_STATS, 1470 WMI_TAG_IFACE_LINK_STATS, 1471 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1472 WMI_TAG_LPI_START_SCAN_CMD, 1473 WMI_TAG_LPI_STOP_SCAN_CMD, 1474 WMI_TAG_LPI_RESULT_EVENT, 1475 WMI_TAG_PEER_STATE_EVENT, 1476 WMI_TAG_EXTSCAN_BUCKET_CMD, 1477 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1478 WMI_TAG_EXTSCAN_START_CMD, 1479 WMI_TAG_EXTSCAN_STOP_CMD, 1480 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1481 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1482 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1483 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1484 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1485 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1486 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1487 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1488 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1489 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1490 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1491 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1492 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1493 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1494 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1495 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1496 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1497 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1498 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1499 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1500 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1501 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1502 WMI_TAG_UNIT_TEST_CMD, 1503 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1504 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1505 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1506 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1507 WMI_TAG_ROAM_SYNCH_EVENT, 1508 WMI_TAG_ROAM_SYNCH_COMPLETE, 1509 WMI_TAG_EXTWOW_ENABLE_CMD, 1510 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1511 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1512 WMI_TAG_LPI_STATUS_EVENT, 1513 WMI_TAG_LPI_HANDOFF_EVENT, 1514 WMI_TAG_VDEV_RATE_STATS_EVENT, 1515 WMI_TAG_VDEV_RATE_HT_INFO, 1516 WMI_TAG_RIC_REQUEST, 1517 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1518 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1519 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1520 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1521 WMI_TAG_RIC_TSPEC, 1522 WMI_TAG_TPC_CHAINMASK_CONFIG, 1523 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1524 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1525 WMI_TAG_KEY_MATERIAL, 1526 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1527 WMI_TAG_SET_LED_FLASHING_CMD, 1528 WMI_TAG_MDNS_OFFLOAD_CMD, 1529 WMI_TAG_MDNS_SET_FQDN_CMD, 1530 WMI_TAG_MDNS_SET_RESP_CMD, 1531 WMI_TAG_MDNS_GET_STATS_CMD, 1532 WMI_TAG_MDNS_STATS_EVENT, 1533 WMI_TAG_ROAM_INVOKE_CMD, 1534 WMI_TAG_PDEV_RESUME_EVENT, 1535 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1536 WMI_TAG_SAP_OFL_ENABLE_CMD, 1537 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1538 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1539 WMI_TAG_APFIND_CMD_PARAM, 1540 WMI_TAG_APFIND_EVENT_HDR, 1541 WMI_TAG_OCB_SET_SCHED_CMD, 1542 WMI_TAG_OCB_SET_SCHED_EVENT, 1543 WMI_TAG_OCB_SET_CONFIG_CMD, 1544 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1545 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1546 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1547 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1548 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1549 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1550 WMI_TAG_DCC_GET_STATS_CMD, 1551 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1552 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1553 WMI_TAG_DCC_CLEAR_STATS_CMD, 1554 WMI_TAG_DCC_UPDATE_NDL_CMD, 1555 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1556 WMI_TAG_DCC_STATS_EVENT, 1557 WMI_TAG_OCB_CHANNEL, 1558 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1559 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1560 WMI_TAG_DCC_NDL_CHAN, 1561 WMI_TAG_QOS_PARAMETER, 1562 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1563 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1564 WMI_TAG_ROAM_FILTER, 1565 WMI_TAG_PASSPOINT_CONFIG_CMD, 1566 WMI_TAG_PASSPOINT_EVENT_HDR, 1567 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1568 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1569 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1570 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1571 WMI_TAG_GET_FW_MEM_DUMP, 1572 WMI_TAG_UPDATE_FW_MEM_DUMP, 1573 WMI_TAG_FW_MEM_DUMP_PARAMS, 1574 WMI_TAG_DEBUG_MESG_FLUSH, 1575 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1576 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1577 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1578 WMI_TAG_VDEV_SET_IE_CMD, 1579 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1580 WMI_TAG_RSSI_BREACH_EVENT, 1581 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1582 WMI_TAG_SOC_SET_PCL_CMD, 1583 WMI_TAG_SOC_SET_HW_MODE_CMD, 1584 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1585 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1586 WMI_TAG_VDEV_TXRX_STREAMS, 1587 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1588 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1589 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1590 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1591 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1592 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1593 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1594 WMI_TAG_PACKET_FILTER_CONFIG, 1595 WMI_TAG_PACKET_FILTER_ENABLE, 1596 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1597 WMI_TAG_MGMT_TX_SEND_CMD, 1598 WMI_TAG_MGMT_TX_COMPL_EVENT, 1599 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1600 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1601 WMI_TAG_LRO_INFO_CMD, 1602 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1603 WMI_TAG_SERVICE_READY_EXT_EVENT, 1604 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1605 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1606 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1607 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1608 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1609 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1610 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1611 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1612 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1613 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1614 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1615 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1616 WMI_TAG_SCPC_EVENT, 1617 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1618 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1619 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1620 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1621 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1622 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1623 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1624 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1625 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1626 WMI_TAG_PEER_DELETE_RESP_EVENT, 1627 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1628 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1629 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1630 WMI_TAG_VDEV_CONFIG_RATEMASK, 1631 WMI_TAG_PDEV_FIPS_CMD, 1632 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1633 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1634 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1635 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1636 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1637 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1638 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1639 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1640 WMI_TAG_FWTEST_SET_PARAM_CMD, 1641 WMI_TAG_PEER_ATF_REQUEST, 1642 WMI_TAG_VDEV_ATF_REQUEST, 1643 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1644 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1645 WMI_TAG_INST_RSSI_STATS_RESP, 1646 WMI_TAG_MED_UTIL_REPORT_EVENT, 1647 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1648 WMI_TAG_WDS_ADDR_EVENT, 1649 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1650 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1651 WMI_TAG_PDEV_TPC_EVENT, 1652 WMI_TAG_ANI_OFDM_EVENT, 1653 WMI_TAG_ANI_CCK_EVENT, 1654 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1655 WMI_TAG_PDEV_FIPS_EVENT, 1656 WMI_TAG_ATF_PEER_INFO, 1657 WMI_TAG_PDEV_GET_TPC_CMD, 1658 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1659 WMI_TAG_QBOOST_CFG_CMD, 1660 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1661 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1662 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1663 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1664 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1665 WMI_TAG_PEER_MCS_RATE_INFO, 1666 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1667 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1668 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1669 WMI_TAG_MU_REPORT_TOTAL_MU, 1670 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1671 WMI_TAG_ROAM_SET_MBO, 1672 WMI_TAG_MIB_STATS_ENABLE_CMD, 1673 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1674 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1675 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1676 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1677 WMI_TAG_NDI_GET_CAP_REQ, 1678 WMI_TAG_NDP_INITIATOR_REQ, 1679 WMI_TAG_NDP_RESPONDER_REQ, 1680 WMI_TAG_NDP_END_REQ, 1681 WMI_TAG_NDI_CAP_RSP_EVENT, 1682 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1683 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1684 WMI_TAG_NDP_END_RSP_EVENT, 1685 WMI_TAG_NDP_INDICATION_EVENT, 1686 WMI_TAG_NDP_CONFIRM_EVENT, 1687 WMI_TAG_NDP_END_INDICATION_EVENT, 1688 WMI_TAG_VDEV_SET_QUIET_CMD, 1689 WMI_TAG_PDEV_SET_PCL_CMD, 1690 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1691 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1692 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1693 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1694 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1695 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1696 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1697 WMI_TAG_COEX_CONFIG_CMD, 1698 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1699 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1700 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1701 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1702 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1703 WMI_TAG_MAC_PHY_CAPABILITIES, 1704 WMI_TAG_HW_MODE_CAPABILITIES, 1705 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1706 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1707 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1708 WMI_TAG_VDEV_WISA_CMD, 1709 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1710 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1711 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1712 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1713 WMI_TAG_NDP_END_RSP_PER_NDI, 1714 WMI_TAG_PEER_BWF_REQUEST, 1715 WMI_TAG_BWF_PEER_INFO, 1716 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1717 WMI_TAG_RMC_SET_LEADER_CMD, 1718 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1719 WMI_TAG_PER_CHAIN_RSSI_STATS, 1720 WMI_TAG_RSSI_STATS, 1721 WMI_TAG_P2P_LO_START_CMD, 1722 WMI_TAG_P2P_LO_STOP_CMD, 1723 WMI_TAG_P2P_LO_STOPPED_EVENT, 1724 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1725 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1726 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1727 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1728 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1729 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1730 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1731 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1732 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1733 WMI_TAG_TLV_BUF_LEN_PARAM, 1734 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1735 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1736 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1737 WMI_TAG_PEER_ANTDIV_INFO, 1738 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1739 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1740 WMI_TAG_MNT_FILTER_CMD, 1741 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1742 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1743 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1744 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1745 WMI_TAG_CHAN_CCA_STATS, 1746 WMI_TAG_PEER_SIGNAL_STATS, 1747 WMI_TAG_TX_STATS, 1748 WMI_TAG_PEER_AC_TX_STATS, 1749 WMI_TAG_RX_STATS, 1750 WMI_TAG_PEER_AC_RX_STATS, 1751 WMI_TAG_REPORT_STATS_EVENT, 1752 WMI_TAG_CHAN_CCA_STATS_THRESH, 1753 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1754 WMI_TAG_TX_STATS_THRESH, 1755 WMI_TAG_RX_STATS_THRESH, 1756 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1757 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1758 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1759 WMI_TAG_RX_AGGR_FAILURE_INFO, 1760 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1761 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1762 WMI_TAG_PDEV_BAND_TO_MAC, 1763 WMI_TAG_TBTT_OFFSET_INFO, 1764 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1765 WMI_TAG_SAR_LIMITS_CMD, 1766 WMI_TAG_SAR_LIMIT_CMD_ROW, 1767 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1768 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1769 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1770 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1771 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1772 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1773 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1774 WMI_TAG_VENDOR_OUI, 1775 WMI_TAG_REQUEST_RCPI_CMD, 1776 WMI_TAG_UPDATE_RCPI_EVENT, 1777 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1778 WMI_TAG_PEER_STATS_INFO, 1779 WMI_TAG_PEER_STATS_INFO_EVENT, 1780 WMI_TAG_PKGID_EVENT, 1781 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1782 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1783 WMI_TAG_REGULATORY_RULE_STRUCT, 1784 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1785 WMI_TAG_11D_SCAN_START_CMD, 1786 WMI_TAG_11D_SCAN_STOP_CMD, 1787 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1788 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1789 WMI_TAG_RADIO_CHAN_STATS, 1790 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1791 WMI_TAG_ROAM_PER_CONFIG, 1792 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1793 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1794 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1795 WMI_TAG_HW_DATA_FILTER_CMD, 1796 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1797 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1798 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1799 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1800 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1801 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1802 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1803 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1804 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1805 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1806 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1807 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1808 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1809 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1810 WMI_TAG_IFACE_OFFLOAD_STATS, 1811 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1812 WMI_TAG_RSSI_CTL_EXT, 1813 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1814 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1815 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1816 WMI_TAG_VDEV_TX_POWER_EVENT, 1817 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1818 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1819 WMI_TAG_TX_SEND_PARAMS, 1820 WMI_TAG_HE_RATE_SET, 1821 WMI_TAG_CONGESTION_STATS, 1822 WMI_TAG_SET_INIT_COUNTRY_CMD, 1823 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1824 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1825 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1826 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1827 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1828 WMI_TAG_THERM_THROT_STATS_EVENT, 1829 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1830 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1831 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1832 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1833 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1834 WMI_TAG_OEM_INDIRECT_DATA, 1835 WMI_TAG_OEM_DMA_BUF_RELEASE, 1836 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1837 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1838 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1839 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1840 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1841 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1842 WMI_TAG_UNIT_TEST_EVENT, 1843 WMI_TAG_ROAM_FILS_OFFLOAD, 1844 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1845 WMI_TAG_PMK_CACHE, 1846 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1847 WMI_TAG_ROAM_FILS_SYNCH, 1848 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1849 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1850 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1851 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1852 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1853 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1854 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1855 WMI_TAG_BTM_CONFIG, 1856 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1857 WMI_TAG_WLM_CONFIG_CMD, 1858 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1859 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1860 WMI_TAG_ROAM_CND_SCORING_PARAM, 1861 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1862 WMI_TAG_VENDOR_OUI_EXT, 1863 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1864 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1865 WMI_TAG_ENABLE_FILS_CMD, 1866 WMI_TAG_HOST_SWFDA_EVENT, 1867 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1868 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1869 WMI_TAG_STATS_PERIOD, 1870 WMI_TAG_NDL_SCHEDULE_UPDATE, 1871 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1872 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1873 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1874 WMI_TAG_SAR2_RESULT_EVENT, 1875 WMI_TAG_SAR_CAPABILITIES, 1876 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1877 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1878 WMI_TAG_DMA_RING_CAPABILITIES, 1879 WMI_TAG_DMA_RING_CFG_REQ, 1880 WMI_TAG_DMA_RING_CFG_RSP, 1881 WMI_TAG_DMA_BUF_RELEASE, 1882 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1883 WMI_TAG_SAR_GET_LIMITS_CMD, 1884 WMI_TAG_SAR_GET_LIMITS_EVENT, 1885 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1886 WMI_TAG_OFFLOAD_11K_REPORT, 1887 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1888 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1889 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1890 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1891 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1892 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1893 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1894 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1895 WMI_TAG_PDEV_GET_NFCAL_POWER, 1896 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1897 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1898 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1899 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1900 WMI_TAG_TWT_ENABLE_CMD, 1901 WMI_TAG_TWT_DISABLE_CMD, 1902 WMI_TAG_TWT_ADD_DIALOG_CMD, 1903 WMI_TAG_TWT_DEL_DIALOG_CMD, 1904 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1905 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1906 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1907 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1908 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1909 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1910 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1911 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1912 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1913 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1914 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1915 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1916 WMI_TAG_GET_TPC_POWER_CMD, 1917 WMI_TAG_GET_TPC_POWER_EVENT, 1918 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1919 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1920 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1921 WMI_TAG_MOTION_DET_START_STOP_CMD, 1922 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1923 WMI_TAG_MOTION_DET_EVENT, 1924 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1925 WMI_TAG_NDP_TRANSPORT_IP, 1926 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1927 WMI_TAG_ESP_ESTIMATE_EVENT, 1928 WMI_TAG_NAN_HOST_CONFIG, 1929 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1930 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1931 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1932 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1933 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1934 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1935 WMI_TAG_PEER_EXTD2_STATS, 1936 WMI_TAG_HPCS_PULSE_START_CMD, 1937 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1938 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1939 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1940 WMI_TAG_NAN_EVENT_INFO, 1941 WMI_TAG_NDP_CHANNEL_INFO, 1942 WMI_TAG_NDP_CMD, 1943 WMI_TAG_NDP_EVENT, 1944 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1945 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1946 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1947 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1948 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1949 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1950 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1951 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1952 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1953 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1954 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1955 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1956 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1957 WMI_TAG_MAX 1958 }; 1959 1960 enum wmi_tlv_service { 1961 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1962 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1963 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1964 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1965 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1966 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1967 WMI_TLV_SERVICE_AP_UAPSD = 6, 1968 WMI_TLV_SERVICE_AP_DFS = 7, 1969 WMI_TLV_SERVICE_11AC = 8, 1970 WMI_TLV_SERVICE_BLOCKACK = 9, 1971 WMI_TLV_SERVICE_PHYERR = 10, 1972 WMI_TLV_SERVICE_BCN_FILTER = 11, 1973 WMI_TLV_SERVICE_RTT = 12, 1974 WMI_TLV_SERVICE_WOW = 13, 1975 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1976 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1977 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1978 WMI_TLV_SERVICE_NLO = 17, 1979 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1980 WMI_TLV_SERVICE_SCAN_SCH = 19, 1981 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1982 WMI_TLV_SERVICE_CHATTER = 21, 1983 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1984 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1985 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1986 WMI_TLV_SERVICE_GPIO = 25, 1987 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1988 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1989 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1990 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1991 WMI_TLV_SERVICE_TX_ENCAP = 30, 1992 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1993 WMI_TLV_SERVICE_EARLY_RX = 32, 1994 WMI_TLV_SERVICE_STA_SMPS = 33, 1995 WMI_TLV_SERVICE_FWTEST = 34, 1996 WMI_TLV_SERVICE_STA_WMMAC = 35, 1997 WMI_TLV_SERVICE_TDLS = 36, 1998 WMI_TLV_SERVICE_BURST = 37, 1999 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 2000 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 2001 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 2002 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 2003 WMI_TLV_SERVICE_WLAN_HB = 42, 2004 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 2005 WMI_TLV_SERVICE_BATCH_SCAN = 44, 2006 WMI_TLV_SERVICE_QPOWER = 45, 2007 WMI_TLV_SERVICE_PLMREQ = 46, 2008 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 2009 WMI_TLV_SERVICE_RMC = 48, 2010 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 2011 WMI_TLV_SERVICE_COEX_SAR = 50, 2012 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 2013 WMI_TLV_SERVICE_NAN = 52, 2014 WMI_TLV_SERVICE_L1SS_STAT = 53, 2015 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 2016 WMI_TLV_SERVICE_OBSS_SCAN = 55, 2017 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 2018 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 2019 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 2020 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 2021 WMI_TLV_SERVICE_LPASS = 60, 2022 WMI_TLV_SERVICE_EXTSCAN = 61, 2023 WMI_TLV_SERVICE_D0WOW = 62, 2024 WMI_TLV_SERVICE_HSOFFLOAD = 63, 2025 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 2026 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 2027 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 2028 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 2029 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 2030 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 2031 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 2032 WMI_TLV_SERVICE_OCB = 71, 2033 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 2034 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 2035 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 2036 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 2037 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 2038 WMI_TLV_SERVICE_EXT_MSG = 77, 2039 WMI_TLV_SERVICE_MAWC = 78, 2040 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 2041 WMI_TLV_SERVICE_EGAP = 80, 2042 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 2043 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 2044 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 2045 WMI_TLV_SERVICE_ATF = 84, 2046 WMI_TLV_SERVICE_COEX_GPIO = 85, 2047 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 2048 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 2049 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 2050 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 2051 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 2052 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 2053 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 2054 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 2055 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 2056 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 2057 WMI_TLV_SERVICE_NAN_DATA = 96, 2058 WMI_TLV_SERVICE_NAN_RTT = 97, 2059 WMI_TLV_SERVICE_11AX = 98, 2060 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 2061 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 2062 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 2063 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 2064 WMI_TLV_SERVICE_MESH_11S = 103, 2065 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 2066 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 2067 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 2068 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 2069 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 2070 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 2071 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 2072 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 2073 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2074 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2075 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2076 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2077 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2078 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2079 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2080 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2081 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2082 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2083 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2084 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2085 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2086 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2087 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2088 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2089 2090 /* The first 128 bits */ 2091 WMI_MAX_SERVICE = 128, 2092 2093 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2094 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2095 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2096 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2097 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2098 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2099 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2100 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2101 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2102 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2103 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2104 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2105 WMI_TLV_SERVICE_THERM_THROT = 140, 2106 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2107 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2108 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2109 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2110 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2111 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2112 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2113 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2114 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2115 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2116 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2117 WMI_TLV_SERVICE_STA_TWT = 152, 2118 WMI_TLV_SERVICE_AP_TWT = 153, 2119 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2120 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2121 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2122 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2123 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2124 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2125 WMI_TLV_SERVICE_MOTION_DET = 160, 2126 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2127 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2128 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2129 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2130 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2131 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2132 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2133 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2134 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2135 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2136 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2137 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2138 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2139 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2140 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2141 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2142 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2143 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2144 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2145 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2146 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2147 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2148 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2149 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2150 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2151 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2152 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2153 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2154 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2155 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2156 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2157 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2158 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2159 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2160 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2161 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2162 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2163 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2164 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2165 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2166 WMI_TLV_SERVICE_PS_TDCC = 201, 2167 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2168 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2169 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2170 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2171 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2172 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2173 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2174 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2175 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2176 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2177 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2178 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2179 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2180 WMI_TLV_SERVICE_EXT2_MSG = 220, 2181 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2182 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2183 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2184 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, 2185 2186 /* The second 128 bits */ 2187 WMI_MAX_EXT_SERVICE = 256, 2188 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, 2189 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2190 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2191 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, 2192 WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, 2193 2194 /* The third 128 bits */ 2195 WMI_MAX_EXT2_SERVICE = 384 2196 }; 2197 2198 enum { 2199 WMI_SMPS_FORCED_MODE_NONE = 0, 2200 WMI_SMPS_FORCED_MODE_DISABLED, 2201 WMI_SMPS_FORCED_MODE_STATIC, 2202 WMI_SMPS_FORCED_MODE_DYNAMIC 2203 }; 2204 2205 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2206 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2207 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2208 2209 #define WMI_PEER_MIMO_PS_STATE 0x1 2210 #define WMI_PEER_AMPDU 0x2 2211 #define WMI_PEER_AUTHORIZE 0x3 2212 #define WMI_PEER_CHWIDTH 0x4 2213 #define WMI_PEER_NSS 0x5 2214 #define WMI_PEER_USE_4ADDR 0x6 2215 #define WMI_PEER_MEMBERSHIP 0x7 2216 #define WMI_PEER_USERPOS 0x8 2217 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2218 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2219 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2220 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2221 #define WMI_PEER_PHYMODE 0xD 2222 #define WMI_PEER_USE_FIXED_PWR 0xE 2223 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2224 #define WMI_PEER_SET_MU_WHITELIST 0x10 2225 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2226 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2227 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2228 2229 /* slot time long */ 2230 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2231 /* slot time short */ 2232 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2233 /* preamble long */ 2234 #define WMI_VDEV_PREAMBLE_LONG 0x1 2235 /* preamble short */ 2236 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2237 2238 enum wmi_peer_smps_state { 2239 WMI_PEER_SMPS_PS_NONE = 0x0, 2240 WMI_PEER_SMPS_STATIC = 0x1, 2241 WMI_PEER_SMPS_DYNAMIC = 0x2 2242 }; 2243 2244 enum wmi_peer_chwidth { 2245 WMI_PEER_CHWIDTH_20MHZ = 0, 2246 WMI_PEER_CHWIDTH_40MHZ = 1, 2247 WMI_PEER_CHWIDTH_80MHZ = 2, 2248 WMI_PEER_CHWIDTH_160MHZ = 3, 2249 }; 2250 2251 enum wmi_beacon_gen_mode { 2252 WMI_BEACON_STAGGERED_MODE = 0, 2253 WMI_BEACON_BURST_MODE = 1 2254 }; 2255 2256 enum wmi_direct_buffer_module { 2257 WMI_DIRECT_BUF_SPECTRAL = 0, 2258 WMI_DIRECT_BUF_CFR = 1, 2259 2260 /* keep it last */ 2261 WMI_DIRECT_BUF_MAX 2262 }; 2263 2264 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2265 * event 2266 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2267 * of 80MHz 2268 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2269 * of 80MHz 2270 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2271 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2272 * nss of 80MHz 2273 */ 2274 2275 enum wmi_nss_ratio { 2276 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2277 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2278 WMI_NSS_RATIO_1_NSS = 0x2, 2279 WMI_NSS_RATIO_2_NSS = 0x3, 2280 }; 2281 2282 enum wmi_dtim_policy { 2283 WMI_DTIM_POLICY_IGNORE = 1, 2284 WMI_DTIM_POLICY_NORMAL = 2, 2285 WMI_DTIM_POLICY_STICK = 3, 2286 WMI_DTIM_POLICY_AUTO = 4, 2287 }; 2288 2289 struct wmi_host_pdev_band_to_mac { 2290 uint32_t pdev_id; 2291 uint32_t start_freq; 2292 uint32_t end_freq; 2293 }; 2294 2295 struct ath12k_ppe_threshold { 2296 uint32_t numss_m1; 2297 uint32_t ru_bit_mask; 2298 uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2299 }; 2300 2301 struct ath12k_service_ext_param { 2302 uint32_t default_conc_scan_config_bits; 2303 uint32_t default_fw_config_bits; 2304 struct ath12k_ppe_threshold ppet; 2305 uint32_t he_cap_info; 2306 uint32_t mpdu_density; 2307 uint32_t max_bssid_rx_filters; 2308 uint32_t num_hw_modes; 2309 uint32_t num_phy; 2310 }; 2311 2312 struct ath12k_hw_mode_caps { 2313 uint32_t hw_mode_id; 2314 uint32_t phy_id_map; 2315 uint32_t hw_mode_config_type; 2316 }; 2317 2318 #define PSOC_HOST_MAX_PHY_SIZE (3) 2319 #define ATH12K_11B_SUPPORT BIT(0) 2320 #define ATH12K_11G_SUPPORT BIT(1) 2321 #define ATH12K_11A_SUPPORT BIT(2) 2322 #define ATH12K_11N_SUPPORT BIT(3) 2323 #define ATH12K_11AC_SUPPORT BIT(4) 2324 #define ATH12K_11AX_SUPPORT BIT(5) 2325 2326 struct ath12k_hal_reg_capabilities_ext { 2327 uint32_t phy_id; 2328 uint32_t eeprom_reg_domain; 2329 uint32_t eeprom_reg_domain_ext; 2330 uint32_t regcap1; 2331 uint32_t regcap2; 2332 uint32_t wireless_modes; 2333 uint32_t low_2ghz_chan; 2334 uint32_t high_2ghz_chan; 2335 uint32_t low_5ghz_chan; 2336 uint32_t high_5ghz_chan; 2337 }; 2338 2339 #define WMI_HOST_MAX_PDEV 3 2340 2341 struct wlan_host_mem_chunk { 2342 uint32_t tlv_header; 2343 uint32_t req_id; 2344 uint32_t ptr; 2345 uint32_t size; 2346 } __packed; 2347 2348 struct wmi_host_mem_chunk { 2349 void *vaddr; 2350 bus_addr_t paddr; 2351 uint32_t len; 2352 uint32_t req_id; 2353 }; 2354 2355 enum peer_metadata_version { 2356 ATH12K_PEER_METADATA_V0, 2357 ATH12K_PEER_METADATA_V1, 2358 ATH12K_PEER_METADATA_V1A, 2359 ATH12K_PEER_METADATA_V1B, 2360 }; 2361 2362 struct wmi_resource_config_arg { 2363 uint32_t num_vdevs; 2364 uint32_t num_peers; 2365 uint32_t num_active_peers; 2366 uint32_t num_offload_peers; 2367 uint32_t num_offload_reorder_buffs; 2368 uint32_t num_peer_keys; 2369 uint32_t num_tids; 2370 uint32_t ast_skid_limit; 2371 uint32_t tx_chain_mask; 2372 uint32_t rx_chain_mask; 2373 uint32_t rx_timeout_pri[4]; 2374 uint32_t rx_decap_mode; 2375 uint32_t scan_max_pending_req; 2376 uint32_t bmiss_offload_max_vdev; 2377 uint32_t roam_offload_max_vdev; 2378 uint32_t roam_offload_max_ap_profiles; 2379 uint32_t num_mcast_groups; 2380 uint32_t num_mcast_table_elems; 2381 uint32_t mcast2ucast_mode; 2382 uint32_t tx_dbg_log_size; 2383 uint32_t num_wds_entries; 2384 uint32_t dma_burst_size; 2385 uint32_t mac_aggr_delim; 2386 uint32_t rx_skip_defrag_timeout_dup_detection_check; 2387 uint32_t vow_config; 2388 uint32_t gtk_offload_max_vdev; 2389 uint32_t num_msdu_desc; 2390 uint32_t max_frag_entries; 2391 uint32_t max_peer_ext_stats; 2392 uint32_t smart_ant_cap; 2393 uint32_t bk_minfree; 2394 uint32_t be_minfree; 2395 uint32_t vi_minfree; 2396 uint32_t vo_minfree; 2397 uint32_t rx_batchmode; 2398 uint32_t tt_support; 2399 uint32_t atf_config; 2400 uint32_t iphdr_pad_config; 2401 uint32_t qwrap_config:16, 2402 alloc_frag_desc_for_data_pkt:16; 2403 uint32_t num_tdls_vdevs; 2404 uint32_t num_tdls_conn_table_entries; 2405 uint32_t beacon_tx_offload_max_vdev; 2406 uint32_t num_multicast_filter_entries; 2407 uint32_t num_wow_filters; 2408 uint32_t num_keep_alive_pattern; 2409 uint32_t keep_alive_pattern_size; 2410 uint32_t max_tdls_concurrent_sleep_sta; 2411 uint32_t max_tdls_concurrent_buffer_sta; 2412 uint32_t wmi_send_separate; 2413 uint32_t num_ocb_vdevs; 2414 uint32_t num_ocb_channels; 2415 uint32_t num_ocb_schedules; 2416 uint32_t num_ns_ext_tuples_cfg; 2417 uint32_t bpf_instruction_size; 2418 uint32_t max_bssid_rx_filters; 2419 uint32_t use_pdev_id; 2420 uint32_t peer_map_unmap_version; 2421 uint32_t sched_params; 2422 uint32_t twt_ap_pdev_count; 2423 uint32_t twt_ap_sta_count; 2424 enum peer_metadata_version peer_metadata_ver; 2425 uint32_t ema_max_vap_cnt; 2426 uint32_t ema_max_profile_period; 2427 bool is_reg_cc_ext_event_supported; 2428 } __packed; 2429 2430 struct wmi_init_cmd_arg { 2431 struct wmi_resource_config_arg res_cfg; 2432 uint8_t num_mem_chunks; 2433 struct wmi_host_mem_chunk *mem_chunks; 2434 uint32_t hw_mode_id; 2435 uint32_t num_band_to_mac; 2436 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2437 }; 2438 2439 struct wmi_pdev_band_to_mac { 2440 uint32_t tlv_header; 2441 uint32_t pdev_id; 2442 uint32_t start_freq; 2443 uint32_t end_freq; 2444 } __packed; 2445 2446 struct wmi_pdev_set_hw_mode_cmd_param { 2447 uint32_t tlv_header; 2448 uint32_t pdev_id; 2449 uint32_t hw_mode_index; 2450 uint32_t num_band_to_mac; 2451 } __packed; 2452 2453 struct wmi_ppe_threshold { 2454 uint32_t numss_m1; /** NSS - 1*/ 2455 union { 2456 uint32_t ru_count; 2457 uint32_t ru_mask; 2458 } __packed; 2459 uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2460 } __packed; 2461 2462 #define HW_BD_INFO_SIZE 5 2463 2464 struct wmi_abi_version { 2465 uint32_t abi_version_0; 2466 uint32_t abi_version_1; 2467 uint32_t abi_version_ns_0; 2468 uint32_t abi_version_ns_1; 2469 uint32_t abi_version_ns_2; 2470 uint32_t abi_version_ns_3; 2471 } __packed; 2472 2473 struct wmi_init_cmd { 2474 uint32_t tlv_header; 2475 struct wmi_abi_version host_abi_vers; 2476 uint32_t num_host_mem_chunks; 2477 } __packed; 2478 2479 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2480 #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2481 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2482 2483 #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 2484 2485 struct wmi_resource_config { 2486 uint32_t tlv_header; 2487 uint32_t num_vdevs; 2488 uint32_t num_peers; 2489 uint32_t num_offload_peers; 2490 uint32_t num_offload_reorder_buffs; 2491 uint32_t num_peer_keys; 2492 uint32_t num_tids; 2493 uint32_t ast_skid_limit; 2494 uint32_t tx_chain_mask; 2495 uint32_t rx_chain_mask; 2496 uint32_t rx_timeout_pri[4]; 2497 uint32_t rx_decap_mode; 2498 uint32_t scan_max_pending_req; 2499 uint32_t bmiss_offload_max_vdev; 2500 uint32_t roam_offload_max_vdev; 2501 uint32_t roam_offload_max_ap_profiles; 2502 uint32_t num_mcast_groups; 2503 uint32_t num_mcast_table_elems; 2504 uint32_t mcast2ucast_mode; 2505 uint32_t tx_dbg_log_size; 2506 uint32_t num_wds_entries; 2507 uint32_t dma_burst_size; 2508 uint32_t mac_aggr_delim; 2509 uint32_t rx_skip_defrag_timeout_dup_detection_check; 2510 uint32_t vow_config; 2511 uint32_t gtk_offload_max_vdev; 2512 uint32_t num_msdu_desc; 2513 uint32_t max_frag_entries; 2514 uint32_t num_tdls_vdevs; 2515 uint32_t num_tdls_conn_table_entries; 2516 uint32_t beacon_tx_offload_max_vdev; 2517 uint32_t num_multicast_filter_entries; 2518 uint32_t num_wow_filters; 2519 uint32_t num_keep_alive_pattern; 2520 uint32_t keep_alive_pattern_size; 2521 uint32_t max_tdls_concurrent_sleep_sta; 2522 uint32_t max_tdls_concurrent_buffer_sta; 2523 uint32_t wmi_send_separate; 2524 uint32_t num_ocb_vdevs; 2525 uint32_t num_ocb_channels; 2526 uint32_t num_ocb_schedules; 2527 uint32_t flag1; 2528 uint32_t smart_ant_cap; 2529 uint32_t bk_minfree; 2530 uint32_t be_minfree; 2531 uint32_t vi_minfree; 2532 uint32_t vo_minfree; 2533 uint32_t alloc_frag_desc_for_data_pkt; 2534 uint32_t num_ns_ext_tuples_cfg; 2535 uint32_t bpf_instruction_size; 2536 uint32_t max_bssid_rx_filters; 2537 uint32_t use_pdev_id; 2538 uint32_t max_num_dbs_scan_duty_cycle; 2539 uint32_t max_num_group_keys; 2540 uint32_t peer_map_unmap_version; 2541 uint32_t sched_params; 2542 uint32_t twt_ap_pdev_count; 2543 uint32_t twt_ap_sta_count; 2544 #ifdef notyet /* 6 GHz support */ 2545 uint32_t max_nlo_ssids; 2546 uint32_t num_pkt_filters; 2547 uint32_t num_max_sta_vdevs; 2548 uint32_t max_bssid_indicator; 2549 uint32_t ul_resp_config; 2550 uint32_t msdu_flow_override_config0; 2551 uint32_t msdu_flow_override_config1; 2552 uint32_t flags2; 2553 uint32_t host_service_flags; 2554 uint32_t max_rnr_neighbours; 2555 uint32_t ema_max_vap_cnt; 2556 uint32_t ema_max_profile_period; 2557 #endif 2558 } __packed; 2559 2560 struct wmi_service_ready_event { 2561 uint32_t fw_build_vers; 2562 struct wmi_abi_version fw_abi_vers; 2563 uint32_t phy_capability; 2564 uint32_t max_frag_entry; 2565 uint32_t num_rf_chains; 2566 uint32_t ht_cap_info; 2567 uint32_t vht_cap_info; 2568 uint32_t vht_supp_mcs; 2569 uint32_t hw_min_tx_power; 2570 uint32_t hw_max_tx_power; 2571 uint32_t sys_cap_info; 2572 uint32_t min_pkt_size_enable; 2573 uint32_t max_bcn_ie_size; 2574 uint32_t num_mem_reqs; 2575 uint32_t max_num_scan_channels; 2576 uint32_t hw_bd_id; 2577 uint32_t hw_bd_info[HW_BD_INFO_SIZE]; 2578 uint32_t max_supported_macs; 2579 uint32_t wmi_fw_sub_feat_caps; 2580 uint32_t num_dbs_hw_modes; 2581 /* txrx_chainmask 2582 * [7:0] - 2G band tx chain mask 2583 * [15:8] - 2G band rx chain mask 2584 * [23:16] - 5G band tx chain mask 2585 * [31:24] - 5G band rx chain mask 2586 */ 2587 uint32_t txrx_chainmask; 2588 uint32_t default_dbs_hw_mode_index; 2589 uint32_t num_msdu_desc; 2590 } __packed; 2591 2592 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t)) 2593 2594 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x uint32_t = 128 bits */ 2595 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t)) 2596 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2597 #define WMI_SERVICE_BITS_IN_SIZE32 4 2598 2599 struct wmi_service_ready_ext_event { 2600 uint32_t default_conc_scan_config_bits; 2601 uint32_t default_fw_config_bits; 2602 struct wmi_ppe_threshold ppet; 2603 uint32_t he_cap_info; 2604 uint32_t mpdu_density; 2605 uint32_t max_bssid_rx_filters; 2606 uint32_t fw_build_vers_ext; 2607 uint32_t max_nlo_ssids; 2608 uint32_t max_bssid_indicator; 2609 uint32_t he_cap_info_ext; 2610 } __packed; 2611 2612 struct wmi_soc_mac_phy_hw_mode_caps { 2613 uint32_t num_hw_modes; 2614 uint32_t num_chainmask_tables; 2615 } __packed; 2616 2617 struct wmi_hw_mode_capabilities { 2618 uint32_t tlv_header; 2619 uint32_t hw_mode_id; 2620 uint32_t phy_id_map; 2621 uint32_t hw_mode_config_type; 2622 } __packed; 2623 2624 #define WMI_MAX_HECAP_PHY_SIZE (3) 2625 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2626 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2627 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2628 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2629 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2630 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2631 2632 struct wmi_mac_phy_capabilities { 2633 uint32_t hw_mode_id; 2634 uint32_t pdev_id; 2635 uint32_t phy_id; 2636 uint32_t supported_flags; 2637 uint32_t supported_bands; 2638 uint32_t ampdu_density; 2639 uint32_t max_bw_supported_2g; 2640 uint32_t ht_cap_info_2g; 2641 uint32_t vht_cap_info_2g; 2642 uint32_t vht_supp_mcs_2g; 2643 uint32_t he_cap_info_2g; 2644 uint32_t he_supp_mcs_2g; 2645 uint32_t tx_chain_mask_2g; 2646 uint32_t rx_chain_mask_2g; 2647 uint32_t max_bw_supported_5g; 2648 uint32_t ht_cap_info_5g; 2649 uint32_t vht_cap_info_5g; 2650 uint32_t vht_supp_mcs_5g; 2651 uint32_t he_cap_info_5g; 2652 uint32_t he_supp_mcs_5g; 2653 uint32_t tx_chain_mask_5g; 2654 uint32_t rx_chain_mask_5g; 2655 uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2656 uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2657 struct wmi_ppe_threshold he_ppet2g; 2658 struct wmi_ppe_threshold he_ppet5g; 2659 uint32_t chainmask_table_id; 2660 uint32_t lmac_id; 2661 uint32_t he_cap_info_2g_ext; 2662 uint32_t he_cap_info_5g_ext; 2663 uint32_t he_cap_info_internal; 2664 uint32_t wireless_modes; 2665 uint32_t low_2ghz_chan_freq; 2666 uint32_t high_2ghz_chan_freq; 2667 uint32_t low_5ghz_chan_freq; 2668 uint32_t high_5ghz_chan_freq; 2669 uint32_t nss_ratio; 2670 } __packed; 2671 2672 struct wmi_hal_reg_capabilities_ext { 2673 uint32_t tlv_header; 2674 uint32_t phy_id; 2675 uint32_t eeprom_reg_domain; 2676 uint32_t eeprom_reg_domain_ext; 2677 uint32_t regcap1; 2678 uint32_t regcap2; 2679 uint32_t wireless_modes; 2680 uint32_t low_2ghz_chan; 2681 uint32_t high_2ghz_chan; 2682 uint32_t low_5ghz_chan; 2683 uint32_t high_5ghz_chan; 2684 } __packed; 2685 2686 struct wmi_soc_hal_reg_capabilities { 2687 uint32_t num_phy; 2688 } __packed; 2689 2690 /* 2 word representation of MAC addr */ 2691 struct wmi_mac_addr { 2692 union { 2693 uint8_t addr[6]; 2694 struct { 2695 uint32_t word0; 2696 uint32_t word1; 2697 } __packed; 2698 } __packed; 2699 } __packed; 2700 2701 struct wmi_dma_ring_capabilities { 2702 uint32_t tlv_header; 2703 uint32_t pdev_id; 2704 uint32_t module_id; 2705 uint32_t min_elem; 2706 uint32_t min_buf_sz; 2707 uint32_t min_buf_align; 2708 } __packed; 2709 2710 struct wmi_ready_event_min { 2711 struct wmi_abi_version fw_abi_vers; 2712 struct wmi_mac_addr mac_addr; 2713 uint32_t status; 2714 uint32_t num_dscp_table; 2715 uint32_t num_extra_mac_addr; 2716 uint32_t num_total_peers; 2717 uint32_t num_extra_peers; 2718 } __packed; 2719 2720 struct wmi_ready_event { 2721 struct wmi_ready_event_min ready_event_min; 2722 uint32_t max_ast_index; 2723 uint32_t pktlog_defs_checksum; 2724 } __packed; 2725 2726 struct wmi_service_available_event { 2727 uint32_t wmi_service_segment_offset; 2728 uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2729 } __packed; 2730 2731 struct vdev_create_params { 2732 uint8_t if_id; 2733 uint32_t type; 2734 uint32_t subtype; 2735 struct { 2736 uint8_t tx; 2737 uint8_t rx; 2738 } chains[2]; 2739 uint32_t pdev_id; 2740 uint32_t mbssid_flags; 2741 uint32_t mbssid_tx_vdev_id; 2742 }; 2743 2744 struct wmi_vdev_create_cmd { 2745 uint32_t tlv_header; 2746 uint32_t vdev_id; 2747 uint32_t vdev_type; 2748 uint32_t vdev_subtype; 2749 struct wmi_mac_addr vdev_macaddr; 2750 uint32_t num_cfg_txrx_streams; 2751 uint32_t pdev_id; 2752 uint32_t mbssid_flags; 2753 uint32_t mbssid_tx_vdev_id; 2754 } __packed; 2755 2756 struct wmi_vdev_txrx_streams { 2757 uint32_t tlv_header; 2758 uint32_t band; 2759 uint32_t supported_tx_streams; 2760 uint32_t supported_rx_streams; 2761 } __packed; 2762 2763 struct wmi_vdev_delete_cmd { 2764 uint32_t tlv_header; 2765 uint32_t vdev_id; 2766 } __packed; 2767 2768 struct wmi_vdev_up_cmd { 2769 uint32_t tlv_header; 2770 uint32_t vdev_id; 2771 uint32_t vdev_assoc_id; 2772 struct wmi_mac_addr vdev_bssid; 2773 struct wmi_mac_addr tx_vdev_bssid; 2774 uint32_t nontx_profile_idx; 2775 uint32_t nontx_profile_cnt; 2776 } __packed; 2777 2778 struct wmi_vdev_stop_cmd { 2779 uint32_t tlv_header; 2780 uint32_t vdev_id; 2781 } __packed; 2782 2783 struct wmi_vdev_down_cmd { 2784 uint32_t tlv_header; 2785 uint32_t vdev_id; 2786 } __packed; 2787 2788 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2789 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2790 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2791 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2792 2793 struct wmi_ssid { 2794 uint32_t ssid_len; 2795 uint32_t ssid[8]; 2796 } __packed; 2797 2798 #define ATH12K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2799 2800 struct wmi_vdev_start_request_cmd { 2801 uint32_t tlv_header; 2802 uint32_t vdev_id; 2803 uint32_t requestor_id; 2804 uint32_t beacon_interval; 2805 uint32_t dtim_period; 2806 uint32_t flags; 2807 struct wmi_ssid ssid; 2808 uint32_t bcn_tx_rate; 2809 uint32_t bcn_txpower; 2810 uint32_t num_noa_descriptors; 2811 uint32_t disable_hw_ack; 2812 uint32_t preferred_tx_streams; 2813 uint32_t preferred_rx_streams; 2814 uint32_t he_ops; 2815 uint32_t cac_duration_ms; 2816 uint32_t regdomain; 2817 uint32_t min_data_rate; 2818 uint32_t mbssid_flags; 2819 uint32_t mbssid_tx_vdev_id; 2820 } __packed; 2821 2822 #define MGMT_TX_DL_FRM_LEN 64 2823 #define WMI_MAC_MAX_SSID_LENGTH 32 2824 struct mac_ssid { 2825 uint8_t length; 2826 uint8_t mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2827 } __packed; 2828 2829 struct wmi_p2p_noa_descriptor { 2830 uint32_t type_count; 2831 uint32_t duration; 2832 uint32_t interval; 2833 uint32_t start_time; 2834 }; 2835 2836 struct channel_param { 2837 uint8_t chan_id; 2838 uint8_t pwr; 2839 uint32_t mhz; 2840 uint32_t half_rate:1, 2841 quarter_rate:1, 2842 dfs_set:1, 2843 dfs_set_cfreq2:1, 2844 is_chan_passive:1, 2845 allow_ht:1, 2846 allow_vht:1, 2847 allow_he:1, 2848 set_agile:1, 2849 psc_channel:1; 2850 uint32_t phy_mode; 2851 uint32_t cfreq1; 2852 uint32_t cfreq2; 2853 char maxpower; 2854 char minpower; 2855 char maxregpower; 2856 uint8_t antennamax; 2857 uint8_t reg_class_id; 2858 } __packed; 2859 2860 enum wmi_phy_mode { 2861 MODE_11A = 0, 2862 MODE_11G = 1, /* 11b/g Mode */ 2863 MODE_11B = 2, /* 11b Mode */ 2864 MODE_11GONLY = 3, /* 11g only Mode */ 2865 MODE_11NA_HT20 = 4, 2866 MODE_11NG_HT20 = 5, 2867 MODE_11NA_HT40 = 6, 2868 MODE_11NG_HT40 = 7, 2869 MODE_11AC_VHT20 = 8, 2870 MODE_11AC_VHT40 = 9, 2871 MODE_11AC_VHT80 = 10, 2872 MODE_11AC_VHT20_2G = 11, 2873 MODE_11AC_VHT40_2G = 12, 2874 MODE_11AC_VHT80_2G = 13, 2875 MODE_11AC_VHT80_80 = 14, 2876 MODE_11AC_VHT160 = 15, 2877 MODE_11AX_HE20 = 16, 2878 MODE_11AX_HE40 = 17, 2879 MODE_11AX_HE80 = 18, 2880 MODE_11AX_HE80_80 = 19, 2881 MODE_11AX_HE160 = 20, 2882 MODE_11AX_HE20_2G = 21, 2883 MODE_11AX_HE40_2G = 22, 2884 MODE_11AX_HE80_2G = 23, 2885 MODE_UNKNOWN = 24, 2886 MODE_MAX = 24 2887 }; 2888 2889 static inline const char *qwz_wmi_phymode_str(enum wmi_phy_mode mode) 2890 { 2891 switch (mode) { 2892 case MODE_11A: 2893 return "11a"; 2894 case MODE_11G: 2895 return "11g"; 2896 case MODE_11B: 2897 return "11b"; 2898 case MODE_11GONLY: 2899 return "11gonly"; 2900 case MODE_11NA_HT20: 2901 return "11na-ht20"; 2902 case MODE_11NG_HT20: 2903 return "11ng-ht20"; 2904 case MODE_11NA_HT40: 2905 return "11na-ht40"; 2906 case MODE_11NG_HT40: 2907 return "11ng-ht40"; 2908 case MODE_11AC_VHT20: 2909 return "11ac-vht20"; 2910 case MODE_11AC_VHT40: 2911 return "11ac-vht40"; 2912 case MODE_11AC_VHT80: 2913 return "11ac-vht80"; 2914 case MODE_11AC_VHT160: 2915 return "11ac-vht160"; 2916 case MODE_11AC_VHT80_80: 2917 return "11ac-vht80+80"; 2918 case MODE_11AC_VHT20_2G: 2919 return "11ac-vht20-2g"; 2920 case MODE_11AC_VHT40_2G: 2921 return "11ac-vht40-2g"; 2922 case MODE_11AC_VHT80_2G: 2923 return "11ac-vht80-2g"; 2924 case MODE_11AX_HE20: 2925 return "11ax-he20"; 2926 case MODE_11AX_HE40: 2927 return "11ax-he40"; 2928 case MODE_11AX_HE80: 2929 return "11ax-he80"; 2930 case MODE_11AX_HE80_80: 2931 return "11ax-he80+80"; 2932 case MODE_11AX_HE160: 2933 return "11ax-he160"; 2934 case MODE_11AX_HE20_2G: 2935 return "11ax-he20-2g"; 2936 case MODE_11AX_HE40_2G: 2937 return "11ax-he40-2g"; 2938 case MODE_11AX_HE80_2G: 2939 return "11ax-he80-2g"; 2940 case MODE_UNKNOWN: 2941 /* skip */ 2942 break; 2943 2944 /* no default handler to allow compiler to check that the 2945 * enum is fully handled 2946 */ 2947 } 2948 2949 return "<unknown>"; 2950 } 2951 2952 struct wmi_channel_arg { 2953 uint32_t freq; 2954 uint32_t band_center_freq1; 2955 uint32_t band_center_freq2; 2956 bool passive; 2957 bool allow_ibss; 2958 bool allow_ht; 2959 bool allow_vht; 2960 bool ht40plus; 2961 bool chan_radar; 2962 bool freq2_radar; 2963 bool allow_he; 2964 uint32_t min_power; 2965 uint32_t max_power; 2966 uint32_t max_reg_power; 2967 uint32_t max_antenna_gain; 2968 enum wmi_phy_mode mode; 2969 }; 2970 2971 struct wmi_vdev_start_req_arg { 2972 uint32_t vdev_id; 2973 struct wmi_channel_arg channel; 2974 uint32_t bcn_intval; 2975 uint32_t dtim_period; 2976 uint8_t *ssid; 2977 uint32_t ssid_len; 2978 uint32_t bcn_tx_rate; 2979 uint32_t bcn_tx_power; 2980 bool disable_hw_ack; 2981 bool hidden_ssid; 2982 bool pmf_enabled; 2983 uint32_t he_ops; 2984 uint32_t cac_duration_ms; 2985 uint32_t regdomain; 2986 uint32_t pref_rx_streams; 2987 uint32_t pref_tx_streams; 2988 uint32_t num_noa_descriptors; 2989 uint32_t min_data_rate; 2990 uint32_t mbssid_flags; 2991 uint32_t mbssid_tx_vdev_id; 2992 }; 2993 2994 struct peer_create_params { 2995 uint8_t *peer_addr; 2996 uint32_t peer_type; 2997 uint32_t vdev_id; 2998 }; 2999 3000 struct peer_delete_params { 3001 uint8_t vdev_id; 3002 }; 3003 3004 struct peer_flush_params { 3005 uint32_t peer_tid_bitmap; 3006 uint8_t vdev_id; 3007 }; 3008 3009 struct pdev_set_regdomain_params { 3010 uint16_t current_rd_in_use; 3011 uint16_t current_rd_2g; 3012 uint16_t current_rd_5g; 3013 uint32_t ctl_2g; 3014 uint32_t ctl_5g; 3015 uint8_t dfs_domain; 3016 uint32_t pdev_id; 3017 }; 3018 3019 struct rx_reorder_queue_remove_params { 3020 uint8_t *peer_macaddr; 3021 uint16_t vdev_id; 3022 uint32_t peer_tid_bitmap; 3023 }; 3024 3025 #define WMI_HOST_PDEV_ID_SOC 0xFF 3026 #define WMI_HOST_PDEV_ID_0 0 3027 #define WMI_HOST_PDEV_ID_1 1 3028 #define WMI_HOST_PDEV_ID_2 2 3029 3030 #define WMI_PDEV_ID_SOC 0 3031 #define WMI_PDEV_ID_1ST 1 3032 #define WMI_PDEV_ID_2ND 2 3033 #define WMI_PDEV_ID_3RD 3 3034 3035 /* Freq units in MHz */ 3036 #define REG_RULE_START_FREQ 0x0000ffff 3037 #define REG_RULE_END_FREQ 0xffff0000 3038 #define REG_RULE_FLAGS 0x0000ffff 3039 #define REG_RULE_MAX_BW 0x0000ffff 3040 #define REG_RULE_REG_PWR 0x00ff0000 3041 #define REG_RULE_ANT_GAIN 0xff000000 3042 #define REG_RULE_PSD_INFO BIT(0) 3043 #define REG_RULE_PSD_EIRP 0xff0000 3044 3045 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 3046 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 3047 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 3048 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 3049 3050 #define HE_PHYCAP_BYTE_0 0 3051 #define HE_PHYCAP_BYTE_1 1 3052 #define HE_PHYCAP_BYTE_2 2 3053 #define HE_PHYCAP_BYTE_3 3 3054 #define HE_PHYCAP_BYTE_4 4 3055 3056 #define HECAP_PHY_SU_BFER BIT(7) 3057 #define HECAP_PHY_SU_BFEE BIT(0) 3058 #define HECAP_PHY_MU_BFER BIT(1) 3059 #define HECAP_PHY_UL_MUMIMO BIT(6) 3060 #define HECAP_PHY_UL_MUOFDMA BIT(7) 3061 3062 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 3063 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) 3064 3065 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 3066 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) 3067 3068 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 3069 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) 3070 3071 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 3072 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) 3073 3074 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 3075 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) 3076 3077 #define HE_MODE_SU_TX_BFEE BIT(0) 3078 #define HE_MODE_SU_TX_BFER BIT(1) 3079 #define HE_MODE_MU_TX_BFEE BIT(2) 3080 #define HE_MODE_MU_TX_BFER BIT(3) 3081 #define HE_MODE_DL_OFDMA BIT(4) 3082 #define HE_MODE_UL_OFDMA BIT(5) 3083 #define HE_MODE_UL_MUMIMO BIT(6) 3084 3085 #define HE_DL_MUOFDMA_ENABLE 1 3086 #define HE_UL_MUOFDMA_ENABLE 1 3087 #define HE_DL_MUMIMO_ENABLE 1 3088 #define HE_UL_MUMIMO_ENABLE 1 3089 #define HE_MU_BFEE_ENABLE 1 3090 #define HE_SU_BFEE_ENABLE 1 3091 #define HE_MU_BFER_ENABLE 1 3092 #define HE_SU_BFER_ENABLE 1 3093 3094 #define HE_VHT_SOUNDING_MODE_ENABLE 1 3095 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 3096 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 3097 3098 /* HE or VHT Sounding */ 3099 #define HE_VHT_SOUNDING_MODE BIT(0) 3100 /* SU or MU Sounding */ 3101 #define HE_SU_MU_SOUNDING_MODE BIT(2) 3102 /* Trig or Non-Trig Sounding */ 3103 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 3104 3105 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 3106 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 3107 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 3108 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 3109 3110 struct pdev_params { 3111 uint32_t param_id; 3112 uint32_t param_value; 3113 }; 3114 3115 enum wmi_peer_type { 3116 WMI_PEER_TYPE_DEFAULT = 0, 3117 WMI_PEER_TYPE_BSS = 1, 3118 WMI_PEER_TYPE_TDLS = 2, 3119 }; 3120 3121 struct wmi_peer_create_cmd { 3122 uint32_t tlv_header; 3123 uint32_t vdev_id; 3124 struct wmi_mac_addr peer_macaddr; 3125 uint32_t peer_type; 3126 } __packed; 3127 3128 struct wmi_peer_delete_cmd { 3129 uint32_t tlv_header; 3130 uint32_t vdev_id; 3131 struct wmi_mac_addr peer_macaddr; 3132 } __packed; 3133 3134 struct wmi_peer_reorder_queue_setup_cmd { 3135 uint32_t tlv_header; 3136 uint32_t vdev_id; 3137 struct wmi_mac_addr peer_macaddr; 3138 uint32_t tid; 3139 uint32_t queue_ptr_lo; 3140 uint32_t queue_ptr_hi; 3141 uint32_t queue_no; 3142 uint32_t ba_window_size_valid; 3143 uint32_t ba_window_size; 3144 } __packed; 3145 3146 struct wmi_peer_reorder_queue_remove_cmd { 3147 uint32_t tlv_header; 3148 uint32_t vdev_id; 3149 struct wmi_mac_addr peer_macaddr; 3150 uint32_t tid_mask; 3151 } __packed; 3152 3153 struct gpio_config_params { 3154 uint32_t gpio_num; 3155 uint32_t input; 3156 uint32_t pull_type; 3157 uint32_t intr_mode; 3158 }; 3159 3160 enum wmi_gpio_type { 3161 WMI_GPIO_PULL_NONE, 3162 WMI_GPIO_PULL_UP, 3163 WMI_GPIO_PULL_DOWN 3164 }; 3165 3166 enum wmi_gpio_intr_type { 3167 WMI_GPIO_INTTYPE_DISABLE, 3168 WMI_GPIO_INTTYPE_RISING_EDGE, 3169 WMI_GPIO_INTTYPE_FALLING_EDGE, 3170 WMI_GPIO_INTTYPE_BOTH_EDGE, 3171 WMI_GPIO_INTTYPE_LEVEL_LOW, 3172 WMI_GPIO_INTTYPE_LEVEL_HIGH 3173 }; 3174 3175 enum wmi_bss_chan_info_req_type { 3176 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3177 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3178 }; 3179 3180 struct wmi_gpio_config_cmd_param { 3181 uint32_t tlv_header; 3182 uint32_t gpio_num; 3183 uint32_t input; 3184 uint32_t pull_type; 3185 uint32_t intr_mode; 3186 }; 3187 3188 struct gpio_output_params { 3189 uint32_t gpio_num; 3190 uint32_t set; 3191 }; 3192 3193 struct wmi_gpio_output_cmd_param { 3194 uint32_t tlv_header; 3195 uint32_t gpio_num; 3196 uint32_t set; 3197 }; 3198 3199 struct set_fwtest_params { 3200 uint32_t arg; 3201 uint32_t value; 3202 }; 3203 3204 struct wmi_fwtest_set_param_cmd_param { 3205 uint32_t tlv_header; 3206 uint32_t param_id; 3207 uint32_t param_value; 3208 }; 3209 3210 struct wmi_pdev_set_param_cmd { 3211 uint32_t tlv_header; 3212 uint32_t pdev_id; 3213 uint32_t param_id; 3214 uint32_t param_value; 3215 } __packed; 3216 3217 struct wmi_pdev_set_ps_mode_cmd { 3218 uint32_t tlv_header; 3219 uint32_t vdev_id; 3220 uint32_t sta_ps_mode; 3221 } __packed; 3222 3223 struct wmi_pdev_suspend_cmd { 3224 uint32_t tlv_header; 3225 uint32_t pdev_id; 3226 uint32_t suspend_opt; 3227 } __packed; 3228 3229 struct wmi_pdev_resume_cmd { 3230 uint32_t tlv_header; 3231 uint32_t pdev_id; 3232 } __packed; 3233 3234 struct wmi_pdev_bss_chan_info_req_cmd { 3235 uint32_t tlv_header; 3236 /* ref wmi_bss_chan_info_req_type */ 3237 uint32_t req_type; 3238 uint32_t pdev_id; 3239 } __packed; 3240 3241 struct wmi_ap_ps_peer_cmd { 3242 uint32_t tlv_header; 3243 uint32_t vdev_id; 3244 struct wmi_mac_addr peer_macaddr; 3245 uint32_t param; 3246 uint32_t value; 3247 } __packed; 3248 3249 struct wmi_sta_powersave_param_cmd { 3250 uint32_t tlv_header; 3251 uint32_t vdev_id; 3252 uint32_t param; 3253 uint32_t value; 3254 } __packed; 3255 3256 struct wmi_pdev_set_regdomain_cmd { 3257 uint32_t tlv_header; 3258 uint32_t pdev_id; 3259 uint32_t reg_domain; 3260 uint32_t reg_domain_2g; 3261 uint32_t reg_domain_5g; 3262 uint32_t conformance_test_limit_2g; 3263 uint32_t conformance_test_limit_5g; 3264 uint32_t dfs_domain; 3265 } __packed; 3266 3267 struct wmi_peer_set_param_cmd { 3268 uint32_t tlv_header; 3269 uint32_t vdev_id; 3270 struct wmi_mac_addr peer_macaddr; 3271 uint32_t param_id; 3272 uint32_t param_value; 3273 } __packed; 3274 3275 struct wmi_peer_flush_tids_cmd { 3276 uint32_t tlv_header; 3277 uint32_t vdev_id; 3278 struct wmi_mac_addr peer_macaddr; 3279 uint32_t peer_tid_bitmap; 3280 } __packed; 3281 3282 struct wmi_dfs_phyerr_offload_cmd { 3283 uint32_t tlv_header; 3284 uint32_t pdev_id; 3285 } __packed; 3286 3287 struct wmi_bcn_offload_ctrl_cmd { 3288 uint32_t tlv_header; 3289 uint32_t vdev_id; 3290 uint32_t bcn_ctrl_op; 3291 } __packed; 3292 3293 enum scan_dwelltime_adaptive_mode { 3294 SCAN_DWELL_MODE_DEFAULT = 0, 3295 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3296 SCAN_DWELL_MODE_MODERATE = 2, 3297 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3298 SCAN_DWELL_MODE_STATIC = 4 3299 }; 3300 3301 #define WLAN_SSID_MAX_LEN 32 3302 3303 struct element_info { 3304 uint32_t len; 3305 uint8_t *ptr; 3306 }; 3307 3308 struct wlan_ssid { 3309 uint8_t length; 3310 uint8_t ssid[WLAN_SSID_MAX_LEN]; 3311 }; 3312 3313 #define WMI_IE_BITMAP_SIZE 8 3314 3315 /* prefix used by scan requestor ids on the host */ 3316 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3317 3318 /* prefix used by scan request ids generated on the host */ 3319 /* host cycles through the lower 12 bits to generate ids */ 3320 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3321 3322 /* Values lower than this may be refused by some firmware revisions with a scan 3323 * completion with a timedout reason. 3324 */ 3325 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3326 3327 /* Scan priority numbers must be sequential, starting with 0 */ 3328 enum wmi_scan_priority { 3329 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3330 WMI_SCAN_PRIORITY_LOW, 3331 WMI_SCAN_PRIORITY_MEDIUM, 3332 WMI_SCAN_PRIORITY_HIGH, 3333 WMI_SCAN_PRIORITY_VERY_HIGH, 3334 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3335 }; 3336 3337 enum wmi_scan_event_type { 3338 WMI_SCAN_EVENT_STARTED = BIT(0), 3339 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3340 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3341 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3342 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3343 /* possibly by high-prio scan */ 3344 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3345 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3346 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3347 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3348 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3349 WMI_SCAN_EVENT_RESUMED = BIT(10), 3350 WMI_SCAN_EVENT_MAX = BIT(15), 3351 }; 3352 3353 enum wmi_scan_completion_reason { 3354 WMI_SCAN_REASON_COMPLETED, 3355 WMI_SCAN_REASON_CANCELLED, 3356 WMI_SCAN_REASON_PREEMPTED, 3357 WMI_SCAN_REASON_TIMEDOUT, 3358 WMI_SCAN_REASON_INTERNAL_FAILURE, 3359 WMI_SCAN_REASON_MAX, 3360 }; 3361 3362 struct wmi_start_scan_cmd { 3363 uint32_t tlv_header; 3364 uint32_t scan_id; 3365 uint32_t scan_req_id; 3366 uint32_t vdev_id; 3367 uint32_t scan_priority; 3368 uint32_t notify_scan_events; 3369 uint32_t dwell_time_active; 3370 uint32_t dwell_time_passive; 3371 uint32_t min_rest_time; 3372 uint32_t max_rest_time; 3373 uint32_t repeat_probe_time; 3374 uint32_t probe_spacing_time; 3375 uint32_t idle_time; 3376 uint32_t max_scan_time; 3377 uint32_t probe_delay; 3378 uint32_t scan_ctrl_flags; 3379 uint32_t burst_duration; 3380 uint32_t num_chan; 3381 uint32_t num_bssid; 3382 uint32_t num_ssids; 3383 uint32_t ie_len; 3384 uint32_t n_probes; 3385 struct wmi_mac_addr mac_addr; 3386 struct wmi_mac_addr mac_mask; 3387 uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE]; 3388 uint32_t num_vendor_oui; 3389 uint32_t scan_ctrl_flags_ext; 3390 uint32_t dwell_time_active_2g; 3391 uint32_t dwell_time_active_6g; 3392 uint32_t dwell_time_passive_6g; 3393 uint32_t scan_start_offset; 3394 } __packed; 3395 3396 #define WMI_SCAN_FLAG_PASSIVE 0x1 3397 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3398 #define WMI_SCAN_ADD_CCK_RATES 0x4 3399 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3400 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3401 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3402 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3403 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3404 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3405 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3406 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3407 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3408 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3409 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3410 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3411 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3412 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3413 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3414 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3415 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3416 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3417 3418 #define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21) 3419 3420 enum { 3421 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3422 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3423 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3424 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3425 WMI_SCAN_DWELL_MODE_STATIC = 4, 3426 }; 3427 3428 struct hint_short_ssid { 3429 uint32_t freq_flags; 3430 uint32_t short_ssid; 3431 }; 3432 3433 struct hint_bssid { 3434 uint32_t freq_flags; 3435 struct wmi_mac_addr bssid; 3436 }; 3437 3438 struct scan_req_params { 3439 uint32_t scan_id; 3440 uint32_t scan_req_id; 3441 uint32_t vdev_id; 3442 uint32_t pdev_id; 3443 enum wmi_scan_priority scan_priority; 3444 union { 3445 struct { 3446 uint32_t scan_ev_started:1, 3447 scan_ev_completed:1, 3448 scan_ev_bss_chan:1, 3449 scan_ev_foreign_chan:1, 3450 scan_ev_dequeued:1, 3451 scan_ev_preempted:1, 3452 scan_ev_start_failed:1, 3453 scan_ev_restarted:1, 3454 scan_ev_foreign_chn_exit:1, 3455 scan_ev_invalid:1, 3456 scan_ev_gpio_timeout:1, 3457 scan_ev_suspended:1, 3458 scan_ev_resumed:1; 3459 }; 3460 uint32_t scan_events; 3461 }; 3462 uint32_t scan_ctrl_flags_ext; 3463 uint32_t dwell_time_active; 3464 uint32_t dwell_time_active_2g; 3465 uint32_t dwell_time_passive; 3466 uint32_t dwell_time_active_6g; 3467 uint32_t dwell_time_passive_6g; 3468 uint32_t min_rest_time; 3469 uint32_t max_rest_time; 3470 uint32_t repeat_probe_time; 3471 uint32_t probe_spacing_time; 3472 uint32_t idle_time; 3473 uint32_t max_scan_time; 3474 uint32_t probe_delay; 3475 union { 3476 struct { 3477 uint32_t scan_f_passive:1, 3478 scan_f_bcast_probe:1, 3479 scan_f_cck_rates:1, 3480 scan_f_ofdm_rates:1, 3481 scan_f_chan_stat_evnt:1, 3482 scan_f_filter_prb_req:1, 3483 scan_f_bypass_dfs_chn:1, 3484 scan_f_continue_on_err:1, 3485 scan_f_offchan_mgmt_tx:1, 3486 scan_f_offchan_data_tx:1, 3487 scan_f_promisc_mode:1, 3488 scan_f_capture_phy_err:1, 3489 scan_f_strict_passive_pch:1, 3490 scan_f_half_rate:1, 3491 scan_f_quarter_rate:1, 3492 scan_f_force_active_dfs_chn:1, 3493 scan_f_add_tpc_ie_in_probe:1, 3494 scan_f_add_ds_ie_in_probe:1, 3495 scan_f_add_spoofed_mac_in_probe:1, 3496 scan_f_add_rand_seq_in_probe:1, 3497 scan_f_en_ie_whitelist_in_probe:1, 3498 scan_f_forced:1, 3499 scan_f_2ghz:1, 3500 scan_f_5ghz:1, 3501 scan_f_80mhz:1; 3502 }; 3503 uint32_t scan_flags; 3504 }; 3505 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3506 uint32_t burst_duration; 3507 uint32_t num_chan; 3508 uint32_t num_bssid; 3509 uint32_t num_ssids; 3510 uint32_t n_probes; 3511 uint32_t *chan_list; 3512 uint32_t notify_scan_events; 3513 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3514 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3515 struct element_info extraie; 3516 struct element_info htcap; 3517 struct element_info vhtcap; 3518 uint32_t num_hint_s_ssid; 3519 uint32_t num_hint_bssid; 3520 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3521 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3522 struct wmi_mac_addr mac_addr; 3523 struct wmi_mac_addr mac_mask; 3524 }; 3525 3526 struct wmi_ssid_arg { 3527 int len; 3528 const uint8_t *ssid; 3529 }; 3530 3531 struct wmi_bssid_arg { 3532 const uint8_t *bssid; 3533 }; 3534 3535 struct wmi_start_scan_arg { 3536 uint32_t scan_id; 3537 uint32_t scan_req_id; 3538 uint32_t vdev_id; 3539 uint32_t scan_priority; 3540 uint32_t notify_scan_events; 3541 uint32_t dwell_time_active; 3542 uint32_t dwell_time_passive; 3543 uint32_t min_rest_time; 3544 uint32_t max_rest_time; 3545 uint32_t repeat_probe_time; 3546 uint32_t probe_spacing_time; 3547 uint32_t idle_time; 3548 uint32_t max_scan_time; 3549 uint32_t probe_delay; 3550 uint32_t scan_ctrl_flags; 3551 3552 uint32_t ie_len; 3553 uint32_t n_channels; 3554 uint32_t n_ssids; 3555 uint32_t n_bssids; 3556 3557 uint8_t ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3558 uint32_t channels[64]; 3559 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3560 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3561 }; 3562 3563 #define WMI_SCAN_STOP_ONE 0x00000000 3564 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3565 #define WMI_SCAN_STOP_ALL 0x04000000 3566 3567 /* Prefix 0xA000 indicates that the scan request 3568 * is trigger by HOST 3569 */ 3570 #define ATH12K_SCAN_ID 0xA000 3571 3572 enum scan_cancel_req_type { 3573 WLAN_SCAN_CANCEL_SINGLE = 1, 3574 WLAN_SCAN_CANCEL_VDEV_ALL, 3575 WLAN_SCAN_CANCEL_PDEV_ALL, 3576 }; 3577 3578 struct scan_cancel_param { 3579 uint32_t requester; 3580 uint32_t scan_id; 3581 enum scan_cancel_req_type req_type; 3582 uint32_t vdev_id; 3583 uint32_t pdev_id; 3584 }; 3585 3586 struct wmi_bcn_send_from_host_cmd { 3587 uint32_t tlv_header; 3588 uint32_t vdev_id; 3589 uint32_t data_len; 3590 union { 3591 uint32_t frag_ptr; 3592 uint32_t frag_ptr_lo; 3593 }; 3594 uint32_t frame_ctrl; 3595 uint32_t dtim_flag; 3596 uint32_t bcn_antenna; 3597 uint32_t frag_ptr_hi; 3598 }; 3599 3600 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3601 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3602 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3603 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3604 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3605 #define WMI_CHAN_INFO_DFS BIT(10) 3606 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3607 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3608 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3609 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3610 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3611 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3612 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3613 #define WMI_CHAN_INFO_PSC BIT(18) 3614 3615 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3616 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3617 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3618 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3619 3620 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3621 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3622 3623 struct wmi_channel { 3624 uint32_t tlv_header; 3625 uint32_t mhz; 3626 uint32_t band_center_freq1; 3627 uint32_t band_center_freq2; 3628 uint32_t info; 3629 uint32_t reg_info_1; 3630 uint32_t reg_info_2; 3631 } __packed; 3632 3633 struct wmi_mgmt_params { 3634 void *tx_frame; 3635 uint16_t frm_len; 3636 uint8_t vdev_id; 3637 uint16_t chanfreq; 3638 void *pdata; 3639 uint16_t desc_id; 3640 uint8_t *macaddr; 3641 }; 3642 3643 enum wmi_sta_ps_mode { 3644 WMI_STA_PS_MODE_DISABLED = 0, 3645 WMI_STA_PS_MODE_ENABLED = 1, 3646 }; 3647 3648 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3649 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3650 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3651 3652 #define ATH12K_WMI_FW_HANG_ASSERT_TYPE 1 3653 #define ATH12K_WMI_FW_HANG_DELAY 0 3654 3655 /* type, 0:unused 1: ASSERT 2: not respond detect command 3656 * delay_time_ms, the simulate will delay time 3657 */ 3658 3659 struct wmi_force_fw_hang_cmd { 3660 uint32_t tlv_header; 3661 uint32_t type; 3662 uint32_t delay_time_ms; 3663 }; 3664 3665 struct wmi_vdev_set_param_cmd { 3666 uint32_t tlv_header; 3667 uint32_t vdev_id; 3668 uint32_t param_id; 3669 uint32_t param_value; 3670 } __packed; 3671 3672 enum wmi_stats_id { 3673 WMI_REQUEST_PEER_STAT = BIT(0), 3674 WMI_REQUEST_AP_STAT = BIT(1), 3675 WMI_REQUEST_PDEV_STAT = BIT(2), 3676 WMI_REQUEST_VDEV_STAT = BIT(3), 3677 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3678 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3679 WMI_REQUEST_INST_STAT = BIT(6), 3680 WMI_REQUEST_MIB_STAT = BIT(7), 3681 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3682 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3683 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3684 WMI_REQUEST_BCN_STAT = BIT(11), 3685 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3686 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3687 }; 3688 3689 struct wmi_request_stats_cmd { 3690 uint32_t tlv_header; 3691 enum wmi_stats_id stats_id; 3692 uint32_t vdev_id; 3693 struct wmi_mac_addr peer_macaddr; 3694 uint32_t pdev_id; 3695 } __packed; 3696 3697 struct wmi_get_pdev_temperature_cmd { 3698 uint32_t tlv_header; 3699 uint32_t param; 3700 uint32_t pdev_id; 3701 } __packed; 3702 3703 struct wmi_ftm_seg_hdr { 3704 uint32_t len; 3705 uint32_t msgref; 3706 uint32_t segmentinfo; 3707 uint32_t pdev_id; 3708 } __packed; 3709 3710 struct wmi_ftm_cmd { 3711 uint32_t tlv_header; 3712 struct wmi_ftm_seg_hdr seg_hdr; 3713 uint8_t data[]; 3714 } __packed; 3715 3716 struct wmi_ftm_event_msg { 3717 struct wmi_ftm_seg_hdr seg_hdr; 3718 uint8_t data[]; 3719 } __packed; 3720 3721 #define WMI_BEACON_TX_BUFFER_SIZE 512 3722 3723 #define WMI_EMA_TMPL_IDX_SHIFT 8 3724 #define WMI_EMA_FIRST_TMPL_SHIFT 16 3725 #define WMI_EMA_LAST_TMPL_SHIFT 24 3726 3727 struct wmi_bcn_tmpl_cmd { 3728 uint32_t tlv_header; 3729 uint32_t vdev_id; 3730 uint32_t tim_ie_offset; 3731 uint32_t buf_len; 3732 uint32_t csa_switch_count_offset; 3733 uint32_t ext_csa_switch_count_offset; 3734 uint32_t csa_event_bitmap; 3735 uint32_t mbssid_ie_offset; 3736 uint32_t esp_ie_offset; 3737 uint32_t csc_switch_count_offset; 3738 uint32_t csc_event_bitmap; 3739 uint32_t mu_edca_ie_offset; 3740 uint32_t feature_enable_bitmap; 3741 uint32_t ema_params; 3742 } __packed; 3743 3744 struct wmi_key_seq_counter { 3745 uint32_t key_seq_counter_l; 3746 uint32_t key_seq_counter_h; 3747 } __packed; 3748 3749 struct wmi_vdev_install_key_cmd { 3750 uint32_t tlv_header; 3751 uint32_t vdev_id; 3752 struct wmi_mac_addr peer_macaddr; 3753 uint32_t key_idx; 3754 uint32_t key_flags; 3755 uint32_t key_cipher; 3756 struct wmi_key_seq_counter key_rsc_counter; 3757 struct wmi_key_seq_counter key_global_rsc_counter; 3758 struct wmi_key_seq_counter key_tsc_counter; 3759 uint8_t wpi_key_rsc_counter[16]; 3760 uint8_t wpi_key_tsc_counter[16]; 3761 uint32_t key_len; 3762 uint32_t key_txmic_len; 3763 uint32_t key_rxmic_len; 3764 uint32_t is_group_key_id_valid; 3765 uint32_t group_key_id; 3766 3767 /* Followed by key_data containing key followed by 3768 * tx mic and then rx mic 3769 */ 3770 } __packed; 3771 3772 struct wmi_vdev_install_key_arg { 3773 uint32_t vdev_id; 3774 const uint8_t *macaddr; 3775 uint32_t key_idx; 3776 uint32_t key_flags; 3777 uint32_t key_cipher; 3778 uint32_t key_len; 3779 uint32_t key_txmic_len; 3780 uint32_t key_rxmic_len; 3781 uint64_t key_rsc_counter; 3782 const void *key_data; 3783 }; 3784 3785 #define WMI_MAX_SUPPORTED_RATES 128 3786 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3787 #define WMI_HOST_MAX_HE_RATE_SET 3 3788 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3789 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3790 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3791 3792 struct wmi_rate_set_arg { 3793 uint32_t num_rates; 3794 uint8_t rates[WMI_MAX_SUPPORTED_RATES]; 3795 }; 3796 3797 struct peer_assoc_params { 3798 struct wmi_mac_addr peer_macaddr; 3799 uint32_t vdev_id; 3800 uint32_t peer_new_assoc; 3801 uint32_t peer_associd; 3802 uint32_t peer_flags; 3803 uint32_t peer_caps; 3804 uint32_t peer_listen_intval; 3805 uint32_t peer_ht_caps; 3806 uint32_t peer_max_mpdu; 3807 uint32_t peer_mpdu_density; 3808 uint32_t peer_rate_caps; 3809 uint32_t peer_nss; 3810 uint32_t peer_vht_caps; 3811 uint32_t peer_phymode; 3812 uint32_t peer_ht_info[2]; 3813 struct wmi_rate_set_arg peer_legacy_rates; 3814 struct wmi_rate_set_arg peer_ht_rates; 3815 uint32_t rx_max_rate; 3816 uint32_t rx_mcs_set; 3817 uint32_t tx_max_rate; 3818 uint32_t tx_mcs_set; 3819 uint8_t vht_capable; 3820 uint8_t min_data_rate; 3821 uint32_t tx_max_mcs_nss; 3822 uint32_t peer_bw_rxnss_override; 3823 bool is_pmf_enabled; 3824 bool is_wme_set; 3825 bool qos_flag; 3826 bool apsd_flag; 3827 bool ht_flag; 3828 bool bw_40; 3829 bool bw_80; 3830 bool bw_160; 3831 bool stbc_flag; 3832 bool ldpc_flag; 3833 bool static_mimops_flag; 3834 bool dynamic_mimops_flag; 3835 bool spatial_mux_flag; 3836 bool vht_flag; 3837 bool vht_ng_flag; 3838 bool need_ptk_4_way; 3839 bool need_gtk_2_way; 3840 bool auth_flag; 3841 bool safe_mode_enabled; 3842 bool amsdu_disable; 3843 /* Use common structure */ 3844 uint8_t peer_mac[IEEE80211_ADDR_LEN]; 3845 3846 bool he_flag; 3847 uint32_t peer_he_cap_macinfo[2]; 3848 uint32_t peer_he_cap_macinfo_internal; 3849 uint32_t peer_he_caps_6ghz; 3850 uint32_t peer_he_ops; 3851 uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3852 uint32_t peer_he_mcs_count; 3853 uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3854 uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3855 bool twt_responder; 3856 bool twt_requester; 3857 bool is_assoc; 3858 struct ath12k_ppe_threshold peer_ppet; 3859 }; 3860 3861 struct wmi_peer_assoc_complete_cmd { 3862 uint32_t tlv_header; 3863 struct wmi_mac_addr peer_macaddr; 3864 uint32_t vdev_id; 3865 uint32_t peer_new_assoc; 3866 uint32_t peer_associd; 3867 uint32_t peer_flags; 3868 uint32_t peer_caps; 3869 uint32_t peer_listen_intval; 3870 uint32_t peer_ht_caps; 3871 uint32_t peer_max_mpdu; 3872 uint32_t peer_mpdu_density; 3873 uint32_t peer_rate_caps; 3874 uint32_t peer_nss; 3875 uint32_t peer_vht_caps; 3876 uint32_t peer_phymode; 3877 uint32_t peer_ht_info[2]; 3878 uint32_t num_peer_legacy_rates; 3879 uint32_t num_peer_ht_rates; 3880 uint32_t peer_bw_rxnss_override; 3881 struct wmi_ppe_threshold peer_ppet; 3882 uint32_t peer_he_cap_info; 3883 uint32_t peer_he_ops; 3884 uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3885 uint32_t peer_he_mcs; 3886 uint32_t peer_he_cap_info_ext; 3887 uint32_t peer_he_cap_info_internal; 3888 uint32_t min_data_rate; 3889 uint32_t peer_he_caps_6ghz; 3890 } __packed; 3891 3892 struct wmi_stop_scan_cmd { 3893 uint32_t tlv_header; 3894 uint32_t requestor; 3895 uint32_t scan_id; 3896 uint32_t req_type; 3897 uint32_t vdev_id; 3898 uint32_t pdev_id; 3899 }; 3900 3901 struct scan_chan_list_params { 3902 uint32_t pdev_id; 3903 uint16_t nallchans; 3904 struct channel_param ch_param[]; 3905 }; 3906 3907 struct wmi_scan_chan_list_cmd { 3908 uint32_t tlv_header; 3909 uint32_t num_scan_chans; 3910 uint32_t flags; 3911 uint32_t pdev_id; 3912 } __packed; 3913 3914 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3915 3916 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3917 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3918 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3919 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3920 3921 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3922 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3923 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3924 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3925 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3926 3927 struct wmi_mgmt_send_cmd { 3928 uint32_t tlv_header; 3929 uint32_t vdev_id; 3930 uint32_t desc_id; 3931 uint32_t chanfreq; 3932 uint32_t paddr_lo; 3933 uint32_t paddr_hi; 3934 uint32_t frame_len; 3935 uint32_t buf_len; 3936 uint32_t tx_params_valid; 3937 3938 /* 3939 * Followed by struct wmi_tlv and buf_len bytes of frame data with 3940 * buf_len <= WMI_MGMT_SEND_DOWNLD_LEN, which may be exceeded by 3941 * frame_len. The full frame is mapped at paddr_lo/hi. 3942 * Presumably the idea is that small frames can skip the extra DMA 3943 * transfer of frame data after the command has been transferred. 3944 */ 3945 } __packed; 3946 3947 struct wmi_sta_powersave_mode_cmd { 3948 uint32_t tlv_header; 3949 uint32_t vdev_id; 3950 uint32_t sta_ps_mode; 3951 }; 3952 3953 struct wmi_sta_smps_force_mode_cmd { 3954 uint32_t tlv_header; 3955 uint32_t vdev_id; 3956 uint32_t forced_mode; 3957 }; 3958 3959 struct wmi_sta_smps_param_cmd { 3960 uint32_t tlv_header; 3961 uint32_t vdev_id; 3962 uint32_t param; 3963 uint32_t value; 3964 }; 3965 3966 struct wmi_bcn_prb_info { 3967 uint32_t tlv_header; 3968 uint32_t caps; 3969 uint32_t erp; 3970 } __packed; 3971 3972 enum { 3973 WMI_PDEV_SUSPEND, 3974 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3975 }; 3976 3977 struct green_ap_ps_params { 3978 uint32_t value; 3979 }; 3980 3981 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3982 uint32_t tlv_header; 3983 uint32_t pdev_id; 3984 uint32_t enable; 3985 }; 3986 3987 struct ap_ps_params { 3988 uint32_t vdev_id; 3989 uint32_t param; 3990 uint32_t value; 3991 }; 3992 3993 struct vdev_set_params { 3994 uint32_t if_id; 3995 uint32_t param_id; 3996 uint32_t param_value; 3997 }; 3998 3999 struct stats_request_params { 4000 uint32_t stats_id; 4001 uint32_t vdev_id; 4002 uint32_t pdev_id; 4003 }; 4004 4005 struct wmi_set_current_country_params { 4006 uint8_t alpha2[3]; 4007 }; 4008 4009 struct wmi_set_current_country_cmd { 4010 uint32_t tlv_header; 4011 uint32_t pdev_id; 4012 uint32_t new_alpha2; 4013 } __packed; 4014 4015 enum set_init_cc_type { 4016 WMI_COUNTRY_INFO_TYPE_ALPHA, 4017 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 4018 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 4019 }; 4020 4021 enum set_init_cc_flags { 4022 INVALID_CC, 4023 CC_IS_SET, 4024 REGDMN_IS_SET, 4025 ALPHA_IS_SET, 4026 }; 4027 4028 struct wmi_init_country_params { 4029 union { 4030 uint16_t country_code; 4031 uint16_t regdom_id; 4032 uint8_t alpha2[3]; 4033 } cc_info; 4034 enum set_init_cc_flags flags; 4035 }; 4036 4037 struct wmi_init_country_cmd { 4038 uint32_t tlv_header; 4039 uint32_t pdev_id; 4040 uint32_t init_cc_type; 4041 union { 4042 uint32_t country_code; 4043 uint32_t regdom_id; 4044 uint32_t alpha2; 4045 } cc_info; 4046 } __packed; 4047 4048 struct wmi_11d_scan_start_params { 4049 uint32_t vdev_id; 4050 uint32_t scan_period_msec; 4051 uint32_t start_interval_msec; 4052 }; 4053 4054 struct wmi_11d_scan_start_cmd { 4055 uint32_t tlv_header; 4056 uint32_t vdev_id; 4057 uint32_t scan_period_msec; 4058 uint32_t start_interval_msec; 4059 } __packed; 4060 4061 struct wmi_11d_scan_stop_cmd { 4062 uint32_t tlv_header; 4063 uint32_t vdev_id; 4064 } __packed; 4065 4066 struct wmi_11d_new_cc_ev { 4067 uint32_t new_alpha2; 4068 } __packed; 4069 4070 #define THERMAL_LEVELS 1 4071 struct tt_level_config { 4072 uint32_t tmplwm; 4073 uint32_t tmphwm; 4074 uint32_t dcoffpercent; 4075 uint32_t priority; 4076 }; 4077 4078 struct thermal_mitigation_params { 4079 uint32_t pdev_id; 4080 uint32_t enable; 4081 uint32_t dc; 4082 uint32_t dc_per_event; 4083 struct tt_level_config levelconf[THERMAL_LEVELS]; 4084 }; 4085 4086 struct wmi_therm_throt_config_request_cmd { 4087 uint32_t tlv_header; 4088 uint32_t pdev_id; 4089 uint32_t enable; 4090 uint32_t dc; 4091 uint32_t dc_per_event; 4092 uint32_t therm_throt_levels; 4093 } __packed; 4094 4095 struct wmi_therm_throt_level_config_info { 4096 uint32_t tlv_header; 4097 uint32_t temp_lwm; 4098 uint32_t temp_hwm; 4099 uint32_t dc_off_percent; 4100 uint32_t prio; 4101 } __packed; 4102 4103 struct wmi_delba_send_cmd { 4104 uint32_t tlv_header; 4105 uint32_t vdev_id; 4106 struct wmi_mac_addr peer_macaddr; 4107 uint32_t tid; 4108 uint32_t initiator; 4109 uint32_t reasoncode; 4110 } __packed; 4111 4112 struct wmi_addba_setresponse_cmd { 4113 uint32_t tlv_header; 4114 uint32_t vdev_id; 4115 struct wmi_mac_addr peer_macaddr; 4116 uint32_t tid; 4117 uint32_t statuscode; 4118 } __packed; 4119 4120 struct wmi_addba_send_cmd { 4121 uint32_t tlv_header; 4122 uint32_t vdev_id; 4123 struct wmi_mac_addr peer_macaddr; 4124 uint32_t tid; 4125 uint32_t buffersize; 4126 } __packed; 4127 4128 struct wmi_addba_clear_resp_cmd { 4129 uint32_t tlv_header; 4130 uint32_t vdev_id; 4131 struct wmi_mac_addr peer_macaddr; 4132 } __packed; 4133 4134 struct wmi_pdev_pktlog_filter_info { 4135 uint32_t tlv_header; 4136 struct wmi_mac_addr peer_macaddr; 4137 } __packed; 4138 4139 struct wmi_pdev_pktlog_filter_cmd { 4140 uint32_t tlv_header; 4141 uint32_t pdev_id; 4142 uint32_t enable; 4143 uint32_t filter_type; 4144 uint32_t num_mac; 4145 } __packed; 4146 4147 enum ath12k_wmi_pktlog_enable { 4148 ATH12K_WMI_PKTLOG_ENABLE_AUTO = 0, 4149 ATH12K_WMI_PKTLOG_ENABLE_FORCE = 1, 4150 }; 4151 4152 struct wmi_pktlog_enable_cmd { 4153 uint32_t tlv_header; 4154 uint32_t pdev_id; 4155 uint32_t evlist; /* WMI_PKTLOG_EVENT */ 4156 uint32_t enable; 4157 } __packed; 4158 4159 struct wmi_pktlog_disable_cmd { 4160 uint32_t tlv_header; 4161 uint32_t pdev_id; 4162 } __packed; 4163 4164 #define DFS_PHYERR_UNIT_TEST_CMD 0 4165 #define DFS_UNIT_TEST_MODULE 0x2b 4166 #define DFS_UNIT_TEST_TOKEN 0xAA 4167 4168 enum dfs_test_args_idx { 4169 DFS_TEST_CMDID = 0, 4170 DFS_TEST_PDEV_ID, 4171 DFS_TEST_RADAR_PARAM, 4172 DFS_MAX_TEST_ARGS, 4173 }; 4174 4175 struct wmi_dfs_unit_test_arg { 4176 uint32_t cmd_id; 4177 uint32_t pdev_id; 4178 uint32_t radar_param; 4179 }; 4180 4181 struct wmi_unit_test_cmd { 4182 uint32_t tlv_header; 4183 uint32_t vdev_id; 4184 uint32_t module_id; 4185 uint32_t num_args; 4186 uint32_t diag_token; 4187 /* Followed by test args*/ 4188 } __packed; 4189 4190 #define MAX_SUPPORTED_RATES 128 4191 4192 #define WMI_PEER_AUTH 0x00000001 4193 #define WMI_PEER_QOS 0x00000002 4194 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 4195 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 4196 #define WMI_PEER_HE 0x00000400 4197 #define WMI_PEER_APSD 0x00000800 4198 #define WMI_PEER_HT 0x00001000 4199 #define WMI_PEER_40MHZ 0x00002000 4200 #define WMI_PEER_STBC 0x00008000 4201 #define WMI_PEER_LDPC 0x00010000 4202 #define WMI_PEER_DYN_MIMOPS 0x00020000 4203 #define WMI_PEER_STATIC_MIMOPS 0x00040000 4204 #define WMI_PEER_SPATIAL_MUX 0x00200000 4205 #define WMI_PEER_TWT_REQ 0x00400000 4206 #define WMI_PEER_TWT_RESP 0x00800000 4207 #define WMI_PEER_VHT 0x02000000 4208 #define WMI_PEER_80MHZ 0x04000000 4209 #define WMI_PEER_PMF 0x08000000 4210 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4211 * Need to be cleaned up 4212 */ 4213 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4214 #define WMI_PEER_160MHZ 0x40000000 4215 #define WMI_PEER_SAFEMODE_EN 0x80000000 4216 4217 struct beacon_tmpl_params { 4218 uint8_t vdev_id; 4219 uint32_t tim_ie_offset; 4220 uint32_t tmpl_len; 4221 uint32_t tmpl_len_aligned; 4222 uint32_t csa_switch_count_offset; 4223 uint32_t ext_csa_switch_count_offset; 4224 uint8_t *frm; 4225 }; 4226 4227 struct wmi_rate_set { 4228 uint32_t num_rates; 4229 uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4230 }; 4231 4232 struct wmi_vht_rate_set { 4233 uint32_t tlv_header; 4234 uint32_t rx_max_rate; 4235 uint32_t rx_mcs_set; 4236 uint32_t tx_max_rate; 4237 uint32_t tx_mcs_set; 4238 uint32_t tx_max_mcs_nss; 4239 } __packed; 4240 4241 struct wmi_he_rate_set { 4242 uint32_t tlv_header; 4243 4244 /* MCS at which the peer can receive */ 4245 uint32_t rx_mcs_set; 4246 4247 /* MCS at which the peer can transmit */ 4248 uint32_t tx_mcs_set; 4249 } __packed; 4250 4251 #define MAX_REG_RULES 10 4252 #define REG_ALPHA2_LEN 2 4253 #define MAX_6GHZ_REG_RULES 5 4254 4255 enum wmi_start_event_param { 4256 WMI_VDEV_START_RESP_EVENT = 0, 4257 WMI_VDEV_RESTART_RESP_EVENT, 4258 }; 4259 4260 struct wmi_vdev_start_resp_event { 4261 uint32_t vdev_id; 4262 uint32_t requestor_id; 4263 enum wmi_start_event_param resp_type; 4264 uint32_t status; 4265 uint32_t chain_mask; 4266 uint32_t smps_mode; 4267 union { 4268 uint32_t mac_id; 4269 uint32_t pdev_id; 4270 }; 4271 uint32_t cfgd_tx_streams; 4272 uint32_t cfgd_rx_streams; 4273 } __packed; 4274 4275 /* VDEV start response status codes */ 4276 enum wmi_vdev_start_resp_status_code { 4277 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4278 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4279 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4280 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4281 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4282 }; 4283 4284 /* Regulatory Rule Flags Passed by FW */ 4285 #define REGULATORY_CHAN_DISABLED BIT(0) 4286 #define REGULATORY_CHAN_NO_IR BIT(1) 4287 #define REGULATORY_CHAN_RADAR BIT(3) 4288 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4289 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4290 4291 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4292 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4293 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4294 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4295 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4296 4297 enum wmi_reg_chan_list_cmd_type { 4298 WMI_REG_CHAN_LIST_CC_ID = 0, 4299 WMI_REG_CHAN_LIST_CC_EXT_ID = 1, 4300 }; 4301 4302 enum wmi_reg_cc_setting_code { 4303 WMI_REG_SET_CC_STATUS_PASS = 0, 4304 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4305 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4306 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4307 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4308 WMI_REG_SET_CC_STATUS_FAIL = 5, 4309 4310 /* add new setting code above, update in 4311 * @enum cc_setting_code as well. 4312 * Also handle it in ath12k_wmi_cc_setting_code_to_reg() 4313 */ 4314 }; 4315 4316 enum cc_setting_code { 4317 REG_SET_CC_STATUS_PASS = 0, 4318 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4319 REG_INIT_ALPHA2_NOT_FOUND = 2, 4320 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4321 REG_SET_CC_STATUS_NO_MEMORY = 4, 4322 REG_SET_CC_STATUS_FAIL = 5, 4323 4324 /* add new setting code above, update in 4325 * @enum wmi_reg_cc_setting_code as well. 4326 * Also handle it in ath12k_cc_status_to_str() 4327 */ 4328 }; 4329 4330 static inline enum cc_setting_code 4331 qwz_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) 4332 { 4333 switch (status_code) { 4334 case WMI_REG_SET_CC_STATUS_PASS: 4335 return REG_SET_CC_STATUS_PASS; 4336 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 4337 return REG_CURRENT_ALPHA2_NOT_FOUND; 4338 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 4339 return REG_INIT_ALPHA2_NOT_FOUND; 4340 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 4341 return REG_SET_CC_CHANGE_NOT_ALLOWED; 4342 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 4343 return REG_SET_CC_STATUS_NO_MEMORY; 4344 case WMI_REG_SET_CC_STATUS_FAIL: 4345 return REG_SET_CC_STATUS_FAIL; 4346 } 4347 4348 return REG_SET_CC_STATUS_FAIL; 4349 } 4350 4351 static inline const char * 4352 qwz_cc_status_to_str(enum cc_setting_code code) 4353 { 4354 switch (code) { 4355 case REG_SET_CC_STATUS_PASS: 4356 return "REG_SET_CC_STATUS_PASS"; 4357 case REG_CURRENT_ALPHA2_NOT_FOUND: 4358 return "REG_CURRENT_ALPHA2_NOT_FOUND"; 4359 case REG_INIT_ALPHA2_NOT_FOUND: 4360 return "REG_INIT_ALPHA2_NOT_FOUND"; 4361 case REG_SET_CC_CHANGE_NOT_ALLOWED: 4362 return "REG_SET_CC_CHANGE_NOT_ALLOWED"; 4363 case REG_SET_CC_STATUS_NO_MEMORY: 4364 return "REG_SET_CC_STATUS_NO_MEMORY"; 4365 case REG_SET_CC_STATUS_FAIL: 4366 return "REG_SET_CC_STATUS_FAIL"; 4367 } 4368 4369 return "Unknown CC status"; 4370 } 4371 4372 enum wmi_reg_6ghz_ap_type { 4373 WMI_REG_INDOOR_AP = 0, 4374 WMI_REG_STANDARD_POWER_AP = 1, 4375 WMI_REG_VERY_LOW_POWER_AP = 2, 4376 4377 /* add AP type above, handle in ath12k_6ghz_ap_type_to_str() 4378 */ 4379 WMI_REG_CURRENT_MAX_AP_TYPE, 4380 WMI_REG_MAX_AP_TYPE = 7, 4381 }; 4382 4383 static inline const char * 4384 qwz_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) 4385 { 4386 switch (type) { 4387 case WMI_REG_INDOOR_AP: 4388 return "INDOOR AP"; 4389 case WMI_REG_STANDARD_POWER_AP: 4390 return "STANDARD POWER AP"; 4391 case WMI_REG_VERY_LOW_POWER_AP: 4392 return "VERY LOW POWER AP"; 4393 case WMI_REG_CURRENT_MAX_AP_TYPE: 4394 return "CURRENT_MAX_AP_TYPE"; 4395 case WMI_REG_MAX_AP_TYPE: 4396 return "MAX_AP_TYPE"; 4397 } 4398 4399 return "unknown 6 GHz AP type"; 4400 } 4401 4402 enum wmi_reg_6ghz_client_type { 4403 WMI_REG_DEFAULT_CLIENT = 0, 4404 WMI_REG_SUBORDINATE_CLIENT = 1, 4405 WMI_REG_MAX_CLIENT_TYPE = 2, 4406 4407 /* add client type above, handle it in 4408 * ath12k_6ghz_client_type_to_str() 4409 */ 4410 }; 4411 4412 static inline const char * 4413 qwz_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) 4414 { 4415 switch (type) { 4416 case WMI_REG_DEFAULT_CLIENT: 4417 return "DEFAULT CLIENT"; 4418 case WMI_REG_SUBORDINATE_CLIENT: 4419 return "SUBORDINATE CLIENT"; 4420 case WMI_REG_MAX_CLIENT_TYPE: 4421 return "MAX_CLIENT_TYPE"; 4422 } 4423 4424 return "unknown 6 GHz client type"; 4425 } 4426 4427 enum reg_subdomains_6ghz { 4428 EMPTY_6GHZ = 0x0, 4429 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, 4430 FCC1_CLIENT_SP_6GHZ = 0x02, 4431 FCC1_AP_LPI_6GHZ = 0x03, 4432 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, 4433 FCC1_AP_SP_6GHZ = 0x04, 4434 ETSI1_LPI_6GHZ = 0x10, 4435 ETSI1_VLP_6GHZ = 0x11, 4436 ETSI2_LPI_6GHZ = 0x12, 4437 ETSI2_VLP_6GHZ = 0x13, 4438 APL1_LPI_6GHZ = 0x20, 4439 APL1_VLP_6GHZ = 0x21, 4440 4441 /* add sub-domain above, handle it in 4442 * ath12k_sub_reg_6ghz_to_str() 4443 */ 4444 }; 4445 4446 static inline const char * 4447 qwz_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) 4448 { 4449 switch (sub_id) { 4450 case EMPTY_6GHZ: 4451 return "N/A"; 4452 case FCC1_CLIENT_LPI_REGULAR_6GHZ: 4453 return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; 4454 case FCC1_CLIENT_SP_6GHZ: 4455 return "FCC1_CLIENT_SP_6GHZ"; 4456 case FCC1_AP_LPI_6GHZ: 4457 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; 4458 case FCC1_AP_SP_6GHZ: 4459 return "FCC1_AP_SP_6GHZ"; 4460 case ETSI1_LPI_6GHZ: 4461 return "ETSI1_LPI_6GHZ"; 4462 case ETSI1_VLP_6GHZ: 4463 return "ETSI1_VLP_6GHZ"; 4464 case ETSI2_LPI_6GHZ: 4465 return "ETSI2_LPI_6GHZ"; 4466 case ETSI2_VLP_6GHZ: 4467 return "ETSI2_VLP_6GHZ"; 4468 case APL1_LPI_6GHZ: 4469 return "APL1_LPI_6GHZ"; 4470 case APL1_VLP_6GHZ: 4471 return "APL1_VLP_6GHZ"; 4472 } 4473 4474 return "unknown sub reg id"; 4475 } 4476 4477 enum reg_super_domain_6ghz { 4478 FCC1_6GHZ = 0x01, 4479 ETSI1_6GHZ = 0x02, 4480 ETSI2_6GHZ = 0x03, 4481 APL1_6GHZ = 0x04, 4482 FCC1_6GHZ_CL = 0x05, 4483 4484 /* add super domain above, handle it in 4485 * ath12k_super_reg_6ghz_to_str() 4486 */ 4487 }; 4488 4489 static inline const char * 4490 qwz_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) 4491 { 4492 switch (domain_id) { 4493 case FCC1_6GHZ: 4494 return "FCC1_6GHZ"; 4495 case ETSI1_6GHZ: 4496 return "ETSI1_6GHZ"; 4497 case ETSI2_6GHZ: 4498 return "ETSI2_6GHZ"; 4499 case APL1_6GHZ: 4500 return "APL1_6GHZ"; 4501 case FCC1_6GHZ_CL: 4502 return "FCC1_6GHZ_CL"; 4503 } 4504 4505 return "unknown domain id"; 4506 } 4507 4508 struct cur_reg_rule { 4509 uint16_t start_freq; 4510 uint16_t end_freq; 4511 uint16_t max_bw; 4512 uint8_t reg_power; 4513 uint8_t ant_gain; 4514 uint16_t flags; 4515 bool psd_flag; 4516 int8_t psd_eirp; 4517 }; 4518 4519 struct cur_regulatory_info { 4520 enum cc_setting_code status_code; 4521 uint8_t num_phy; 4522 uint8_t phy_id; 4523 uint16_t reg_dmn_pair; 4524 uint16_t ctry_code; 4525 uint8_t alpha2[REG_ALPHA2_LEN + 1]; 4526 uint32_t dfs_region; 4527 uint32_t phybitmap; 4528 uint32_t min_bw_2ghz; 4529 uint32_t max_bw_2ghz; 4530 uint32_t min_bw_5ghz; 4531 uint32_t max_bw_5ghz; 4532 uint32_t num_2ghz_reg_rules; 4533 uint32_t num_5ghz_reg_rules; 4534 struct cur_reg_rule *reg_rules_2ghz_ptr; 4535 struct cur_reg_rule *reg_rules_5ghz_ptr; 4536 bool is_ext_reg_event; 4537 enum wmi_reg_6ghz_client_type client_type; 4538 bool rnr_tpe_usable; 4539 bool unspecified_ap_usable; 4540 uint8_t domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4541 uint8_t domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4542 uint32_t domain_code_6ghz_super_id; 4543 uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4544 uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4545 uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4546 uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4547 uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4548 uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4549 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 4550 struct cur_reg_rule *reg_rules_6ghz_client_ptr 4551 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4552 }; 4553 4554 struct wmi_reg_chan_list_cc_event { 4555 uint32_t status_code; 4556 uint32_t phy_id; 4557 uint32_t alpha2; 4558 uint32_t num_phy; 4559 uint32_t country_id; 4560 uint32_t domain_code; 4561 uint32_t dfs_region; 4562 uint32_t phybitmap; 4563 uint32_t min_bw_2ghz; 4564 uint32_t max_bw_2ghz; 4565 uint32_t min_bw_5ghz; 4566 uint32_t max_bw_5ghz; 4567 uint32_t num_2ghz_reg_rules; 4568 uint32_t num_5ghz_reg_rules; 4569 } __packed; 4570 4571 struct wmi_regulatory_rule_struct { 4572 uint32_t tlv_header; 4573 uint32_t freq_info; 4574 uint32_t bw_pwr_info; 4575 uint32_t flag_info; 4576 }; 4577 4578 #define WMI_REG_CLIENT_MAX 4 4579 4580 struct wmi_reg_chan_list_cc_ext_event { 4581 uint32_t status_code; 4582 uint32_t phy_id; 4583 uint32_t alpha2; 4584 uint32_t num_phy; 4585 uint32_t country_id; 4586 uint32_t domain_code; 4587 uint32_t dfs_region; 4588 uint32_t phybitmap; 4589 uint32_t min_bw_2ghz; 4590 uint32_t max_bw_2ghz; 4591 uint32_t min_bw_5ghz; 4592 uint32_t max_bw_5ghz; 4593 uint32_t num_2ghz_reg_rules; 4594 uint32_t num_5ghz_reg_rules; 4595 uint32_t client_type; 4596 uint32_t rnr_tpe_usable; 4597 uint32_t unspecified_ap_usable; 4598 uint32_t domain_code_6ghz_ap_lpi; 4599 uint32_t domain_code_6ghz_ap_sp; 4600 uint32_t domain_code_6ghz_ap_vlp; 4601 uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4602 uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4603 uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4604 uint32_t domain_code_6ghz_super_id; 4605 uint32_t min_bw_6ghz_ap_sp; 4606 uint32_t max_bw_6ghz_ap_sp; 4607 uint32_t min_bw_6ghz_ap_lpi; 4608 uint32_t max_bw_6ghz_ap_lpi; 4609 uint32_t min_bw_6ghz_ap_vlp; 4610 uint32_t max_bw_6ghz_ap_vlp; 4611 uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4612 uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4613 uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4614 uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4615 uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4616 uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4617 uint32_t num_6ghz_reg_rules_ap_sp; 4618 uint32_t num_6ghz_reg_rules_ap_lpi; 4619 uint32_t num_6ghz_reg_rules_ap_vlp; 4620 uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; 4621 uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; 4622 uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; 4623 } __packed; 4624 4625 struct wmi_regulatory_ext_rule { 4626 uint32_t tlv_header; 4627 uint32_t freq_info; 4628 uint32_t bw_pwr_info; 4629 uint32_t flag_info; 4630 uint32_t psd_power_info; 4631 } __packed; 4632 4633 struct wmi_vdev_delete_resp_event { 4634 uint32_t vdev_id; 4635 } __packed; 4636 4637 struct wmi_peer_delete_resp_event { 4638 uint32_t vdev_id; 4639 struct wmi_mac_addr peer_macaddr; 4640 } __packed; 4641 4642 struct wmi_bcn_tx_status_event { 4643 uint32_t vdev_id; 4644 uint32_t tx_status; 4645 } __packed; 4646 4647 struct wmi_vdev_stopped_event { 4648 uint32_t vdev_id; 4649 } __packed; 4650 4651 struct wmi_pdev_bss_chan_info_event { 4652 uint32_t freq; /* Units in MHz */ 4653 uint32_t noise_floor; /* units are dBm */ 4654 /* rx clear - how often the channel was unused */ 4655 uint32_t rx_clear_count_low; 4656 uint32_t rx_clear_count_high; 4657 /* cycle count - elapsed time during measured period, in clock ticks */ 4658 uint32_t cycle_count_low; 4659 uint32_t cycle_count_high; 4660 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4661 uint32_t tx_cycle_count_low; 4662 uint32_t tx_cycle_count_high; 4663 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4664 uint32_t rx_cycle_count_low; 4665 uint32_t rx_cycle_count_high; 4666 /*rx_cycle cnt for my bss in 64bits format */ 4667 uint32_t rx_bss_cycle_count_low; 4668 uint32_t rx_bss_cycle_count_high; 4669 uint32_t pdev_id; 4670 } __packed; 4671 4672 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4673 4674 struct wmi_vdev_install_key_compl_event { 4675 uint32_t vdev_id; 4676 struct wmi_mac_addr peer_macaddr; 4677 uint32_t key_idx; 4678 uint32_t key_flags; 4679 uint32_t status; 4680 } __packed; 4681 4682 struct wmi_vdev_install_key_complete_arg { 4683 uint32_t vdev_id; 4684 const uint8_t *macaddr; 4685 uint32_t key_idx; 4686 uint32_t key_flags; 4687 uint32_t status; 4688 }; 4689 4690 struct wmi_peer_assoc_conf_event { 4691 uint32_t vdev_id; 4692 struct wmi_mac_addr peer_macaddr; 4693 } __packed; 4694 4695 struct wmi_peer_assoc_conf_arg { 4696 uint32_t vdev_id; 4697 const uint8_t *macaddr; 4698 }; 4699 4700 struct wmi_fils_discovery_event { 4701 uint32_t vdev_id; 4702 uint32_t fils_tt; 4703 uint32_t tbtt; 4704 } __packed; 4705 4706 struct wmi_probe_resp_tx_status_event { 4707 uint32_t vdev_id; 4708 uint32_t tx_status; 4709 } __packed; 4710 4711 /* 4712 * PDEV statistics 4713 */ 4714 struct wmi_pdev_stats_base { 4715 int32_t chan_nf; 4716 uint32_t tx_frame_count; /* Cycles spent transmitting frames */ 4717 uint32_t rx_frame_count; /* Cycles spent receiving frames */ 4718 uint32_t rx_clear_count; /* Total channel busy time, evidently */ 4719 uint32_t cycle_count; /* Total on-channel time */ 4720 uint32_t phy_err_count; 4721 uint32_t chan_tx_pwr; 4722 } __packed; 4723 4724 struct wmi_pdev_stats_extra { 4725 uint32_t ack_rx_bad; 4726 uint32_t rts_bad; 4727 uint32_t rts_good; 4728 uint32_t fcs_bad; 4729 uint32_t no_beacons; 4730 uint32_t mib_int_count; 4731 } __packed; 4732 4733 struct wmi_pdev_stats_tx { 4734 /* Num HTT cookies queued to dispatch list */ 4735 int32_t comp_queued; 4736 4737 /* Num HTT cookies dispatched */ 4738 int32_t comp_delivered; 4739 4740 /* Num MSDU queued to WAL */ 4741 int32_t msdu_enqued; 4742 4743 /* Num MPDU queue to WAL */ 4744 int32_t mpdu_enqued; 4745 4746 /* Num MSDUs dropped by WMM limit */ 4747 int32_t wmm_drop; 4748 4749 /* Num Local frames queued */ 4750 int32_t local_enqued; 4751 4752 /* Num Local frames done */ 4753 int32_t local_freed; 4754 4755 /* Num queued to HW */ 4756 int32_t hw_queued; 4757 4758 /* Num PPDU reaped from HW */ 4759 int32_t hw_reaped; 4760 4761 /* Num underruns */ 4762 int32_t underrun; 4763 4764 /* Num hw paused */ 4765 uint32_t hw_paused; 4766 4767 /* Num PPDUs cleaned up in TX abort */ 4768 int32_t tx_abort; 4769 4770 /* Num MPDUs requeued by SW */ 4771 int32_t mpdus_requeued; 4772 4773 /* excessive retries */ 4774 uint32_t tx_ko; 4775 4776 uint32_t tx_xretry; 4777 4778 /* data hw rate code */ 4779 uint32_t data_rc; 4780 4781 /* Scheduler self triggers */ 4782 uint32_t self_triggers; 4783 4784 /* frames dropped due to excessive sw retries */ 4785 uint32_t sw_retry_failure; 4786 4787 /* illegal rate phy errors */ 4788 uint32_t illgl_rate_phy_err; 4789 4790 /* wal pdev continuous xretry */ 4791 uint32_t pdev_cont_xretry; 4792 4793 /* wal pdev tx timeouts */ 4794 uint32_t pdev_tx_timeout; 4795 4796 /* wal pdev resets */ 4797 uint32_t pdev_resets; 4798 4799 /* frames dropped due to non-availability of stateless TIDs */ 4800 uint32_t stateless_tid_alloc_failure; 4801 4802 /* PhY/BB underrun */ 4803 uint32_t phy_underrun; 4804 4805 /* MPDU is more than txop limit */ 4806 uint32_t txop_ovf; 4807 4808 /* Num sequences posted */ 4809 uint32_t seq_posted; 4810 4811 /* Num sequences failed in queueing */ 4812 uint32_t seq_failed_queueing; 4813 4814 /* Num sequences completed */ 4815 uint32_t seq_completed; 4816 4817 /* Num sequences restarted */ 4818 uint32_t seq_restarted; 4819 4820 /* Num of MU sequences posted */ 4821 uint32_t mu_seq_posted; 4822 4823 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4824 * (Reset,channel change) 4825 */ 4826 int32_t mpdus_sw_flush; 4827 4828 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4829 int32_t mpdus_hw_filter; 4830 4831 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4832 * PPDU_duration based on rate, dyn_bw) 4833 */ 4834 int32_t mpdus_truncated; 4835 4836 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4837 int32_t mpdus_ack_failed; 4838 4839 /* Num MPDUs that was dropped du to expiry. */ 4840 int32_t mpdus_expired; 4841 } __packed; 4842 4843 struct wmi_pdev_stats_rx { 4844 /* Cnts any change in ring routing mid-ppdu */ 4845 int32_t mid_ppdu_route_change; 4846 4847 /* Total number of statuses processed */ 4848 int32_t status_rcvd; 4849 4850 /* Extra frags on rings 0-3 */ 4851 int32_t r0_frags; 4852 int32_t r1_frags; 4853 int32_t r2_frags; 4854 int32_t r3_frags; 4855 4856 /* MSDUs / MPDUs delivered to HTT */ 4857 int32_t htt_msdus; 4858 int32_t htt_mpdus; 4859 4860 /* MSDUs / MPDUs delivered to local stack */ 4861 int32_t loc_msdus; 4862 int32_t loc_mpdus; 4863 4864 /* AMSDUs that have more MSDUs than the status ring size */ 4865 int32_t oversize_amsdu; 4866 4867 /* Number of PHY errors */ 4868 int32_t phy_errs; 4869 4870 /* Number of PHY errors drops */ 4871 int32_t phy_err_drop; 4872 4873 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4874 int32_t mpdu_errs; 4875 4876 /* Num overflow errors */ 4877 int32_t rx_ovfl_errs; 4878 } __packed; 4879 4880 struct wmi_pdev_stats { 4881 struct wmi_pdev_stats_base base; 4882 struct wmi_pdev_stats_tx tx; 4883 struct wmi_pdev_stats_rx rx; 4884 } __packed; 4885 4886 #define WLAN_MAX_AC 4 4887 #define MAX_TX_RATE_VALUES 10 4888 #define MAX_TX_RATE_VALUES 10 4889 4890 struct wmi_vdev_stats { 4891 uint32_t vdev_id; 4892 uint32_t beacon_snr; 4893 uint32_t data_snr; 4894 uint32_t num_tx_frames[WLAN_MAX_AC]; 4895 uint32_t num_rx_frames; 4896 uint32_t num_tx_frames_retries[WLAN_MAX_AC]; 4897 uint32_t num_tx_frames_failures[WLAN_MAX_AC]; 4898 uint32_t num_rts_fail; 4899 uint32_t num_rts_success; 4900 uint32_t num_rx_err; 4901 uint32_t num_rx_discard; 4902 uint32_t num_tx_not_acked; 4903 uint32_t tx_rate_history[MAX_TX_RATE_VALUES]; 4904 uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES]; 4905 } __packed; 4906 4907 struct wmi_bcn_stats { 4908 uint32_t vdev_id; 4909 uint32_t tx_bcn_succ_cnt; 4910 uint32_t tx_bcn_outage_cnt; 4911 } __packed; 4912 4913 struct wmi_stats_event { 4914 uint32_t stats_id; 4915 uint32_t num_pdev_stats; 4916 uint32_t num_vdev_stats; 4917 uint32_t num_peer_stats; 4918 uint32_t num_bcnflt_stats; 4919 uint32_t num_chan_stats; 4920 uint32_t num_mib_stats; 4921 uint32_t pdev_id; 4922 uint32_t num_bcn_stats; 4923 uint32_t num_peer_extd_stats; 4924 uint32_t num_peer_extd2_stats; 4925 } __packed; 4926 4927 struct wmi_rssi_stats { 4928 uint32_t vdev_id; 4929 uint32_t rssi_avg_beacon[WMI_MAX_CHAINS]; 4930 uint32_t rssi_avg_data[WMI_MAX_CHAINS]; 4931 struct wmi_mac_addr peer_macaddr; 4932 } __packed; 4933 4934 struct wmi_per_chain_rssi_stats { 4935 uint32_t num_per_chain_rssi_stats; 4936 } __packed; 4937 4938 struct wmi_pdev_ctl_failsafe_chk_event { 4939 uint32_t pdev_id; 4940 uint32_t ctl_failsafe_status; 4941 } __packed; 4942 4943 struct wmi_pdev_csa_switch_ev { 4944 uint32_t pdev_id; 4945 uint32_t current_switch_count; 4946 uint32_t num_vdevs; 4947 } __packed; 4948 4949 struct wmi_pdev_radar_ev { 4950 uint32_t pdev_id; 4951 uint32_t detection_mode; 4952 uint32_t chan_freq; 4953 uint32_t chan_width; 4954 uint32_t detector_id; 4955 uint32_t segment_id; 4956 uint32_t timestamp; 4957 uint32_t is_chirp; 4958 int32_t freq_offset; 4959 int32_t sidx; 4960 } __packed; 4961 4962 struct wmi_pdev_temperature_event { 4963 /* temperature value in Celsius degree */ 4964 int32_t temp; 4965 uint32_t pdev_id; 4966 } __packed; 4967 4968 #define WMI_RX_STATUS_OK 0x00 4969 #define WMI_RX_STATUS_ERR_CRC 0x01 4970 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4971 #define WMI_RX_STATUS_ERR_MIC 0x10 4972 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4973 4974 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4975 4976 struct mgmt_rx_event_params { 4977 uint32_t chan_freq; 4978 uint32_t channel; 4979 uint32_t snr; 4980 uint8_t rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4981 uint32_t rate; 4982 enum wmi_phy_mode phy_mode; 4983 uint32_t buf_len; 4984 int status; 4985 uint32_t flags; 4986 int rssi; 4987 uint32_t tsf_delta; 4988 uint8_t pdev_id; 4989 }; 4990 4991 #define ATH_MAX_ANTENNA 4 4992 4993 struct wmi_mgmt_rx_hdr { 4994 uint32_t channel; 4995 uint32_t snr; 4996 uint32_t rate; 4997 uint32_t phy_mode; 4998 uint32_t buf_len; 4999 uint32_t status; 5000 uint32_t rssi_ctl[ATH_MAX_ANTENNA]; 5001 uint32_t flags; 5002 int rssi; 5003 uint32_t tsf_delta; 5004 uint32_t rx_tsf_l32; 5005 uint32_t rx_tsf_u32; 5006 uint32_t pdev_id; 5007 uint32_t chan_freq; 5008 } __packed; 5009 5010 #define MAX_ANTENNA_EIGHT 8 5011 5012 struct wmi_rssi_ctl_ext { 5013 uint32_t tlv_header; 5014 uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 5015 }; 5016 5017 struct wmi_mgmt_tx_compl_event { 5018 uint32_t desc_id; 5019 uint32_t status; 5020 uint32_t pdev_id; 5021 uint32_t ppdu_id; 5022 uint32_t ack_rssi; 5023 } __packed; 5024 5025 struct wmi_scan_event { 5026 uint32_t event_type; /* %WMI_SCAN_EVENT_ */ 5027 uint32_t reason; /* %WMI_SCAN_REASON_ */ 5028 uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 5029 uint32_t scan_req_id; 5030 uint32_t scan_id; 5031 uint32_t vdev_id; 5032 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 5033 * In case of AP it is TSF of the AP vdev 5034 * In case of STA connected state, this is the TSF of the AP 5035 * In case of STA not connected, it will be the free running HW timer 5036 */ 5037 uint32_t tsf_timestamp; 5038 } __packed; 5039 5040 struct wmi_peer_sta_kickout_arg { 5041 const uint8_t *mac_addr; 5042 }; 5043 5044 struct wmi_peer_sta_kickout_event { 5045 struct wmi_mac_addr peer_macaddr; 5046 } __packed; 5047 5048 enum wmi_roam_reason { 5049 WMI_ROAM_REASON_BETTER_AP = 1, 5050 WMI_ROAM_REASON_BEACON_MISS = 2, 5051 WMI_ROAM_REASON_LOW_RSSI = 3, 5052 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 5053 WMI_ROAM_REASON_HO_FAILED = 5, 5054 5055 /* keep last */ 5056 WMI_ROAM_REASON_MAX, 5057 }; 5058 5059 struct wmi_roam_event { 5060 uint32_t vdev_id; 5061 uint32_t reason; 5062 uint32_t rssi; 5063 } __packed; 5064 5065 #define WMI_CHAN_INFO_START_RESP 0 5066 #define WMI_CHAN_INFO_END_RESP 1 5067 5068 struct wmi_chan_info_event { 5069 uint32_t err_code; 5070 uint32_t freq; 5071 uint32_t cmd_flags; 5072 uint32_t noise_floor; 5073 uint32_t rx_clear_count; 5074 uint32_t cycle_count; 5075 uint32_t chan_tx_pwr_range; 5076 uint32_t chan_tx_pwr_tp; 5077 uint32_t rx_frame_count; 5078 uint32_t my_bss_rx_cycle_count; 5079 uint32_t rx_11b_mode_data_duration; 5080 uint32_t tx_frame_cnt; 5081 uint32_t mac_clk_mhz; 5082 uint32_t vdev_id; 5083 } __packed; 5084 5085 struct ath12k_targ_cap { 5086 uint32_t phy_capability; 5087 uint32_t max_frag_entry; 5088 uint32_t num_rf_chains; 5089 uint32_t ht_cap_info; 5090 uint32_t vht_cap_info; 5091 uint32_t vht_supp_mcs; 5092 uint32_t hw_min_tx_power; 5093 uint32_t hw_max_tx_power; 5094 uint32_t sys_cap_info; 5095 uint32_t min_pkt_size_enable; 5096 uint32_t max_bcn_ie_size; 5097 uint32_t max_num_scan_channels; 5098 uint32_t max_supported_macs; 5099 uint32_t wmi_fw_sub_feat_caps; 5100 uint32_t txrx_chainmask; 5101 uint32_t default_dbs_hw_mode_index; 5102 uint32_t num_msdu_desc; 5103 }; 5104 5105 enum wmi_vdev_type { 5106 WMI_VDEV_TYPE_AP = 1, 5107 WMI_VDEV_TYPE_STA = 2, 5108 WMI_VDEV_TYPE_IBSS = 3, 5109 WMI_VDEV_TYPE_MONITOR = 4, 5110 }; 5111 5112 enum wmi_vdev_subtype { 5113 WMI_VDEV_SUBTYPE_NONE, 5114 WMI_VDEV_SUBTYPE_P2P_DEVICE, 5115 WMI_VDEV_SUBTYPE_P2P_CLIENT, 5116 WMI_VDEV_SUBTYPE_P2P_GO, 5117 WMI_VDEV_SUBTYPE_PROXY_STA, 5118 WMI_VDEV_SUBTYPE_MESH_NON_11S, 5119 WMI_VDEV_SUBTYPE_MESH_11S, 5120 }; 5121 5122 enum wmi_sta_powersave_param { 5123 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 5124 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 5125 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 5126 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 5127 WMI_STA_PS_PARAM_UAPSD = 4, 5128 }; 5129 5130 #define WMI_UAPSD_AC_TYPE_DELI 0 5131 #define WMI_UAPSD_AC_TYPE_TRIG 1 5132 5133 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 5134 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 5135 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 5136 5137 enum wmi_sta_ps_param_uapsd { 5138 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5139 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5140 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5141 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5142 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5143 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5144 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5145 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5146 }; 5147 5148 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 5149 5150 struct wmi_sta_uapsd_auto_trig_param { 5151 uint32_t wmm_ac; 5152 uint32_t user_priority; 5153 uint32_t service_interval; 5154 uint32_t suspend_interval; 5155 uint32_t delay_interval; 5156 }; 5157 5158 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 5159 uint32_t vdev_id; 5160 struct wmi_mac_addr peer_macaddr; 5161 uint32_t num_ac; 5162 }; 5163 5164 struct wmi_sta_uapsd_auto_trig_arg { 5165 uint32_t wmm_ac; 5166 uint32_t user_priority; 5167 uint32_t service_interval; 5168 uint32_t suspend_interval; 5169 uint32_t delay_interval; 5170 }; 5171 5172 enum wmi_sta_ps_param_tx_wake_threshold { 5173 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 5174 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 5175 5176 /* Values greater than one indicate that many TX attempts per beacon 5177 * interval before the STA will wake up 5178 */ 5179 }; 5180 5181 /* The maximum number of PS-Poll frames the FW will send in response to 5182 * traffic advertised in TIM before waking up (by sending a null frame with PS 5183 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 5184 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 5185 * parameter is used when the RX wake policy is 5186 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 5187 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 5188 */ 5189 enum wmi_sta_ps_param_pspoll_count { 5190 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 5191 /* Values greater than 0 indicate the maximum number of PS-Poll frames 5192 * FW will send before waking up. 5193 */ 5194 }; 5195 5196 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 5197 enum wmi_ap_ps_param_uapsd { 5198 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5199 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5200 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5201 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5202 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5203 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5204 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5205 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5206 }; 5207 5208 /* U-APSD maximum service period of peer station */ 5209 enum wmi_ap_ps_peer_param_max_sp { 5210 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 5211 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 5212 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 5213 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 5214 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 5215 }; 5216 5217 enum wmi_ap_ps_peer_param { 5218 /** Set uapsd configuration for a given peer. 5219 * 5220 * This include the delivery and trigger enabled state for each AC. 5221 * The host MLME needs to set this based on AP capability and stations 5222 * request Set in the association request received from the station. 5223 * 5224 * Lower 8 bits of the value specify the UAPSD configuration. 5225 * 5226 * (see enum wmi_ap_ps_param_uapsd) 5227 * The default value is 0. 5228 */ 5229 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 5230 5231 /** 5232 * Set the service period for a UAPSD capable station 5233 * 5234 * The service period from wme ie in the (re)assoc request frame. 5235 * 5236 * (see enum wmi_ap_ps_peer_param_max_sp) 5237 */ 5238 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 5239 5240 /** Time in seconds for aging out buffered frames 5241 * for STA in power save 5242 */ 5243 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 5244 5245 /** Specify frame types that are considered SIFS 5246 * RESP trigger frame 5247 */ 5248 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 5249 5250 /** Specifies the trigger state of TID. 5251 * Valid only for UAPSD frame type 5252 */ 5253 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 5254 5255 /* Specifies the WNM sleep state of a STA */ 5256 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 5257 }; 5258 5259 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 5260 5261 #define WMI_MAX_KEY_INDEX 3 5262 #define WMI_MAX_KEY_LEN 32 5263 5264 #define WMI_KEY_PAIRWISE 0x00 5265 #define WMI_KEY_GROUP 0x01 5266 5267 #define WMI_CIPHER_NONE 0x0 /* clear key */ 5268 #define WMI_CIPHER_WEP 0x1 5269 #define WMI_CIPHER_TKIP 0x2 5270 #define WMI_CIPHER_AES_OCB 0x3 5271 #define WMI_CIPHER_AES_CCM 0x4 5272 #define WMI_CIPHER_WAPI 0x5 5273 #define WMI_CIPHER_CKIP 0x6 5274 #define WMI_CIPHER_AES_CMAC 0x7 5275 #define WMI_CIPHER_ANY 0x8 5276 #define WMI_CIPHER_AES_GCM 0x9 5277 #define WMI_CIPHER_AES_GMAC 0xa 5278 5279 /* Value to disable fixed rate setting */ 5280 #define WMI_FIXED_RATE_NONE (0xffff) 5281 5282 #define ATH12K_RC_VERSION_OFFSET 28 5283 #define ATH12K_RC_PREAMBLE_OFFSET 8 5284 #define ATH12K_RC_NSS_OFFSET 5 5285 5286 #define ATH12K_HW_RATE_CODE(rate, nss, preamble) \ 5287 ((1 << ATH12K_RC_VERSION_OFFSET) | \ 5288 ((nss) << ATH12K_RC_NSS_OFFSET) | \ 5289 ((preamble) << ATH12K_RC_PREAMBLE_OFFSET) | \ 5290 (rate)) 5291 5292 /* Preamble types to be used with VDEV fixed rate configuration */ 5293 enum wmi_rate_preamble { 5294 WMI_RATE_PREAMBLE_OFDM, 5295 WMI_RATE_PREAMBLE_CCK, 5296 WMI_RATE_PREAMBLE_HT, 5297 WMI_RATE_PREAMBLE_VHT, 5298 WMI_RATE_PREAMBLE_HE, 5299 }; 5300 5301 /** 5302 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 5303 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 5304 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 5305 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 5306 */ 5307 enum wmi_rtscts_prot_mode { 5308 WMI_RTS_CTS_DISABLED = 0, 5309 WMI_USE_RTS_CTS = 1, 5310 WMI_USE_CTS2SELF = 2, 5311 }; 5312 5313 /** 5314 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 5315 * protection mode. 5316 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 5317 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 5318 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 5319 * but if there's a sw retry, both the rate 5320 * series will use RTS-CTS. 5321 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 5322 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 5323 */ 5324 enum wmi_rtscts_profile { 5325 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5326 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5327 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5328 WMI_RTSCTS_ERP = 3, 5329 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5330 }; 5331 5332 struct ath12k_hal_reg_cap { 5333 uint32_t eeprom_rd; 5334 uint32_t eeprom_rd_ext; 5335 uint32_t regcap1; 5336 uint32_t regcap2; 5337 uint32_t wireless_modes; 5338 uint32_t low_2ghz_chan; 5339 uint32_t high_2ghz_chan; 5340 uint32_t low_5ghz_chan; 5341 uint32_t high_5ghz_chan; 5342 }; 5343 5344 struct ath12k_mem_chunk { 5345 void *vaddr; 5346 bus_addr_t paddr; 5347 uint32_t len; 5348 uint32_t req_id; 5349 }; 5350 5351 enum wmi_sta_ps_param_rx_wake_policy { 5352 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5353 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5354 }; 5355 5356 /* Do not change existing values! Used by ath12k_frame_mode parameter 5357 * module parameter. 5358 */ 5359 enum ath12k_hw_txrx_mode { 5360 ATH12K_HW_TXRX_RAW = 0, 5361 ATH12K_HW_TXRX_NATIVE_WIFI = 1, 5362 ATH12K_HW_TXRX_ETHERNET = 2, 5363 }; 5364 5365 struct wmi_wmm_params { 5366 uint32_t tlv_header; 5367 uint32_t cwmin; 5368 uint32_t cwmax; 5369 uint32_t aifs; 5370 uint32_t txoplimit; 5371 uint32_t acm; 5372 uint32_t no_ack; 5373 } __packed; 5374 5375 struct wmi_wmm_params_arg { 5376 uint8_t acm; 5377 uint8_t aifs; 5378 uint16_t cwmin; 5379 uint16_t cwmax; 5380 uint16_t txop; 5381 uint8_t no_ack; 5382 }; 5383 5384 struct wmi_vdev_set_wmm_params_cmd { 5385 uint32_t tlv_header; 5386 uint32_t vdev_id; 5387 struct wmi_wmm_params wmm_params[4]; 5388 uint32_t wmm_param_type; 5389 } __packed; 5390 5391 struct wmi_wmm_params_all_arg { 5392 struct wmi_wmm_params_arg ac_be; 5393 struct wmi_wmm_params_arg ac_bk; 5394 struct wmi_wmm_params_arg ac_vi; 5395 struct wmi_wmm_params_arg ac_vo; 5396 }; 5397 5398 #define ATH12K_TWT_DEF_STA_CONG_TIMER_MS 5000 5399 #define ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5400 #define ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5401 #define ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5402 #define ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5403 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5404 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5405 #define ATH12K_TWT_DEF_MIN_NO_STA_SETUP 10 5406 #define ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5407 #define ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5408 #define ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5409 #define ATH12K_TWT_DEF_MAX_NO_STA_TWT 500 5410 #define ATH12K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5411 #define ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5412 #define ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5413 5414 struct wmi_twt_enable_params { 5415 uint32_t sta_cong_timer_ms; 5416 uint32_t mbss_support; 5417 uint32_t default_slot_size; 5418 uint32_t congestion_thresh_setup; 5419 uint32_t congestion_thresh_teardown; 5420 uint32_t congestion_thresh_critical; 5421 uint32_t interference_thresh_teardown; 5422 uint32_t interference_thresh_setup; 5423 uint32_t min_no_sta_setup; 5424 uint32_t min_no_sta_teardown; 5425 uint32_t no_of_bcast_mcast_slots; 5426 uint32_t min_no_twt_slots; 5427 uint32_t max_no_sta_twt; 5428 uint32_t mode_check_interval; 5429 uint32_t add_sta_slot_interval; 5430 uint32_t remove_sta_slot_interval; 5431 }; 5432 5433 struct wmi_twt_enable_params_cmd { 5434 uint32_t tlv_header; 5435 uint32_t pdev_id; 5436 uint32_t sta_cong_timer_ms; 5437 uint32_t mbss_support; 5438 uint32_t default_slot_size; 5439 uint32_t congestion_thresh_setup; 5440 uint32_t congestion_thresh_teardown; 5441 uint32_t congestion_thresh_critical; 5442 uint32_t interference_thresh_teardown; 5443 uint32_t interference_thresh_setup; 5444 uint32_t min_no_sta_setup; 5445 uint32_t min_no_sta_teardown; 5446 uint32_t no_of_bcast_mcast_slots; 5447 uint32_t min_no_twt_slots; 5448 uint32_t max_no_sta_twt; 5449 uint32_t mode_check_interval; 5450 uint32_t add_sta_slot_interval; 5451 uint32_t remove_sta_slot_interval; 5452 } __packed; 5453 5454 struct wmi_twt_disable_params_cmd { 5455 uint32_t tlv_header; 5456 uint32_t pdev_id; 5457 } __packed; 5458 5459 enum WMI_HOST_TWT_COMMAND { 5460 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 5461 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 5462 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 5463 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 5464 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 5465 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 5466 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 5467 WMI_HOST_TWT_COMMAND_REJECT_TWT, 5468 }; 5469 5470 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 5471 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 5472 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 5473 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 5474 5475 struct wmi_twt_add_dialog_params_cmd { 5476 uint32_t tlv_header; 5477 uint32_t vdev_id; 5478 struct wmi_mac_addr peer_macaddr; 5479 uint32_t dialog_id; 5480 uint32_t wake_intvl_us; 5481 uint32_t wake_intvl_mantis; 5482 uint32_t wake_dura_us; 5483 uint32_t sp_offset_us; 5484 uint32_t flags; 5485 } __packed; 5486 5487 struct wmi_twt_add_dialog_params { 5488 uint32_t vdev_id; 5489 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5490 uint32_t dialog_id; 5491 uint32_t wake_intvl_us; 5492 uint32_t wake_intvl_mantis; 5493 uint32_t wake_dura_us; 5494 uint32_t sp_offset_us; 5495 uint8_t twt_cmd; 5496 uint8_t flag_bcast; 5497 uint8_t flag_trigger; 5498 uint8_t flag_flow_type; 5499 uint8_t flag_protection; 5500 } __packed; 5501 5502 enum wmi_twt_add_dialog_status { 5503 WMI_ADD_TWT_STATUS_OK, 5504 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5505 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5506 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5507 WMI_ADD_TWT_STATUS_NOT_READY, 5508 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5509 WMI_ADD_TWT_STATUS_NO_ACK, 5510 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5511 WMI_ADD_TWT_STATUS_DENIED, 5512 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5513 }; 5514 5515 struct wmi_twt_add_dialog_event { 5516 uint32_t vdev_id; 5517 struct wmi_mac_addr peer_macaddr; 5518 uint32_t dialog_id; 5519 uint32_t status; 5520 } __packed; 5521 5522 struct wmi_twt_del_dialog_params { 5523 uint32_t vdev_id; 5524 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5525 uint32_t dialog_id; 5526 } __packed; 5527 5528 struct wmi_twt_del_dialog_params_cmd { 5529 uint32_t tlv_header; 5530 uint32_t vdev_id; 5531 struct wmi_mac_addr peer_macaddr; 5532 uint32_t dialog_id; 5533 } __packed; 5534 5535 struct wmi_twt_pause_dialog_params { 5536 uint32_t vdev_id; 5537 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5538 uint32_t dialog_id; 5539 } __packed; 5540 5541 struct wmi_twt_pause_dialog_params_cmd { 5542 uint32_t tlv_header; 5543 uint32_t vdev_id; 5544 struct wmi_mac_addr peer_macaddr; 5545 uint32_t dialog_id; 5546 } __packed; 5547 5548 struct wmi_twt_resume_dialog_params { 5549 uint32_t vdev_id; 5550 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5551 uint32_t dialog_id; 5552 uint32_t sp_offset_us; 5553 uint32_t next_twt_size; 5554 } __packed; 5555 5556 struct wmi_twt_resume_dialog_params_cmd { 5557 uint32_t tlv_header; 5558 uint32_t vdev_id; 5559 struct wmi_mac_addr peer_macaddr; 5560 uint32_t dialog_id; 5561 uint32_t sp_offset_us; 5562 uint32_t next_twt_size; 5563 } __packed; 5564 5565 struct wmi_obss_spatial_reuse_params_cmd { 5566 uint32_t tlv_header; 5567 uint32_t pdev_id; 5568 uint32_t enable; 5569 int32_t obss_min; 5570 int32_t obss_max; 5571 uint32_t vdev_id; 5572 } __packed; 5573 5574 struct wmi_pdev_obss_pd_bitmap_cmd { 5575 uint32_t tlv_header; 5576 uint32_t pdev_id; 5577 uint32_t bitmap[2]; 5578 } __packed; 5579 5580 #define ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5581 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5582 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION 1 5583 5584 #define ATH12K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5585 #define ATH12K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5586 5587 enum wmi_bss_color_collision { 5588 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5589 WMI_BSS_COLOR_COLLISION_DETECTION, 5590 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5591 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5592 }; 5593 5594 struct wmi_obss_color_collision_cfg_params_cmd { 5595 uint32_t tlv_header; 5596 uint32_t vdev_id; 5597 uint32_t flags; 5598 uint32_t evt_type; 5599 uint32_t current_bss_color; 5600 uint32_t detection_period_ms; 5601 uint32_t scan_period_ms; 5602 uint32_t free_slot_expiry_time_ms; 5603 } __packed; 5604 5605 struct wmi_bss_color_change_enable_params_cmd { 5606 uint32_t tlv_header; 5607 uint32_t vdev_id; 5608 uint32_t enable; 5609 } __packed; 5610 5611 struct wmi_obss_color_collision_event { 5612 uint32_t vdev_id; 5613 uint32_t evt_type; 5614 uint64_t obss_color_bitmap; 5615 } __packed; 5616 5617 #define ATH12K_IPV4_TH_SEED_SIZE 5 5618 #define ATH12K_IPV6_TH_SEED_SIZE 11 5619 5620 struct ath12k_wmi_pdev_lro_config_cmd { 5621 uint32_t tlv_header; 5622 uint32_t lro_enable; 5623 uint32_t res; 5624 uint32_t th_4[ATH12K_IPV4_TH_SEED_SIZE]; 5625 uint32_t th_6[ATH12K_IPV6_TH_SEED_SIZE]; 5626 uint32_t pdev_id; 5627 } __packed; 5628 5629 #define ATH12K_WMI_SPECTRAL_COUNT_DEFAULT 0 5630 #define ATH12K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5631 #define ATH12K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5632 #define ATH12K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5633 #define ATH12K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5634 #define ATH12K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5635 #define ATH12K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5636 #define ATH12K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5637 #define ATH12K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5638 #define ATH12K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5639 #define ATH12K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5640 #define ATH12K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5641 #define ATH12K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5642 #define ATH12K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5643 #define ATH12K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5644 #define ATH12K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5645 #define ATH12K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5646 #define ATH12K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5647 5648 struct ath12k_wmi_vdev_spectral_conf_param { 5649 uint32_t vdev_id; 5650 uint32_t scan_count; 5651 uint32_t scan_period; 5652 uint32_t scan_priority; 5653 uint32_t scan_fft_size; 5654 uint32_t scan_gc_ena; 5655 uint32_t scan_restart_ena; 5656 uint32_t scan_noise_floor_ref; 5657 uint32_t scan_init_delay; 5658 uint32_t scan_nb_tone_thr; 5659 uint32_t scan_str_bin_thr; 5660 uint32_t scan_wb_rpt_mode; 5661 uint32_t scan_rssi_rpt_mode; 5662 uint32_t scan_rssi_thr; 5663 uint32_t scan_pwr_format; 5664 uint32_t scan_rpt_mode; 5665 uint32_t scan_bin_scale; 5666 uint32_t scan_dbm_adj; 5667 uint32_t scan_chn_mask; 5668 } __packed; 5669 5670 struct ath12k_wmi_vdev_spectral_conf_cmd { 5671 uint32_t tlv_header; 5672 struct ath12k_wmi_vdev_spectral_conf_param param; 5673 } __packed; 5674 5675 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5676 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5677 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5678 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5679 5680 struct ath12k_wmi_vdev_spectral_enable_cmd { 5681 uint32_t tlv_header; 5682 uint32_t vdev_id; 5683 uint32_t trigger_cmd; 5684 uint32_t enable_cmd; 5685 } __packed; 5686 5687 struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd { 5688 uint32_t tlv_header; 5689 uint32_t pdev_id; 5690 uint32_t module_id; /* see enum wmi_direct_buffer_module */ 5691 uint32_t base_paddr_lo; 5692 uint32_t base_paddr_hi; 5693 uint32_t head_idx_paddr_lo; 5694 uint32_t head_idx_paddr_hi; 5695 uint32_t tail_idx_paddr_lo; 5696 uint32_t tail_idx_paddr_hi; 5697 uint32_t num_elems; /* Number of elems in the ring */ 5698 uint32_t buf_size; /* size of allocated buffer in bytes */ 5699 5700 /* Number of wmi_dma_buf_release_entry packed together */ 5701 uint32_t num_resp_per_event; 5702 5703 /* Target should timeout and send whatever resp 5704 * it has if this time expires, units in milliseconds 5705 */ 5706 uint32_t event_timeout_ms; 5707 } __packed; 5708 5709 struct ath12k_wmi_dma_buf_release_fixed_param { 5710 uint32_t pdev_id; 5711 uint32_t module_id; 5712 uint32_t num_buf_release_entry; 5713 uint32_t num_meta_data_entry; 5714 } __packed; 5715 5716 struct wmi_dma_buf_release_entry { 5717 uint32_t tlv_header; 5718 uint32_t paddr_lo; 5719 5720 /* Bits 11:0: address of data 5721 * Bits 31:12: host context data 5722 */ 5723 uint32_t paddr_hi; 5724 } __packed; 5725 5726 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5727 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5728 5729 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5730 5731 struct wmi_dma_buf_release_meta_data { 5732 uint32_t tlv_header; 5733 int32_t noise_floor[WMI_MAX_CHAINS]; 5734 uint32_t reset_delay; 5735 uint32_t freq1; 5736 uint32_t freq2; 5737 uint32_t ch_width; 5738 } __packed; 5739 5740 enum wmi_fils_discovery_cmd_type { 5741 WMI_FILS_DISCOVERY_CMD, 5742 WMI_UNSOL_BCAST_PROBE_RESP, 5743 }; 5744 5745 struct wmi_fils_discovery_cmd { 5746 uint32_t tlv_header; 5747 uint32_t vdev_id; 5748 uint32_t interval; 5749 uint32_t config; /* enum wmi_fils_discovery_cmd_type */ 5750 } __packed; 5751 5752 struct wmi_fils_discovery_tmpl_cmd { 5753 uint32_t tlv_header; 5754 uint32_t vdev_id; 5755 uint32_t buf_len; 5756 } __packed; 5757 5758 struct wmi_probe_tmpl_cmd { 5759 uint32_t tlv_header; 5760 uint32_t vdev_id; 5761 uint32_t buf_len; 5762 } __packed; 5763 5764 struct target_resource_config { 5765 uint32_t num_vdevs; 5766 uint32_t num_peers; 5767 uint32_t num_active_peers; 5768 uint32_t num_offload_peers; 5769 uint32_t num_offload_reorder_buffs; 5770 uint32_t num_peer_keys; 5771 uint32_t num_tids; 5772 uint32_t ast_skid_limit; 5773 uint32_t tx_chain_mask; 5774 uint32_t rx_chain_mask; 5775 uint32_t rx_timeout_pri[4]; 5776 uint32_t rx_decap_mode; 5777 uint32_t scan_max_pending_req; 5778 uint32_t bmiss_offload_max_vdev; 5779 uint32_t roam_offload_max_vdev; 5780 uint32_t roam_offload_max_ap_profiles; 5781 uint32_t num_mcast_groups; 5782 uint32_t num_mcast_table_elems; 5783 uint32_t mcast2ucast_mode; 5784 uint32_t tx_dbg_log_size; 5785 uint32_t num_wds_entries; 5786 uint32_t dma_burst_size; 5787 uint32_t mac_aggr_delim; 5788 uint32_t rx_skip_defrag_timeout_dup_detection_check; 5789 uint32_t vow_config; 5790 uint32_t gtk_offload_max_vdev; 5791 uint32_t num_msdu_desc; 5792 uint32_t max_frag_entries; 5793 uint32_t max_peer_ext_stats; 5794 uint32_t smart_ant_cap; 5795 uint32_t bk_minfree; 5796 uint32_t be_minfree; 5797 uint32_t vi_minfree; 5798 uint32_t vo_minfree; 5799 uint32_t rx_batchmode; 5800 uint32_t tt_support; 5801 uint32_t flag1; 5802 uint32_t iphdr_pad_config; 5803 uint32_t qwrap_config:16, 5804 alloc_frag_desc_for_data_pkt:16; 5805 uint32_t num_tdls_vdevs; 5806 uint32_t num_tdls_conn_table_entries; 5807 uint32_t beacon_tx_offload_max_vdev; 5808 uint32_t num_multicast_filter_entries; 5809 uint32_t num_wow_filters; 5810 uint32_t num_keep_alive_pattern; 5811 uint32_t keep_alive_pattern_size; 5812 uint32_t max_tdls_concurrent_sleep_sta; 5813 uint32_t max_tdls_concurrent_buffer_sta; 5814 uint32_t wmi_send_separate; 5815 uint32_t num_ocb_vdevs; 5816 uint32_t num_ocb_channels; 5817 uint32_t num_ocb_schedules; 5818 uint32_t num_ns_ext_tuples_cfg; 5819 uint32_t bpf_instruction_size; 5820 uint32_t max_bssid_rx_filters; 5821 uint32_t use_pdev_id; 5822 uint32_t peer_map_unmap_support; 5823 uint32_t sched_params; 5824 uint32_t twt_ap_pdev_count; 5825 uint32_t twt_ap_sta_count; 5826 uint8_t is_reg_cc_ext_event_supported; 5827 uint32_t ema_max_vap_cnt; 5828 uint32_t ema_max_profile_period; 5829 }; 5830 5831 enum wmi_debug_log_param { 5832 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5833 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5834 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5835 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5836 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5837 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5838 }; 5839 5840 struct wmi_debug_log_config_cmd_fixed_param { 5841 uint32_t tlv_header; 5842 uint32_t dbg_log_param; 5843 uint32_t value; 5844 } __packed; 5845 5846 #define WMI_MAX_MEM_REQS 32 5847 5848 #define MAX_RADIOS 3 5849 5850 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5851 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5852 5853 enum ath12k_wmi_peer_ps_state { 5854 WMI_PEER_PS_STATE_OFF, 5855 WMI_PEER_PS_STATE_ON, 5856 WMI_PEER_PS_STATE_DISABLED, 5857 }; 5858 5859 enum wmi_peer_ps_supported_bitmap { 5860 /* Used to indicate that power save state change is valid */ 5861 WMI_PEER_PS_VALID = 0x1, 5862 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5863 }; 5864 5865 struct wmi_peer_sta_ps_state_chg_event { 5866 struct wmi_mac_addr peer_macaddr; 5867 uint32_t peer_ps_state; 5868 uint32_t ps_supported_bitmap; 5869 uint32_t peer_ps_valid; 5870 uint32_t peer_ps_timestamp; 5871 } __packed; 5872 5873 /* Definition of HW data filtering */ 5874 enum hw_data_filter_type { 5875 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5876 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5877 }; 5878 5879 struct wmi_hw_data_filter_cmd { 5880 uint32_t tlv_header; 5881 uint32_t vdev_id; 5882 uint32_t enable; 5883 uint32_t hw_filter_bitmap; 5884 } __packed; 5885 5886 /* WOW structures */ 5887 enum wmi_wow_wakeup_event { 5888 WOW_BMISS_EVENT = 0, 5889 WOW_BETTER_AP_EVENT, 5890 WOW_DEAUTH_RECVD_EVENT, 5891 WOW_MAGIC_PKT_RECVD_EVENT, 5892 WOW_GTK_ERR_EVENT, 5893 WOW_FOURWAY_HSHAKE_EVENT, 5894 WOW_EAPOL_RECVD_EVENT, 5895 WOW_NLO_DETECTED_EVENT, 5896 WOW_DISASSOC_RECVD_EVENT, 5897 WOW_PATTERN_MATCH_EVENT, 5898 WOW_CSA_IE_EVENT, 5899 WOW_PROBE_REQ_WPS_IE_EVENT, 5900 WOW_AUTH_REQ_EVENT, 5901 WOW_ASSOC_REQ_EVENT, 5902 WOW_HTT_EVENT, 5903 WOW_RA_MATCH_EVENT, 5904 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5905 WOW_IOAC_MAGIC_EVENT, 5906 WOW_IOAC_SHORT_EVENT, 5907 WOW_IOAC_EXTEND_EVENT, 5908 WOW_IOAC_TIMER_EVENT, 5909 WOW_DFS_PHYERR_RADAR_EVENT, 5910 WOW_BEACON_EVENT, 5911 WOW_CLIENT_KICKOUT_EVENT, 5912 WOW_EVENT_MAX, 5913 }; 5914 5915 enum wmi_wow_interface_cfg { 5916 WOW_IFACE_PAUSE_ENABLED, 5917 WOW_IFACE_PAUSE_DISABLED 5918 }; 5919 5920 #define C2S(x) case x: return #x 5921 5922 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5923 { 5924 switch (ev) { 5925 C2S(WOW_BMISS_EVENT); 5926 C2S(WOW_BETTER_AP_EVENT); 5927 C2S(WOW_DEAUTH_RECVD_EVENT); 5928 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5929 C2S(WOW_GTK_ERR_EVENT); 5930 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5931 C2S(WOW_EAPOL_RECVD_EVENT); 5932 C2S(WOW_NLO_DETECTED_EVENT); 5933 C2S(WOW_DISASSOC_RECVD_EVENT); 5934 C2S(WOW_PATTERN_MATCH_EVENT); 5935 C2S(WOW_CSA_IE_EVENT); 5936 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5937 C2S(WOW_AUTH_REQ_EVENT); 5938 C2S(WOW_ASSOC_REQ_EVENT); 5939 C2S(WOW_HTT_EVENT); 5940 C2S(WOW_RA_MATCH_EVENT); 5941 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5942 C2S(WOW_IOAC_MAGIC_EVENT); 5943 C2S(WOW_IOAC_SHORT_EVENT); 5944 C2S(WOW_IOAC_EXTEND_EVENT); 5945 C2S(WOW_IOAC_TIMER_EVENT); 5946 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5947 C2S(WOW_BEACON_EVENT); 5948 C2S(WOW_CLIENT_KICKOUT_EVENT); 5949 C2S(WOW_EVENT_MAX); 5950 default: 5951 return NULL; 5952 } 5953 } 5954 5955 enum wmi_wow_wake_reason { 5956 WOW_REASON_UNSPECIFIED = -1, 5957 WOW_REASON_NLOD = 0, 5958 WOW_REASON_AP_ASSOC_LOST, 5959 WOW_REASON_LOW_RSSI, 5960 WOW_REASON_DEAUTH_RECVD, 5961 WOW_REASON_DISASSOC_RECVD, 5962 WOW_REASON_GTK_HS_ERR, 5963 WOW_REASON_EAP_REQ, 5964 WOW_REASON_FOURWAY_HS_RECV, 5965 WOW_REASON_TIMER_INTR_RECV, 5966 WOW_REASON_PATTERN_MATCH_FOUND, 5967 WOW_REASON_RECV_MAGIC_PATTERN, 5968 WOW_REASON_P2P_DISC, 5969 WOW_REASON_WLAN_HB, 5970 WOW_REASON_CSA_EVENT, 5971 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5972 WOW_REASON_AUTH_REQ_RECV, 5973 WOW_REASON_ASSOC_REQ_RECV, 5974 WOW_REASON_HTT_EVENT, 5975 WOW_REASON_RA_MATCH, 5976 WOW_REASON_HOST_AUTO_SHUTDOWN, 5977 WOW_REASON_IOAC_MAGIC_EVENT, 5978 WOW_REASON_IOAC_SHORT_EVENT, 5979 WOW_REASON_IOAC_EXTEND_EVENT, 5980 WOW_REASON_IOAC_TIMER_EVENT, 5981 WOW_REASON_ROAM_HO, 5982 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5983 WOW_REASON_BEACON_RECV, 5984 WOW_REASON_CLIENT_KICKOUT_EVENT, 5985 WOW_REASON_PAGE_FAULT = 0x3a, 5986 WOW_REASON_DEBUG_TEST = 0xFF, 5987 }; 5988 5989 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5990 { 5991 switch (reason) { 5992 C2S(WOW_REASON_UNSPECIFIED); 5993 C2S(WOW_REASON_NLOD); 5994 C2S(WOW_REASON_AP_ASSOC_LOST); 5995 C2S(WOW_REASON_LOW_RSSI); 5996 C2S(WOW_REASON_DEAUTH_RECVD); 5997 C2S(WOW_REASON_DISASSOC_RECVD); 5998 C2S(WOW_REASON_GTK_HS_ERR); 5999 C2S(WOW_REASON_EAP_REQ); 6000 C2S(WOW_REASON_FOURWAY_HS_RECV); 6001 C2S(WOW_REASON_TIMER_INTR_RECV); 6002 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 6003 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 6004 C2S(WOW_REASON_P2P_DISC); 6005 C2S(WOW_REASON_WLAN_HB); 6006 C2S(WOW_REASON_CSA_EVENT); 6007 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 6008 C2S(WOW_REASON_AUTH_REQ_RECV); 6009 C2S(WOW_REASON_ASSOC_REQ_RECV); 6010 C2S(WOW_REASON_HTT_EVENT); 6011 C2S(WOW_REASON_RA_MATCH); 6012 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 6013 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 6014 C2S(WOW_REASON_IOAC_SHORT_EVENT); 6015 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 6016 C2S(WOW_REASON_IOAC_TIMER_EVENT); 6017 C2S(WOW_REASON_ROAM_HO); 6018 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 6019 C2S(WOW_REASON_BEACON_RECV); 6020 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 6021 C2S(WOW_REASON_PAGE_FAULT); 6022 C2S(WOW_REASON_DEBUG_TEST); 6023 default: 6024 return NULL; 6025 } 6026 } 6027 6028 #undef C2S 6029 6030 struct wmi_wow_ev_arg { 6031 uint32_t vdev_id; 6032 uint32_t flag; 6033 enum wmi_wow_wake_reason wake_reason; 6034 uint32_t data_len; 6035 }; 6036 6037 enum wmi_tlv_pattern_type { 6038 WOW_PATTERN_MIN = 0, 6039 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 6040 WOW_IPV4_SYNC_PATTERN, 6041 WOW_IPV6_SYNC_PATTERN, 6042 WOW_WILD_CARD_PATTERN, 6043 WOW_TIMER_PATTERN, 6044 WOW_MAGIC_PATTERN, 6045 WOW_IPV6_RA_PATTERN, 6046 WOW_IOAC_PKT_PATTERN, 6047 WOW_IOAC_TMR_PATTERN, 6048 WOW_PATTERN_MAX 6049 }; 6050 6051 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 6052 #define WOW_DEFAULT_BITMASK_SIZE 148 6053 6054 #define WOW_MIN_PATTERN_SIZE 1 6055 #define WOW_MAX_PATTERN_SIZE 148 6056 #define WOW_MAX_PKT_OFFSET 128 6057 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 6058 sizeof(struct rfc1042_hdr)) 6059 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 6060 offsetof(struct ieee80211_hdr_3addr, addr1)) 6061 6062 struct wmi_wow_add_del_event_cmd { 6063 uint32_t tlv_header; 6064 uint32_t vdev_id; 6065 uint32_t is_add; 6066 uint32_t event_bitmap; 6067 } __packed; 6068 6069 struct wmi_wow_enable_cmd { 6070 uint32_t tlv_header; 6071 uint32_t enable; 6072 uint32_t pause_iface_config; 6073 uint32_t flags; 6074 } __packed; 6075 6076 struct wmi_wow_host_wakeup_ind { 6077 uint32_t tlv_header; 6078 uint32_t reserved; 6079 } __packed; 6080 6081 struct wmi_tlv_wow_event_info { 6082 uint32_t vdev_id; 6083 uint32_t flag; 6084 uint32_t wake_reason; 6085 uint32_t data_len; 6086 } __packed; 6087 6088 struct wmi_wow_bitmap_pattern { 6089 uint32_t tlv_header; 6090 uint8_t patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 6091 uint8_t bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 6092 uint32_t pattern_offset; 6093 uint32_t pattern_len; 6094 uint32_t bitmask_len; 6095 uint32_t pattern_id; 6096 } __packed; 6097 6098 struct wmi_wow_add_pattern_cmd { 6099 uint32_t tlv_header; 6100 uint32_t vdev_id; 6101 uint32_t pattern_id; 6102 uint32_t pattern_type; 6103 } __packed; 6104 6105 struct wmi_wow_del_pattern_cmd { 6106 uint32_t tlv_header; 6107 uint32_t vdev_id; 6108 uint32_t pattern_id; 6109 uint32_t pattern_type; 6110 } __packed; 6111 6112 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 6113 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 6114 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 6115 #define WMI_PNO_MAX_NETW_CHANNELS 26 6116 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 6117 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 6118 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 6119 6120 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 6121 #define WMI_PNO_MAX_PB_REQ_SIZE 450 6122 6123 #define WMI_PNO_24G_DEFAULT_CH 1 6124 #define WMI_PNO_5G_DEFAULT_CH 36 6125 6126 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 6127 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 6128 6129 /* SSID broadcast type */ 6130 enum wmi_ssid_bcast_type { 6131 BCAST_UNKNOWN = 0, 6132 BCAST_NORMAL = 1, 6133 BCAST_HIDDEN = 2, 6134 }; 6135 6136 #define WMI_NLO_MAX_SSIDS 16 6137 #define WMI_NLO_MAX_CHAN 48 6138 6139 #define WMI_NLO_CONFIG_STOP BIT(0) 6140 #define WMI_NLO_CONFIG_START BIT(1) 6141 #define WMI_NLO_CONFIG_RESET BIT(2) 6142 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 6143 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 6144 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 6145 6146 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 6147 * Only one of them can be enabled at a given time 6148 */ 6149 #define WMI_NLO_CONFIG_ENLO BIT(7) 6150 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 6151 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 6152 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 6153 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 6154 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 6155 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 6156 6157 struct wmi_nlo_ssid_param { 6158 uint32_t valid; 6159 struct wmi_ssid ssid; 6160 } __packed; 6161 6162 struct wmi_nlo_enc_param { 6163 uint32_t valid; 6164 uint32_t enc_type; 6165 } __packed; 6166 6167 struct wmi_nlo_auth_param { 6168 uint32_t valid; 6169 uint32_t auth_type; 6170 } __packed; 6171 6172 struct wmi_nlo_bcast_nw_param { 6173 uint32_t valid; 6174 uint32_t bcast_nw_type; 6175 } __packed; 6176 6177 struct wmi_nlo_rssi_param { 6178 uint32_t valid; 6179 int32_t rssi; 6180 } __packed; 6181 6182 struct nlo_configured_parameters { 6183 /* TLV tag and len;*/ 6184 uint32_t tlv_header; 6185 struct wmi_nlo_ssid_param ssid; 6186 struct wmi_nlo_enc_param enc_type; 6187 struct wmi_nlo_auth_param auth_type; 6188 struct wmi_nlo_rssi_param rssi_cond; 6189 6190 /* indicates if the SSID is hidden or not */ 6191 struct wmi_nlo_bcast_nw_param bcast_nw_type; 6192 } __packed; 6193 6194 struct wmi_network_type { 6195 struct wmi_ssid ssid; 6196 uint32_t authentication; 6197 uint32_t encryption; 6198 uint32_t bcast_nw_type; 6199 uint8_t channel_count; 6200 uint16_t channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 6201 int32_t rssi_threshold; 6202 }; 6203 6204 struct wmi_pno_scan_req { 6205 uint8_t enable; 6206 uint8_t vdev_id; 6207 uint8_t uc_networks_count; 6208 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 6209 uint32_t fast_scan_period; 6210 uint32_t slow_scan_period; 6211 uint8_t fast_scan_max_cycles; 6212 6213 bool do_passive_scan; 6214 6215 uint32_t delay_start_time; 6216 uint32_t active_min_time; 6217 uint32_t active_max_time; 6218 uint32_t passive_min_time; 6219 uint32_t passive_max_time; 6220 6221 /* mac address randomization attributes */ 6222 uint32_t enable_pno_scan_randomization; 6223 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 6224 uint8_t mac_addr_mask[IEEE80211_ADDR_LEN]; 6225 }; 6226 6227 struct wmi_wow_nlo_config_cmd { 6228 uint32_t tlv_header; 6229 uint32_t flags; 6230 uint32_t vdev_id; 6231 uint32_t fast_scan_max_cycles; 6232 uint32_t active_dwell_time; 6233 uint32_t passive_dwell_time; 6234 uint32_t probe_bundle_size; 6235 6236 /* ART = IRT */ 6237 uint32_t rest_time; 6238 6239 /* Max value that can be reached after SBM */ 6240 uint32_t max_rest_time; 6241 6242 /* SBM */ 6243 uint32_t scan_backoff_multiplier; 6244 6245 /* SCBM */ 6246 uint32_t fast_scan_period; 6247 6248 /* specific to windows */ 6249 uint32_t slow_scan_period; 6250 6251 uint32_t no_of_ssids; 6252 6253 uint32_t num_of_channels; 6254 6255 /* NLO scan start delay time in milliseconds */ 6256 uint32_t delay_start_time; 6257 6258 /* MAC Address to use in Probe Req as SA */ 6259 struct wmi_mac_addr mac_addr; 6260 6261 /* Mask on which MAC has to be randomized */ 6262 struct wmi_mac_addr mac_mask; 6263 6264 /* IE bitmap to use in Probe Req */ 6265 uint32_t ie_bitmap[8]; 6266 6267 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 6268 uint32_t num_vendor_oui; 6269 6270 /* Number of connected NLO band preferences */ 6271 uint32_t num_cnlo_band_pref; 6272 6273 /* The TLVs will follow. 6274 * nlo_configured_parameters nlo_list[]; 6275 * uint32_t channel_list[num_of_channels]; 6276 */ 6277 } __packed; 6278 6279 #define WMI_MAX_NS_OFFLOADS 2 6280 #define WMI_MAX_ARP_OFFLOADS 2 6281 6282 #define WMI_ARPOL_FLAGS_VALID BIT(0) 6283 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 6284 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 6285 6286 struct wmi_arp_offload_tuple { 6287 uint32_t tlv_header; 6288 uint32_t flags; 6289 uint8_t target_ipaddr[4]; 6290 uint8_t remote_ipaddr[4]; 6291 struct wmi_mac_addr target_mac; 6292 } __packed; 6293 6294 #define WMI_NSOL_FLAGS_VALID BIT(0) 6295 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 6296 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 6297 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 6298 6299 #define WMI_NSOL_MAX_TARGET_IPS 2 6300 6301 struct wmi_ns_offload_tuple { 6302 uint32_t tlv_header; 6303 uint32_t flags; 6304 uint8_t target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 6305 uint8_t solicitation_ipaddr[16]; 6306 uint8_t remote_ipaddr[16]; 6307 struct wmi_mac_addr target_mac; 6308 } __packed; 6309 6310 struct wmi_set_arp_ns_offload_cmd { 6311 uint32_t tlv_header; 6312 uint32_t flags; 6313 uint32_t vdev_id; 6314 uint32_t num_ns_ext_tuples; 6315 /* The TLVs follow: 6316 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 6317 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 6318 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 6319 */ 6320 } __packed; 6321 6322 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6323 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6324 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6325 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6326 6327 #define GTK_OFFLOAD_KEK_BYTES 16 6328 #define GTK_OFFLOAD_KCK_BYTES 16 6329 #define GTK_REPLAY_COUNTER_BYTES 8 6330 #define WMI_MAX_KEY_LEN 32 6331 #define IGTK_PN_SIZE 6 6332 6333 struct wmi_replayc_cnt { 6334 union { 6335 uint8_t counter[GTK_REPLAY_COUNTER_BYTES]; 6336 struct { 6337 uint32_t word0; 6338 uint32_t word1; 6339 } __packed; 6340 } __packed; 6341 } __packed; 6342 6343 struct wmi_gtk_offload_status_event { 6344 uint32_t vdev_id; 6345 uint32_t flags; 6346 uint32_t refresh_cnt; 6347 struct wmi_replayc_cnt replay_ctr; 6348 uint8_t igtk_key_index; 6349 uint8_t igtk_key_length; 6350 uint8_t igtk_key_rsc[IGTK_PN_SIZE]; 6351 uint8_t igtk_key[WMI_MAX_KEY_LEN]; 6352 uint8_t gtk_key_index; 6353 uint8_t gtk_key_length; 6354 uint8_t gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6355 uint8_t gtk_key[WMI_MAX_KEY_LEN]; 6356 } __packed; 6357 6358 struct wmi_gtk_rekey_offload_cmd { 6359 uint32_t tlv_header; 6360 uint32_t vdev_id; 6361 uint32_t flags; 6362 uint8_t kek[GTK_OFFLOAD_KEK_BYTES]; 6363 uint8_t kck[GTK_OFFLOAD_KCK_BYTES]; 6364 uint8_t replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6365 } __packed; 6366 6367 #define BIOS_SAR_TABLE_LEN (22) 6368 #define BIOS_SAR_RSVD1_LEN (6) 6369 #define BIOS_SAR_RSVD2_LEN (18) 6370 6371 struct wmi_pdev_set_sar_table_cmd { 6372 uint32_t tlv_header; 6373 uint32_t pdev_id; 6374 uint32_t sar_len; 6375 uint32_t rsvd_len; 6376 } __packed; 6377 6378 struct wmi_pdev_set_geo_table_cmd { 6379 uint32_t tlv_header; 6380 uint32_t pdev_id; 6381 uint32_t rsvd_len; 6382 } __packed; 6383 6384 struct wmi_sta_keepalive_cmd { 6385 uint32_t tlv_header; 6386 uint32_t vdev_id; 6387 uint32_t enabled; 6388 6389 /* WMI_STA_KEEPALIVE_METHOD_ */ 6390 uint32_t method; 6391 6392 /* in seconds */ 6393 uint32_t interval; 6394 6395 /* following this structure is the TLV for struct 6396 * wmi_sta_keepalive_arp_resp 6397 */ 6398 } __packed; 6399 6400 struct wmi_sta_keepalive_arp_resp { 6401 uint32_t tlv_header; 6402 uint32_t src_ip4_addr; 6403 uint32_t dest_ip4_addr; 6404 struct wmi_mac_addr dest_mac_addr; 6405 } __packed; 6406 6407 struct wmi_sta_keepalive_arg { 6408 uint32_t vdev_id; 6409 uint32_t enabled; 6410 uint32_t method; 6411 uint32_t interval; 6412 uint32_t src_ip4_addr; 6413 uint32_t dest_ip4_addr; 6414 const uint8_t dest_mac_addr[IEEE80211_ADDR_LEN]; 6415 }; 6416 6417 enum wmi_sta_keepalive_method { 6418 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6419 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6420 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6421 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6422 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6423 }; 6424 6425 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6426 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6427 6428 6429 /* 6430 * qrtr.h 6431 */ 6432 6433 #define QRTR_PROTO_VER_1 1 6434 #define QRTR_PROTO_VER_2 3 /* (sic!) */ 6435 6436 struct qrtr_hdr_v1 { 6437 uint32_t version; 6438 uint32_t type; 6439 uint32_t src_node_id; 6440 uint32_t src_port_id; 6441 uint32_t confirm_rx; 6442 uint32_t size; 6443 uint32_t dst_node_id; 6444 uint32_t dst_port_id; 6445 } __packed; 6446 6447 struct qrtr_hdr_v2 { 6448 uint8_t version; 6449 uint8_t type; 6450 uint8_t flags; 6451 uint8_t optlen; 6452 uint32_t size; 6453 uint16_t src_node_id; 6454 uint16_t src_port_id; 6455 uint16_t dst_node_id; 6456 uint16_t dst_port_id; 6457 }; 6458 6459 struct qrtr_ctrl_pkt { 6460 uint32_t cmd; 6461 6462 union { 6463 struct { 6464 uint32_t service; 6465 uint32_t instance; 6466 uint32_t node; 6467 uint32_t port; 6468 } server; 6469 struct { 6470 uint32_t node; 6471 uint32_t port; 6472 } client; 6473 }; 6474 } __packed; 6475 6476 #define QRTR_TYPE_DATA 1 6477 #define QRTR_TYPE_HELLO 2 6478 #define QRTR_TYPE_BYE 3 6479 #define QRTR_TYPE_NEW_SERVER 4 6480 #define QRTR_TYPE_DEL_SERVER 5 6481 #define QRTR_TYPE_DEL_CLIENT 6 6482 #define QRTR_TYPE_RESUME_TX 7 6483 #define QRTR_TYPE_EXIT 8 6484 #define QRTR_TYPE_PING 9 6485 #define QRTR_TYPE_NEW_LOOKUP 10 6486 #define QRTR_TYPE_DEL_LOOKUP 11 6487 6488 #define QRTR_FLAGS_CONFIRM_RX (1 << 0) 6489 6490 #define QRTR_NODE_BCAST 0xffffffffU 6491 #define QRTR_PORT_CTRL 0xfffffffeU 6492 6493 /* 6494 * qmi.h 6495 */ 6496 6497 #define QMI_REQUEST 0 6498 #define QMI_RESPONSE 2 6499 #define QMI_INDICATION 4 6500 6501 struct qmi_header { 6502 uint8_t type; 6503 uint16_t txn_id; 6504 uint16_t msg_id; 6505 uint16_t msg_len; 6506 } __packed; 6507 6508 #define QMI_COMMON_TLV_TYPE 0 6509 6510 enum qmi_elem_type { 6511 QMI_EOTI, 6512 QMI_OPT_FLAG, 6513 QMI_DATA_LEN, 6514 QMI_UNSIGNED_1_BYTE, 6515 QMI_UNSIGNED_2_BYTE, 6516 QMI_UNSIGNED_4_BYTE, 6517 QMI_UNSIGNED_8_BYTE, 6518 QMI_SIGNED_2_BYTE_ENUM, 6519 QMI_SIGNED_4_BYTE_ENUM, 6520 QMI_STRUCT, 6521 QMI_STRING, 6522 QMI_NUM_DATA_TYPES 6523 }; 6524 6525 enum qmi_array_type { 6526 NO_ARRAY, 6527 STATIC_ARRAY, 6528 VAR_LEN_ARRAY, 6529 }; 6530 6531 struct qmi_elem_info { 6532 enum qmi_elem_type data_type; 6533 uint32_t elem_len; 6534 uint32_t elem_size; 6535 enum qmi_array_type array_type; 6536 uint8_t tlv_type; 6537 uint32_t offset; 6538 const struct qmi_elem_info *ei_array; 6539 }; 6540 6541 #define QMI_RESULT_SUCCESS_V01 0 6542 #define QMI_RESULT_FAILURE_V01 1 6543 6544 #define QMI_ERR_NONE_V01 0 6545 #define QMI_ERR_MALFORMED_MSG_V01 1 6546 #define QMI_ERR_NO_MEMORY_V01 2 6547 #define QMI_ERR_INTERNAL_V01 3 6548 #define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 5 6549 #define QMI_ERR_INVALID_ID_V01 41 6550 #define QMI_ERR_ENCODING_V01 58 6551 #define QMI_ERR_DISABLED_V01 69 6552 #define QMI_ERR_INCOMPATIBLE_STATE_V01 90 6553 #define QMI_ERR_NOT_SUPPORTED_V01 94 6554 6555 struct qmi_response_type_v01 { 6556 uint16_t result; 6557 uint16_t error; 6558 }; 6559 6560 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 6561 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 6562 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 6563 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 6564 6565 struct qmi_wlanfw_phy_cap_req_msg_v01 { 6566 }; 6567 6568 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 6569 struct qmi_response_type_v01 resp; 6570 uint8_t num_phy_valid; 6571 uint8_t num_phy; 6572 uint8_t board_id_valid; 6573 uint32_t board_id; 6574 uint8_t single_chip_mlo_support_valid; 6575 uint8_t single_chip_mlo_support; 6576 }; 6577 6578 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 6579 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 6580 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 6581 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 6582 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 6583 6584 struct qmi_wlanfw_ind_register_req_msg_v01 { 6585 uint8_t fw_ready_enable_valid; 6586 uint8_t fw_ready_enable; 6587 uint8_t initiate_cal_download_enable_valid; 6588 uint8_t initiate_cal_download_enable; 6589 uint8_t initiate_cal_update_enable_valid; 6590 uint8_t initiate_cal_update_enable; 6591 uint8_t msa_ready_enable_valid; 6592 uint8_t msa_ready_enable; 6593 uint8_t pin_connect_result_enable_valid; 6594 uint8_t pin_connect_result_enable; 6595 uint8_t client_id_valid; 6596 uint32_t client_id; 6597 uint8_t request_mem_enable_valid; 6598 uint8_t request_mem_enable; 6599 uint8_t fw_mem_ready_enable_valid; 6600 uint8_t fw_mem_ready_enable; 6601 uint8_t fw_init_done_enable_valid; 6602 uint8_t fw_init_done_enable; 6603 uint8_t rejuvenate_enable_valid; 6604 uint32_t rejuvenate_enable; 6605 uint8_t xo_cal_enable_valid; 6606 uint8_t xo_cal_enable; 6607 uint8_t cal_done_enable_valid; 6608 uint8_t cal_done_enable; 6609 }; 6610 6611 struct qmi_wlanfw_ind_register_resp_msg_v01 { 6612 struct qmi_response_type_v01 resp; 6613 uint8_t fw_status_valid; 6614 uint64_t fw_status; 6615 }; 6616 6617 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 6618 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 6619 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 6620 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 6621 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 6622 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 6623 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 6624 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 6625 #define HOST_DDR_REGION_TYPE 0x1 6626 #define BDF_MEM_REGION_TYPE 0x2 6627 #define M3_DUMP_REGION_TYPE 0x3 6628 #define CALDB_MEM_REGION_TYPE 0x4 6629 6630 struct qmi_wlanfw_host_ddr_range { 6631 uint64_t start; 6632 uint64_t size; 6633 }; 6634 6635 enum qmi_wlanfw_host_build_type { 6636 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 6637 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 6638 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 6639 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 6640 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 6641 }; 6642 6643 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 6644 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 6645 6646 struct wlfw_host_mlo_chip_info_s_v01 { 6647 uint8_t chip_id; 6648 uint8_t num_local_links; 6649 uint8_t hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 6650 uint8_t valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 6651 }; 6652 6653 enum ath12k_qmi_cnss_feature { 6654 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 6655 CNSS_QDSS_CFG_MISS_V01 = 3, 6656 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 6657 CNSS_MAX_FEATURE_V01 = 64, 6658 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 6659 }; 6660 6661 struct qmi_wlanfw_host_cap_req_msg_v01 { 6662 uint8_t num_clients_valid; 6663 uint32_t num_clients; 6664 uint8_t wake_msi_valid; 6665 uint32_t wake_msi; 6666 uint8_t gpios_valid; 6667 uint32_t gpios_len; 6668 uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 6669 uint8_t nm_modem_valid; 6670 uint8_t nm_modem; 6671 uint8_t bdf_support_valid; 6672 uint8_t bdf_support; 6673 uint8_t bdf_cache_support_valid; 6674 uint8_t bdf_cache_support; 6675 uint8_t m3_support_valid; 6676 uint8_t m3_support; 6677 uint8_t m3_cache_support_valid; 6678 uint8_t m3_cache_support; 6679 uint8_t cal_filesys_support_valid; 6680 uint8_t cal_filesys_support; 6681 uint8_t cal_cache_support_valid; 6682 uint8_t cal_cache_support; 6683 uint8_t cal_done_valid; 6684 uint8_t cal_done; 6685 uint8_t mem_bucket_valid; 6686 uint32_t mem_bucket; 6687 uint8_t mem_cfg_mode_valid; 6688 uint8_t mem_cfg_mode; 6689 uint8_t cal_duration_valid; 6690 uint16_t cal_duration; 6691 uint8_t platform_name_valid; 6692 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 6693 uint8_t ddr_range_valid; 6694 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 6695 uint8_t host_build_type_valid; 6696 enum qmi_wlanfw_host_build_type host_build_type; 6697 uint8_t mlo_capable_valid; 6698 uint8_t mlo_capable; 6699 uint8_t mlo_chip_id_valid; 6700 uint16_t mlo_chip_id; 6701 uint8_t mlo_group_id_valid; 6702 uint8_t mlo_group_id; 6703 uint8_t max_mlo_peer_valid; 6704 uint16_t max_mlo_peer; 6705 uint8_t mlo_num_chips_valid; 6706 uint8_t mlo_num_chips; 6707 uint8_t mlo_chip_info_valid; 6708 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 6709 uint8_t feature_list_valid; 6710 uint64_t feature_list; 6711 }; 6712 6713 struct qmi_wlanfw_host_cap_resp_msg_v01 { 6714 struct qmi_response_type_v01 resp; 6715 }; 6716 6717 #define ATH12K_HOST_VERSION_STRING "WIN" 6718 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 6719 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 6720 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 6721 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 6722 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 6723 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 6724 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 6725 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x01 6726 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 6727 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 6728 6729 #define ATH12K_QMI_RESP_LEN_MAX 8192 6730 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 6731 #define ATH12K_QMI_CALDB_SIZE 0x480000 6732 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 6733 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 6734 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 6735 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 6736 6737 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 6738 #define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 6739 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 6740 #define QMI_WLFW_FW_READY_IND_V01 0x0038 6741 6742 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 6743 #define ATH12K_FIRMWARE_MODE_OFF 4 6744 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 6745 6746 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 6747 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 6748 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 6749 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 6750 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 6751 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 6752 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 6753 6754 struct qmi_wlanfw_mem_cfg_s_v01 { 6755 uint64_t offset; 6756 uint32_t size; 6757 uint8_t secure_flag; 6758 }; 6759 6760 enum qmi_wlanfw_mem_type_enum_v01 { 6761 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 6762 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 6763 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 6764 QMI_WLANFW_MEM_BDF_V01 = 2, 6765 QMI_WLANFW_MEM_M3_V01 = 3, 6766 QMI_WLANFW_MEM_CAL_V01 = 4, 6767 QMI_WLANFW_MEM_DPD_V01 = 5, 6768 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 6769 }; 6770 6771 struct qmi_wlanfw_mem_seg_s_v01 { 6772 uint32_t size; 6773 enum qmi_wlanfw_mem_type_enum_v01 type; 6774 uint32_t mem_cfg_len; 6775 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 6776 }; 6777 6778 struct qmi_wlanfw_request_mem_ind_msg_v01 { 6779 uint32_t mem_seg_len; 6780 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6781 }; 6782 6783 struct qmi_wlanfw_mem_seg_resp_s_v01 { 6784 uint64_t addr; 6785 uint32_t size; 6786 enum qmi_wlanfw_mem_type_enum_v01 type; 6787 uint8_t restore; 6788 }; 6789 6790 struct qmi_wlanfw_respond_mem_req_msg_v01 { 6791 uint32_t mem_seg_len; 6792 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6793 }; 6794 6795 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 6796 struct qmi_response_type_v01 resp; 6797 }; 6798 6799 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 6800 char placeholder; 6801 }; 6802 6803 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 6804 char placeholder; 6805 }; 6806 6807 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 6808 char placeholder; 6809 }; 6810 6811 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 6812 char placeholder; 6813 }; 6814 6815 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 6816 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 6817 #define QMI_WLANFW_CAP_REQ_V01 0x0024 6818 #define QMI_WLANFW_CAP_RESP_V01 0x0024 6819 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 6820 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 6821 6822 enum qmi_wlanfw_pipedir_enum_v01 { 6823 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 6824 QMI_WLFW_PIPEDIR_IN_V01 = 1, 6825 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 6826 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 6827 }; 6828 6829 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 6830 uint32_t pipe_num; 6831 uint32_t pipe_dir; 6832 uint32_t nentries; 6833 uint32_t nbytes_max; 6834 uint32_t flags; 6835 }; 6836 6837 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 6838 uint32_t service_id; 6839 uint32_t pipe_dir; 6840 uint32_t pipe_num; 6841 }; 6842 6843 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 6844 uint16_t id; 6845 uint16_t offset; 6846 }; 6847 6848 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 6849 uint32_t addr; 6850 }; 6851 6852 struct qmi_wlanfw_memory_region_info_s_v01 { 6853 uint64_t region_addr; 6854 uint32_t size; 6855 uint8_t secure_flag; 6856 }; 6857 6858 struct qmi_wlanfw_rf_chip_info_s_v01 { 6859 uint32_t chip_id; 6860 uint32_t chip_family; 6861 }; 6862 6863 struct qmi_wlanfw_rf_board_info_s_v01 { 6864 uint32_t board_id; 6865 }; 6866 6867 struct qmi_wlanfw_soc_info_s_v01 { 6868 uint32_t soc_id; 6869 }; 6870 6871 struct qmi_wlanfw_fw_version_info_s_v01 { 6872 uint32_t fw_version; 6873 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 6874 }; 6875 6876 struct qmi_wlanfw_dev_mem_info_s_v01 { 6877 uint64_t start; 6878 uint64_t size; 6879 }; 6880 6881 enum qmi_wlanfw_cal_temp_id_enum_v01 { 6882 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 6883 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 6884 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 6885 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 6886 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 6887 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 6888 }; 6889 6890 enum qmi_wlanfw_rd_card_chain_cap_v01 { 6891 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 6892 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 6893 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 6894 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 6895 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 6896 }; 6897 6898 struct qmi_wlanfw_cap_resp_msg_v01 { 6899 struct qmi_response_type_v01 resp; 6900 uint8_t chip_info_valid; 6901 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 6902 uint8_t board_info_valid; 6903 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 6904 uint8_t soc_info_valid; 6905 struct qmi_wlanfw_soc_info_s_v01 soc_info; 6906 uint8_t fw_version_info_valid; 6907 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 6908 uint8_t fw_build_id_valid; 6909 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 6910 uint8_t num_macs_valid; 6911 uint8_t num_macs; 6912 uint8_t voltage_mv_valid; 6913 uint32_t voltage_mv; 6914 uint8_t time_freq_hz_valid; 6915 uint32_t time_freq_hz; 6916 uint8_t otp_version_valid; 6917 uint32_t otp_version; 6918 uint8_t eeprom_read_timeout_valid; 6919 uint32_t eeprom_read_timeout; 6920 uint8_t fw_caps_valid; 6921 uint64_t fw_caps; 6922 uint8_t rd_card_chain_cap_valid; 6923 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 6924 uint8_t dev_mem_info_valid; 6925 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 6926 }; 6927 6928 struct qmi_wlanfw_cap_req_msg_v01 { 6929 char placeholder; 6930 }; 6931 6932 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 6933 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 6934 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 6935 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 6936 /* TODO: Need to check with MCL and FW team that data can be pointer and 6937 * can be last element in structure 6938 */ 6939 struct qmi_wlanfw_bdf_download_req_msg_v01 { 6940 uint8_t valid; 6941 uint8_t file_id_valid; 6942 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 6943 uint8_t total_size_valid; 6944 uint32_t total_size; 6945 uint8_t seg_id_valid; 6946 uint32_t seg_id; 6947 uint8_t data_valid; 6948 uint32_t data_len; 6949 uint8_t data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 6950 uint8_t end_valid; 6951 uint8_t end; 6952 uint8_t bdf_type_valid; 6953 uint8_t bdf_type; 6954 }; 6955 6956 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 6957 struct qmi_response_type_v01 resp; 6958 }; 6959 6960 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 6961 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 6962 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003c 6963 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003c 6964 6965 struct qmi_wlanfw_m3_info_req_msg_v01 { 6966 uint64_t addr; 6967 uint32_t size; 6968 }; 6969 6970 struct qmi_wlanfw_m3_info_resp_msg_v01 { 6971 struct qmi_response_type_v01 resp; 6972 }; 6973 6974 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 6975 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 6976 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 6977 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 6978 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 6979 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 6980 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 6981 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 6982 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 6983 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002f 6984 #define QMI_WLANFW_WLAN_INI_RESP_V01 0x002f 6985 #define QMI_WLANFW_MAX_STR_LEN_V01 16 6986 #define QMI_WLANFW_MAX_NUM_CE_V01 12 6987 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 6988 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 6989 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 6990 6991 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 6992 uint32_t mode; 6993 uint8_t hw_debug_valid; 6994 uint8_t hw_debug; 6995 }; 6996 6997 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 6998 struct qmi_response_type_v01 resp; 6999 }; 7000 7001 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 7002 uint8_t host_version_valid; 7003 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 7004 uint8_t tgt_cfg_valid; 7005 uint32_t tgt_cfg_len; 7006 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 7007 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 7008 uint8_t svc_cfg_valid; 7009 uint32_t svc_cfg_len; 7010 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 7011 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 7012 uint8_t shadow_reg_valid; 7013 uint32_t shadow_reg_len; 7014 struct qmi_wlanfw_shadow_reg_cfg_s_v01 7015 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 7016 uint8_t shadow_reg_v3_valid; 7017 uint32_t shadow_reg_v3_len; 7018 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 7019 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 7020 }; 7021 7022 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 7023 struct qmi_response_type_v01 resp; 7024 }; 7025 7026 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 7027 /* Must be set to true if enablefwlog is being passed */ 7028 uint8_t enablefwlog_valid; 7029 uint8_t enablefwlog; 7030 }; 7031 7032 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 7033 struct qmi_response_type_v01 resp; 7034 }; 7035 7036 enum ath12k_qmi_file_type { 7037 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN, 7038 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 7039 ATH12K_QMI_FILE_TYPE_EEPROM, 7040 ATH12K_QMI_MAX_FILE_TYPE, 7041 }; 7042 7043 enum ath12k_qmi_bdf_type { 7044 ATH12K_QMI_BDF_TYPE_BIN = 0, 7045 ATH12K_QMI_BDF_TYPE_ELF = 1, 7046 ATH12K_QMI_BDF_TYPE_REGDB = 4, 7047 }; 7048 7049 #define HAL_LINK_DESC_SIZE (32 << 2) 7050 #define HAL_LINK_DESC_ALIGN 128 7051 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 7052 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 7053 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 7054 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 7055 #define HAL_MAX_AVAIL_BLK_RES 3 7056 7057 #define HAL_RING_BASE_ALIGN 8 7058 7059 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 7060 /* TODO: Check with hw team on the supported scatter buf size */ 7061 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 7062 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 7063 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 7064 7065 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32 7066 #define HAL_DSCP_TID_TBL_SIZE 24 7067 7068 /* calculate the register address from bar0 of shadow register x */ 7069 #define HAL_SHADOW_BASE_ADDR 0x000008fc 7070 #define HAL_SHADOW_NUM_REGS 40 7071 #define HAL_HP_OFFSET_IN_REG_START 1 7072 #define HAL_OFFSET_FROM_HP_TO_TP 4 7073 7074 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 7075 7076 enum hal_srng_ring_id { 7077 HAL_SRNG_RING_ID_REO2SW0 = 0, 7078 HAL_SRNG_RING_ID_REO2SW1, 7079 HAL_SRNG_RING_ID_REO2SW2, 7080 HAL_SRNG_RING_ID_REO2SW3, 7081 HAL_SRNG_RING_ID_REO2SW4, 7082 HAL_SRNG_RING_ID_REO2SW5, 7083 HAL_SRNG_RING_ID_REO2SW6, 7084 HAL_SRNG_RING_ID_REO2SW7, 7085 HAL_SRNG_RING_ID_REO2SW8, 7086 HAL_SRNG_RING_ID_REO2TCL, 7087 HAL_SRNG_RING_ID_REO2PPE, 7088 7089 HAL_SRNG_RING_ID_SW2REO = 16, 7090 HAL_SRNG_RING_ID_SW2REO1, 7091 HAL_SRNG_RING_ID_SW2REO2, 7092 HAL_SRNG_RING_ID_SW2REO3, 7093 7094 HAL_SRNG_RING_ID_REO_CMD, 7095 HAL_SRNG_RING_ID_REO_STATUS, 7096 7097 HAL_SRNG_RING_ID_SW2TCL1 = 24, 7098 HAL_SRNG_RING_ID_SW2TCL2, 7099 HAL_SRNG_RING_ID_SW2TCL3, 7100 HAL_SRNG_RING_ID_SW2TCL4, 7101 HAL_SRNG_RING_ID_SW2TCL5, 7102 HAL_SRNG_RING_ID_SW2TCL6, 7103 HAL_SRNG_RING_ID_PPE2TCL1 = 30, 7104 7105 HAL_SRNG_RING_ID_SW2TCL_CMD = 40, 7106 HAL_SRNG_RING_ID_SW2TCL1_CMD, 7107 HAL_SRNG_RING_ID_TCL_STATUS, 7108 7109 HAL_SRNG_RING_ID_CE0_SRC = 64, 7110 HAL_SRNG_RING_ID_CE1_SRC, 7111 HAL_SRNG_RING_ID_CE2_SRC, 7112 HAL_SRNG_RING_ID_CE3_SRC, 7113 HAL_SRNG_RING_ID_CE4_SRC, 7114 HAL_SRNG_RING_ID_CE5_SRC, 7115 HAL_SRNG_RING_ID_CE6_SRC, 7116 HAL_SRNG_RING_ID_CE7_SRC, 7117 HAL_SRNG_RING_ID_CE8_SRC, 7118 HAL_SRNG_RING_ID_CE9_SRC, 7119 HAL_SRNG_RING_ID_CE10_SRC, 7120 HAL_SRNG_RING_ID_CE11_SRC, 7121 HAL_SRNG_RING_ID_CE12_SRC, 7122 HAL_SRNG_RING_ID_CE13_SRC, 7123 HAL_SRNG_RING_ID_CE14_SRC, 7124 HAL_SRNG_RING_ID_CE15_SRC, 7125 7126 HAL_SRNG_RING_ID_CE0_DST = 81, 7127 HAL_SRNG_RING_ID_CE1_DST, 7128 HAL_SRNG_RING_ID_CE2_DST, 7129 HAL_SRNG_RING_ID_CE3_DST, 7130 HAL_SRNG_RING_ID_CE4_DST, 7131 HAL_SRNG_RING_ID_CE5_DST, 7132 HAL_SRNG_RING_ID_CE6_DST, 7133 HAL_SRNG_RING_ID_CE7_DST, 7134 HAL_SRNG_RING_ID_CE8_DST, 7135 HAL_SRNG_RING_ID_CE9_DST, 7136 HAL_SRNG_RING_ID_CE10_DST, 7137 HAL_SRNG_RING_ID_CE11_DST, 7138 HAL_SRNG_RING_ID_CE12_DST, 7139 HAL_SRNG_RING_ID_CE13_DST, 7140 HAL_SRNG_RING_ID_CE14_DST, 7141 HAL_SRNG_RING_ID_CE15_DST, 7142 7143 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100, 7144 HAL_SRNG_RING_ID_CE1_DST_STATUS, 7145 HAL_SRNG_RING_ID_CE2_DST_STATUS, 7146 HAL_SRNG_RING_ID_CE3_DST_STATUS, 7147 HAL_SRNG_RING_ID_CE4_DST_STATUS, 7148 HAL_SRNG_RING_ID_CE5_DST_STATUS, 7149 HAL_SRNG_RING_ID_CE6_DST_STATUS, 7150 HAL_SRNG_RING_ID_CE7_DST_STATUS, 7151 HAL_SRNG_RING_ID_CE8_DST_STATUS, 7152 HAL_SRNG_RING_ID_CE9_DST_STATUS, 7153 HAL_SRNG_RING_ID_CE10_DST_STATUS, 7154 HAL_SRNG_RING_ID_CE11_DST_STATUS, 7155 HAL_SRNG_RING_ID_CE12_DST_STATUS, 7156 HAL_SRNG_RING_ID_CE13_DST_STATUS, 7157 HAL_SRNG_RING_ID_CE14_DST_STATUS, 7158 HAL_SRNG_RING_ID_CE15_DST_STATUS, 7159 7160 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120, 7161 HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 7162 HAL_SRNG_RING_ID_WBM_SW1_RELEASE, 7163 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123, 7164 7165 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128, 7166 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 7167 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 7168 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */ 7169 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 7170 HAL_SRNG_RING_ID_WBM2SW5_RELEASE, 7171 HAL_SRNG_RING_ID_WBM2SW6_RELEASE, 7172 HAL_SRNG_RING_ID_WBM2SW7_RELEASE, 7173 7174 HAL_SRNG_RING_ID_UMAC_ID_END = 159, 7175 7176 /* Common DMAC rings shared by all LMACs */ 7177 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160, 7178 HAL_SRNG_SW2RXDMA_BUF0 = 7179 HAL_SRNG_RING_ID_DMAC_CMN_ID_START, 7180 HAL_SRNG_SW2RXDMA_BUF1 = 161, 7181 HAL_SRNG_SW2RXDMA_BUF2 = 162, 7182 7183 HAL_SRNG_SW2RXMON_BUF0 = 168, 7184 7185 HAL_SRNG_SW2TXMON_BUF0 = 176, 7186 7187 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183, 7188 HAL_SRNG_RING_ID_PMAC1_ID_START = 184, 7189 7190 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = 7191 HAL_SRNG_RING_ID_PMAC1_ID_START, 7192 7193 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 7194 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 7195 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = 7196 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 7197 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 7198 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 7199 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 7200 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 7201 7202 HAL_SRNG_RING_ID_PMAC1_ID_END, 7203 }; 7204 7205 /* SRNG registers are split into two groups R0 and R2 */ 7206 #define HAL_SRNG_REG_GRP_R0 0 7207 #define HAL_SRNG_REG_GRP_R2 1 7208 #define HAL_SRNG_NUM_REG_GRP 2 7209 7210 #define HAL_SRNG_NUM_LMACS 3 7211 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 7212 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 7213 HAL_SRNG_RING_ID_LMAC1_ID_START) 7214 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 7215 7216 /* TODO: number of PMACs */ 7217 #define HAL_SRNG_NUM_PMACS 3 7218 #define HAL_SRNG_NUM_DMAC_RINGS \ 7219 (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \ 7220 HAL_SRNG_RING_ID_DMAC_CMN_ID_START) 7221 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \ 7222 HAL_SRNG_RING_ID_PMAC1_ID_START) 7223 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC) 7224 #define HAL_SRNG_RING_ID_MAX \ 7225 (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + HAL_SRNG_NUM_PMAC_RINGS) 7226 7227 #define HAL_RX_MAX_BA_WINDOW 256 7228 7229 #define ATH12K_HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000) 7230 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 7231 7232 /** 7233 * enum hal_reo_cmd_type: Enum for REO command type 7234 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 7235 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 7236 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 7237 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 7238 * earlier with a 'REO_FLUSH_CACHE' command 7239 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 7240 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 7241 */ 7242 enum hal_reo_cmd_type { 7243 HAL_REO_CMD_GET_QUEUE_STATS = 0, 7244 HAL_REO_CMD_FLUSH_QUEUE = 1, 7245 HAL_REO_CMD_FLUSH_CACHE = 2, 7246 HAL_REO_CMD_UNBLOCK_CACHE = 3, 7247 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 7248 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 7249 }; 7250 7251 /** 7252 * enum hal_reo_cmd_status: Enum for execution status of REO command 7253 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 7254 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 7255 * or cache was blocked 7256 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 7257 * invalid queue desc 7258 * @HAL_REO_CMD_RESOURCE_BLOCKED: 7259 * @HAL_REO_CMD_DRAIN: 7260 */ 7261 enum hal_reo_cmd_status { 7262 HAL_REO_CMD_SUCCESS = 0, 7263 HAL_REO_CMD_BLOCKED = 1, 7264 HAL_REO_CMD_FAILED = 2, 7265 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 7266 HAL_REO_CMD_DRAIN = 0xff, 7267 }; 7268 7269 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 7270 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 7271 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 7272 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 7273 7274 /* Interrupt mitigation - timer threshold in us */ 7275 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 7276 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 7277 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 7278 7279 /* WCSS Relative address */ 7280 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 7281 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 7282 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 7283 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000 7284 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000 7285 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000 7286 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000 7287 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 7288 7289 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 7290 7291 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c 7292 7293 /* SW2TCL(x) R0 ring configuration address */ 7294 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020 7295 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240 7296 #define HAL_TCL1_RING_BASE_LSB 0x00000900 7297 #define HAL_TCL1_RING_BASE_MSB 0x00000904 7298 #define HAL_TCL1_RING_ID(sc) (sc->hw_params.regs->hal_tcl1_ring_id) 7299 #define HAL_TCL1_RING_MISC(sc) \ 7300 (sc->hw_params.regs->hal_tcl1_ring_misc) 7301 #define HAL_TCL1_RING_TP_ADDR_LSB(sc) \ 7302 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_lsb) 7303 #define HAL_TCL1_RING_TP_ADDR_MSB(sc) \ 7304 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_msb) 7305 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) \ 7306 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0) 7307 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) \ 7308 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1) 7309 #define HAL_TCL1_RING_MSI1_BASE_LSB(sc) \ 7310 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_lsb) 7311 #define HAL_TCL1_RING_MSI1_BASE_MSB(sc) \ 7312 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_msb) 7313 #define HAL_TCL1_RING_MSI1_DATA(sc) \ 7314 (sc->hw_params.regs->hal_tcl1_ring_msi1_data) 7315 #define HAL_TCL2_RING_BASE_LSB 0x00000978 7316 #define HAL_TCL_RING_BASE_LSB(sc) \ 7317 (sc->hw_params.regs->hal_tcl_ring_base_lsb) 7318 7319 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7320 (HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB) 7321 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7322 (HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB) 7323 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(sc) \ 7324 (HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB) 7325 #define HAL_TCL1_RING_BASE_MSB_OFFSET \ 7326 (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB) 7327 #define HAL_TCL1_RING_ID_OFFSET(sc) \ 7328 (HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB) 7329 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc) \ 7330 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB) 7331 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc) \ 7332 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - HAL_TCL1_RING_BASE_LSB) 7333 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(sc) \ 7334 (HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB) 7335 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(sc) \ 7336 (HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB) 7337 #define HAL_TCL1_RING_MISC_OFFSET(sc) \ 7338 (HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB) 7339 7340 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 7341 #define HAL_TCL1_RING_HP 0x00002000 7342 #define HAL_TCL1_RING_TP 0x00002004 7343 #define HAL_TCL2_RING_HP 0x00002008 7344 #define HAL_TCL_RING_HP 0x00002028 7345 7346 #define HAL_TCL1_RING_TP_OFFSET \ 7347 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 7348 7349 /* TCL STATUS ring address */ 7350 #define HAL_TCL_STATUS_RING_BASE_LSB(sc) \ 7351 (sc->hw_params.regs->hal_tcl_status_ring_base_lsb) 7352 #define HAL_TCL_STATUS_RING_HP 0x00002048 7353 7354 /* PPE2TCL1 Ring address */ 7355 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48 7356 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038 7357 7358 /* WBM PPE Release Ring address */ 7359 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(sc) \ 7360 (sc->hw_params.regs->hal_ppe_rel_ring_base) 7361 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020 7362 7363 /* REO2SW(x) R0 ring configuration address */ 7364 #define HAL_REO1_GEN_ENABLE 0x00000000 7365 #define HAL_REO1_MISC_CTRL_ADDR(sc) \ 7366 (sc->hw_params.regs->hal_reo1_misc_ctrl_addr) 7367 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 7368 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 7369 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 7370 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 7371 #define HAL_REO1_SW_COOKIE_CFG0(sc) \ 7372 (sc->hw_params.regs->hal_reo1_sw_cookie_cfg0) 7373 #define HAL_REO1_SW_COOKIE_CFG1(sc) \ 7374 (sc->hw_params.regs->hal_reo1_sw_cookie_cfg1) 7375 #define HAL_REO1_QDESC_LUT_BASE0(sc) \ 7376 (sc->hw_params.regs->hal_reo1_qdesc_lut_base0) 7377 #define HAL_REO1_QDESC_LUT_BASE1(sc) \ 7378 (sc->hw_params.regs->hal_reo1_qdesc_lut_base1) 7379 #define HAL_REO1_RING_BASE_LSB(sc) \ 7380 (sc->hw_params.regs->hal_reo1_ring_base_lsb) 7381 #define HAL_REO1_RING_BASE_MSB(sc) \ 7382 (sc->hw_params.regs->hal_reo1_ring_base_msb) 7383 #define HAL_REO1_RING_ID(sc) \ 7384 (sc->hw_params.regs->hal_reo1_ring_id) 7385 #define HAL_REO1_RING_MISC(sc) \ 7386 (sc->hw_params.regs->hal_reo1_ring_misc) 7387 #define HAL_REO1_RING_HP_ADDR_LSB(sc) \ 7388 (sc->hw_params.regs->hal_reo1_ring_hp_addr_lsb) 7389 #define HAL_REO1_RING_HP_ADDR_MSB(sc) \ 7390 (sc->hw_params.regs->hal_reo1_ring_hp_addr_msb) 7391 #define HAL_REO1_RING_PRODUCER_INT_SETUP(sc) \ 7392 (sc->hw_params.regs->hal_reo1_ring_producer_int_setup) 7393 #define HAL_REO1_RING_MSI1_BASE_LSB(sc) \ 7394 (sc->hw_params.regs->hal_reo1_ring_msi1_base_lsb) 7395 #define HAL_REO1_RING_MSI1_BASE_MSB(sc) \ 7396 (sc->hw_params.regs->hal_reo1_ring_msi1_base_msb) 7397 #define HAL_REO1_RING_MSI1_DATA(sc) \ 7398 (sc->hw_params.regs->hal_reo1_ring_msi1_data) 7399 #define HAL_REO2_RING_BASE_LSB(sc) \ 7400 (sc->hw_params.regs->hal_reo2_ring_base) 7401 #define HAL_REO1_AGING_THRESH_IX_0(sc) \ 7402 (sc->hw_params.regs->hal_reo1_aging_thres_ix0) 7403 #define HAL_REO1_AGING_THRESH_IX_1(sc) \ 7404 (sc->hw_params.regs->hal_reo1_aging_thres_ix1) 7405 #define HAL_REO1_AGING_THRESH_IX_2(sc) \ 7406 (sc->hw_params.regs->hal_reo1_aging_thres_ix2) 7407 #define HAL_REO1_AGING_THRESH_IX_3(sc) \ 7408 (sc->hw_params.regs->hal_reo1_aging_thres_ix3) 7409 7410 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7411 (HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7412 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7413 (HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7414 #define HAL_REO1_RING_MSI1_DATA_OFFSET(sc) \ 7415 (HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7416 #define HAL_REO1_RING_BASE_MSB_OFFSET(sc) \ 7417 (HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7418 #define HAL_REO1_RING_ID_OFFSET(sc) \ 7419 (HAL_REO1_RING_ID(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7420 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc) \ 7421 (HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7422 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc) \ 7423 (HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7424 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc) \ 7425 (HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7426 #define HAL_REO1_RING_MISC_OFFSET(sc) \ 7427 (HAL_REO1_RING_MISC(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7428 7429 /* REO2SW(x) R2 ring pointers (head/tail) address */ 7430 #define HAL_REO1_RING_HP 0x00003048 7431 #define HAL_REO1_RING_TP 0x0000304c 7432 #define HAL_REO2_RING_HP 0x00003050 7433 7434 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 7435 7436 /* REO2SW0 ring configuration address */ 7437 #define HAL_REO_SW0_RING_BASE_LSB(sc) \ 7438 ((sc)->hw_params.regs->hal_reo2_sw0_ring_base) 7439 7440 /* REO2SW0 R2 ring pointer (head/tail) address */ 7441 #define HAL_REO_SW0_RING_HP 0x00003088 7442 7443 /* REO CMD R0 address */ 7444 #define HAL_REO_CMD_RING_BASE_LSB(sc) \ 7445 (sc->hw_params.regs->hal_reo_cmd_ring_base) 7446 7447 /* REO CMD R2 address */ 7448 #define HAL_REO_CMD_HP 0x00003020 7449 7450 /* SW2REO R0 address */ 7451 #define HAL_SW2REO_RING_BASE_LSB(sc) \ 7452 (sc->hw_params.regs->hal_sw2reo_ring_base) 7453 #define HAL_SW2REO1_RING_BASE_LSB(sc) \ 7454 (sc->hw_params.regs->hal_sw2reo1_ring_base) 7455 7456 /* SW2REO R2 address */ 7457 #define HAL_SW2REO_RING_HP 0x00003028 7458 #define HAL_SW2REO1_RING_HP 0x00003030 7459 7460 /* CE ring R0 address */ 7461 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000 7462 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 7463 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 7464 #define HAL_CE_DST_RING_CTRL 0x000000b0 7465 7466 /* CE ring R2 address */ 7467 #define HAL_CE_DST_RING_HP 0x00000400 7468 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 7469 7470 /* REO status address */ 7471 #define HAL_REO_STATUS_RING_BASE_LSB(sc) \ 7472 (sc->hw_params.regs->hal_reo_status_ring_base) 7473 #define HAL_REO_STATUS_HP 0x000030a8 7474 7475 /* WBM Idle R0 address */ 7476 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc) \ 7477 (sc->hw_params.regs->hal_wbm_idle_ring_base_lsb) 7478 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(sc) \ 7479 (sc->hw_params.regs->hal_wbm_idle_ring_misc_addr) 7480 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(sc) \ 7481 (sc->hw_params.regs->hal_wbm_r0_idle_list_cntl_addr) 7482 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(sc) \ 7483 (sc->hw_params.regs->hal_wbm_r0_idle_list_size_addr) 7484 #define HAL_WBM_SCATTERED_RING_BASE_LSB(sc) \ 7485 (sc->hw_params.regs->hal_wbm_scattered_ring_base_lsb) 7486 #define HAL_WBM_SCATTERED_RING_BASE_MSB(sc) \ 7487 (sc->hw_params.regs->hal_wbm_scattered_ring_base_msb) 7488 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(sc) \ 7489 (sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix0) 7490 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(sc) \ 7491 (sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix1) 7492 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(sc) \ 7493 (sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix0) 7494 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(sc) \ 7495 (sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix1) 7496 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(sc) \ 7497 (sc->hw_params.regs->hal_wbm_scattered_desc_ptr_hp_addr) 7498 7499 /* WBM Idle R2 address */ 7500 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8 7501 7502 /* SW2WBM R0 release address */ 7503 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(sc) \ 7504 (sc->hw_params.regs->hal_wbm_sw_release_ring_base_lsb) 7505 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(sc) \ 7506 (sc->hw_params.regs->hal_wbm_sw1_release_ring_base_lsb) 7507 7508 /* SW2WBM R2 release address */ 7509 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010 7510 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018 7511 7512 /* WBM2SW R0 release address */ 7513 #define HAL_WBM0_RELEASE_RING_BASE_LSB(sc) \ 7514 (sc->hw_params.regs->hal_wbm0_release_ring_base_lsb) 7515 7516 #define HAL_WBM1_RELEASE_RING_BASE_LSB(sc) \ 7517 (sc->hw_params.regs->hal_wbm1_release_ring_base_lsb) 7518 7519 /* WBM2SW R2 release address */ 7520 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8 7521 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0 7522 7523 /* WBM cookie config address and mask */ 7524 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040 7525 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044 7526 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090 7527 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094 7528 7529 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 7530 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 7531 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 7532 #define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18) 7533 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0) 7534 #define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1) 7535 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3) 7536 7537 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1) 7538 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2) 7539 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3) 7540 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4) 7541 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5) 7542 #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8) 7543 7544 /* TCL ring field mask and offset */ 7545 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7546 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7547 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7548 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0) 7549 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 7550 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 7551 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 7552 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 7553 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 7554 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 7555 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 7556 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 7557 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7558 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7559 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23) 7560 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 7561 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 7562 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 7563 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 7564 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 7565 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 7566 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 7567 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 7568 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 7569 7570 /* REO ring field mask and offset */ 7571 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7572 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7573 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 7574 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7575 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 7576 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 7577 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 7578 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 7579 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 7580 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 7581 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7582 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7583 #define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17) 7584 #define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21) 7585 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 7586 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 7587 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 7588 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 7589 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 7590 #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18) 7591 #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19) 7592 #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20) 7593 7594 /* CE ring bit field mask and shift */ 7595 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 7596 7597 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 7598 7599 #define HAL_ADDR_MSB_REG_SHIFT 32 7600 7601 /* WBM ring bit field mask and shift */ 7602 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 7603 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 7604 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 7605 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 7606 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 7607 7608 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 7609 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 7610 7611 #define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6) 7612 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0) 7613 7614 #define BASE_ADDR_MATCH_TAG_VAL 0x5 7615 7616 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 7617 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff 7618 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 7619 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 7620 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7621 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 7622 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 7623 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7624 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 7625 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 7626 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7627 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff 7628 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 7629 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 7630 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 7631 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff 7632 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 7633 7634 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 7635 7636 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 7637 7638 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 7639 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 7640 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 7641 7642 struct ath12k_buffer_addr { 7643 uint32_t info0; 7644 uint32_t info1; 7645 } __packed; 7646 7647 /* ath12k_buffer_addr 7648 * 7649 * info0 7650 * Address (lower 32 bits) of the msdu buffer or msdu extension 7651 * descriptor or Link descriptor 7652 * 7653 * addr 7654 * Address (upper 8 bits) of the msdu buffer or msdu extension 7655 * descriptor or Link descriptor 7656 * 7657 * return_buffer_manager (RBM) 7658 * Consumer: WBM 7659 * Producer: SW/FW 7660 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 7661 * descriptor or link descriptor that is being pointed to shall be 7662 * returned after the frame has been processed. It is used by WBM 7663 * for routing purposes. 7664 * 7665 * Values are defined in enum %HAL_RX_BUF_RBM_ 7666 * 7667 * sw_buffer_cookie 7668 * Cookie field exclusively used by SW. HW ignores the contents, 7669 * accept that it passes the programmed value on to other 7670 * descriptors together with the physical address. 7671 * 7672 * Field can be used by SW to for example associate the buffers 7673 * physical address with the virtual address. 7674 */ 7675 7676 enum hal_tlv_tag { 7677 HAL_MACTX_CBF_START = 0 /* 0x0 */, 7678 HAL_PHYRX_DATA = 1 /* 0x1 */, 7679 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 7680 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 7681 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 7682 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 7683 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 7684 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 7685 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 7686 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 7687 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 7688 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 7689 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 7690 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 7691 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 7692 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 7693 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 7694 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 7695 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 7696 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 7697 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 7698 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 7699 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 7700 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 7701 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 7702 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 7703 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 7704 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 7705 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 7706 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 7707 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 7708 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 7709 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 7710 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 7711 HAL_MACTX_PKT_END = 34 /* 0x22 */, 7712 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 7713 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 7714 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 7715 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 7716 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 7717 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 7718 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 7719 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 7720 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 7721 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 7722 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 7723 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 7724 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 7725 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 7726 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 7727 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 7728 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 7729 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 7730 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 7731 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 7732 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 7733 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 7734 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 7735 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 7736 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 7737 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 7738 HAL_MACTX_SERVICE = 61 /* 0x3d */, 7739 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 7740 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 7741 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 7742 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 7743 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 7744 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 7745 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 7746 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 7747 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 7748 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 7749 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 7750 HAL_MACTX_DEBUG = 73 /* 0x49 */, 7751 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 7752 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 7753 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 7754 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 7755 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 7756 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 7757 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 7758 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 7759 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 7760 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 7761 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 7762 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 7763 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 7764 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 7765 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 7766 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 7767 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 7768 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 7769 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 7770 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 7771 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 7772 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 7773 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 7774 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 7775 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 7776 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 7777 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 7778 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 7779 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 7780 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 7781 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 7782 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 7783 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 7784 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 7785 HAL_COEX_TX_REQ = 108 /* 0x6c */, 7786 HAL_DUMMY = 109 /* 0x6d */, 7787 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 7788 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 7789 HAL_MPDU_LIMIT = 112 /* 0x70 */, 7790 HAL_NA_LENGTH_END = 113 /* 0x71 */, 7791 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 7792 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 7793 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 7794 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 7795 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 7796 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 7797 HAL_PDG_RESPONSE = 120 /* 0x78 */, 7798 HAL_PDG_TX_REQ = 121 /* 0x79 */, 7799 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 7800 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 7801 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 7802 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 7803 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 7804 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 7805 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 7806 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 7807 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 7808 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 7809 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 7810 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 7811 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 7812 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 7813 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 7814 HAL_TX_DATA = 137 /* 0x89 */, 7815 HAL_TX_FES_SETUP = 138 /* 0x8a */, 7816 HAL_RX_PACKET = 139 /* 0x8b */, 7817 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 7818 HAL_TX_MPDU_END = 141 /* 0x8d */, 7819 HAL_TX_MPDU_START = 142 /* 0x8e */, 7820 HAL_TX_MSDU_END = 143 /* 0x8f */, 7821 HAL_TX_MSDU_START = 144 /* 0x90 */, 7822 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 7823 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 7824 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 7825 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 7826 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 7827 HAL_MPDU_INFO = 150 /* 0x96 */, 7828 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 7829 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 7830 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 7831 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 7832 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 7833 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 7834 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 7835 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 7836 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 7837 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 7838 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 7839 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 7840 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 7841 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 7842 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 7843 HAL_TX_FLUSH = 166 /* 0xa6 */, 7844 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 7845 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 7846 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 7847 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 7848 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 7849 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 7850 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 7851 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 7852 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 7853 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 7854 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 7855 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 7856 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 7857 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 7858 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 7859 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 7860 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 7861 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 7862 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 7863 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 7864 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 7865 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 7866 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 7867 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 7868 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 7869 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 7870 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 7871 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 7872 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 7873 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 7874 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 7875 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 7876 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 7877 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 7878 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 7879 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 7880 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 7881 HAL_RX_START_PARAM = 204 /* 0xcc */, 7882 HAL_RX_PPDU_START = 205 /* 0xcd */, 7883 HAL_RX_PPDU_END = 206 /* 0xce */, 7884 HAL_RX_MPDU_START = 207 /* 0xcf */, 7885 HAL_RX_MPDU_END = 208 /* 0xd0 */, 7886 HAL_RX_MSDU_START = 209 /* 0xd1 */, 7887 HAL_RX_MSDU_END = 210 /* 0xd2 */, 7888 HAL_RX_ATTENTION = 211 /* 0xd3 */, 7889 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 7890 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 7891 HAL_RX_HEADER = 214 /* 0xd6 */, 7892 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 7893 HAL_RX_FLUSH = 216 /* 0xd8 */, 7894 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 7895 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 7896 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 7897 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 7898 HAL_TX_CBF_INFO = 221 /* 0xdd */, 7899 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 7900 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 7901 HAL_RX_PM_INFO = 224 /* 0xe0 */, 7902 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 7903 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 7904 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 7905 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 7906 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 7907 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 7908 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 7909 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 7910 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 7911 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 7912 HAL_COEX_TX_RESP = 235 /* 0xeb */, 7913 HAL_COEX_TX_STATUS = 236 /* 0xec */, 7914 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 7915 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 7916 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 7917 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 7918 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 7919 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 7920 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 7921 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 7922 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 7923 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 7924 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 7925 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 7926 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 7927 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 7928 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 7929 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 7930 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 7931 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 7932 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 7933 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 7934 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 7935 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 7936 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 7937 HAL_WHO_COMMIT = 260 /* 0x104 */, 7938 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 7939 HAL_WHO_FLUSH = 262 /* 0x106 */, 7940 HAL_WHO_L2_LLC = 263 /* 0x107 */, 7941 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 7942 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 7943 HAL_WHO_L3_INFO = 266 /* 0x10a */, 7944 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 7945 HAL_WHO_L4_INFO = 268 /* 0x10c */, 7946 HAL_WHO_MSDU = 269 /* 0x10d */, 7947 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 7948 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 7949 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 7950 HAL_WHO_PPDU_END = 273 /* 0x111 */, 7951 HAL_WHO_PPDU_START = 274 /* 0x112 */, 7952 HAL_WHO_TSO = 275 /* 0x113 */, 7953 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 7954 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 7955 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 7956 HAL_MPDU_INFO_END = 279 /* 0x117 */, 7957 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 7958 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 7959 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 7960 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 7961 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 7962 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 7963 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 7964 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 7965 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 7966 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 7967 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 7968 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 7969 HAL_WHO_TERMINATE = 292 /* 0x124 */, 7970 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 7971 HAL_TX_CV_DATA = 294 /* 0x126 */, 7972 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 7973 HAL_PPDU_TX_END = 296 /* 0x128 */, 7974 HAL_PROT_TX_END = 297 /* 0x129 */, 7975 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 7976 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 7977 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 7978 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 7979 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 7980 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 7981 HAL_ACK_REPORT = 304 /* 0x130 */, 7982 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 7983 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 7984 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 7985 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 7986 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 7987 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 7988 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 7989 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 7990 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 7991 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 7992 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 7993 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 7994 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 7995 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 7996 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 7997 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 7998 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 7999 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 8000 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 8001 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 8002 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 8003 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 8004 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 8005 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 8006 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 8007 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 8008 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 8009 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 8010 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 8011 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 8012 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 8013 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 8014 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 8015 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 8016 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 8017 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 8018 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 8019 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 8020 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 8021 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 8022 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 8023 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 8024 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 8025 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 8026 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 8027 HAL_RX_RING_MASK = 350 /* 0x15e */, 8028 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 8029 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 8030 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 8031 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 8032 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 8033 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 8034 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 8035 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 8036 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 8037 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 8038 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 8039 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 8040 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 8041 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 8042 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 8043 HAL_HT_SIG_INFO = 366 /* 0x16e */, 8044 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 8045 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 8046 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 8047 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 8048 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 8049 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 8050 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 8051 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 8052 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 8053 HAL_SERVICE_INFO = 376 /* 0x178 */, 8054 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 8055 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 8056 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 8057 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 8058 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 8059 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 8060 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 8061 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 8062 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 8063 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 8064 HAL_SCHEDULER_END = 387 /* 0x183 */, 8065 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 8066 HAL_SW_PEER_INFO = 389 /* 0x185 */, 8067 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 8068 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 8069 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 8070 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 8071 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 8072 HAL_CCE_RULE = 395 /* 0x18b */, 8073 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 8074 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 8075 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 8076 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 8077 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 8078 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 8079 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 8080 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 8081 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 8082 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 8083 HAL_CE_SRC_DESC = 406 /* 0x196 */, 8084 HAL_CE_STAT_DESC = 407 /* 0x197 */, 8085 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 8086 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 8087 HAL_CMD_PART_0_END = 410 /* 0x19a */, 8088 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 8089 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 8090 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 8091 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 8092 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 8093 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 8094 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 8095 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 8096 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 8097 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 8098 HAL_TLV_BASE = 511 /* 0x1ff */, 8099 }; 8100 8101 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 8102 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 8103 #define HAL_TLV_USR_ID GENMASK(31, 26) 8104 8105 #define HAL_TLV_ALIGN 4 8106 8107 struct hal_tlv_hdr { 8108 uint32_t tl; 8109 uint8_t value[]; 8110 } __packed; 8111 8112 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1) 8113 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10) 8114 8115 struct hal_tlv_64_hdr { 8116 uint64_t tl; 8117 uint8_t value[]; 8118 } __packed; 8119 8120 #define RX_MPDU_DESC_INFO0_MSDU_COUNT 0xff 8121 #define RX_MPDU_DESC_INFO0_SEQ_NUM 0xfff00 8122 #define RX_MPDU_DESC_INFO0_FRAG_FLAG (1 << 20) 8123 #define RX_MPDU_DESC_INFO0_MPDU_RETRY (1 << 21) 8124 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG (1 << 22) 8125 #define RX_MPDU_DESC_INFO0_BAR_FRAME (1 << 23) 8126 #define RX_MPDU_DESC_INFO0_VALID_PN (1 << 24) 8127 #define RX_MPDU_DESC_INFO0_VALID_SA (1 << 25) 8128 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 26) 8129 #define RX_MPDU_DESC_INFO0_VALID_DA (1 << 27) 8130 #define RX_MPDU_DESC_INFO0_DA_MCBC (1 << 28) 8131 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 29) 8132 #define RX_MPDU_DESC_INFO0_RAW_MPDU (1 << 30) 8133 8134 #define RX_MPDU_DESC_META_DATA_PEER_ID 0xffff 8135 8136 struct rx_mpdu_desc { 8137 uint32_t info0; /* %RX_MPDU_DESC_INFO */ 8138 uint32_t meta_data; 8139 } __packed; 8140 8141 /* rx_mpdu_desc 8142 * Producer: RXDMA 8143 * Consumer: REO/SW/FW 8144 * 8145 * msdu_count 8146 * The number of MSDUs within the MPDU 8147 * 8148 * mpdu_sequence_number 8149 * The field can have two different meanings based on the setting 8150 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 8151 * start sequence number from the BAR frame otherwise it means 8152 * the MPDU sequence number of the received frame. 8153 * 8154 * fragment_flag 8155 * When set, this MPDU is a fragment and REO should forward this 8156 * fragment MPDU to the REO destination ring without any reorder 8157 * checks, pn checks or bitmap update. This implies that REO is 8158 * forwarding the pointer to the MSDU link descriptor. 8159 * 8160 * mpdu_retry_bit 8161 * The retry bit setting from the MPDU header of the received frame 8162 * 8163 * ampdu_flag 8164 * Indicates the MPDU was received as part of an A-MPDU. 8165 * 8166 * bar_frame 8167 * Indicates the received frame is a BAR frame. After processing, 8168 * this frame shall be pushed to SW or deleted. 8169 * 8170 * valid_pn 8171 * When not set, REO will not perform a PN sequence number check. 8172 * 8173 * valid_sa 8174 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 8175 * 8176 * sa_idx_timeout 8177 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 8178 * MAC source address search due to the expiration of search timer. 8179 * 8180 * valid_da 8181 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 8182 * 8183 * da_mcbc 8184 * Field Only valid if valid_da is set. Indicates at least one of 8185 * the DA addresses is a Multicast or Broadcast address. 8186 * 8187 * da_idx_timeout 8188 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 8189 * MAC destination address search due to the expiration of search 8190 * timer. 8191 * 8192 * raw_mpdu 8193 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 8194 * the contents in the MSDU buffer contains a 'RAW' MPDU. 8195 */ 8196 8197 enum hal_rx_msdu_desc_reo_dest_ind { 8198 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 8199 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 8200 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 8201 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 8202 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 8203 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 8204 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 8205 }; 8206 8207 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU (1 << 0) 8208 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU (1 << 1) 8209 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION (1 << 2) 8210 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 8211 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 8212 #define RX_MSDU_DESC_INFO0_MSDU_DROP (1 << 22) 8213 #define RX_MSDU_DESC_INFO0_VALID_SA (1 << 23) 8214 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 24) 8215 #define RX_MSDU_DESC_INFO0_VALID_DA (1 << 25) 8216 #define RX_MSDU_DESC_INFO0_DA_MCBC (1 << 26) 8217 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 27) 8218 8219 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 8220 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 8221 8222 struct rx_msdu_desc { 8223 uint32_t info0; 8224 uint32_t rsvd0; 8225 } __packed; 8226 8227 /* rx_msdu_desc 8228 * 8229 * first_msdu_in_mpdu 8230 * Indicates first msdu in mpdu. 8231 * 8232 * last_msdu_in_mpdu 8233 * Indicates last msdu in mpdu. This flag can be true only when 8234 * 'Msdu_continuation' set to 0. This implies that when an msdu 8235 * is spread out over multiple buffers and thus msdu_continuation 8236 * is set, only for the very last buffer of the msdu, can the 8237 * 'last_msdu_in_mpdu' be set. 8238 * 8239 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 8240 * the MPDU that this MSDU belongs to only contains a single MSDU. 8241 * 8242 * msdu_continuation 8243 * When set, this MSDU buffer was not able to hold the entire MSDU. 8244 * The next buffer will therefore contain additional information 8245 * related to this MSDU. 8246 * 8247 * msdu_length 8248 * Field is only valid in combination with the 'first_msdu_in_mpdu' 8249 * being set. Full MSDU length in bytes after decapsulation. This 8250 * field is still valid for MPDU frames without A-MSDU. It still 8251 * represents MSDU length after decapsulation Or in case of RAW 8252 * MPDUs, it indicates the length of the entire MPDU (without FCS 8253 * field). 8254 * 8255 * reo_destination_indication 8256 * The id of the reo exit ring where the msdu frame shall push 8257 * after (MPDU level) reordering has finished. Values are defined 8258 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 8259 * 8260 * msdu_drop 8261 * Indicates that REO shall drop this MSDU and not forward it to 8262 * any other ring. 8263 * 8264 * valid_sa 8265 * Indicates OLE found a valid SA entry for this MSDU. 8266 * 8267 * sa_idx_timeout 8268 * Indicates, an unsuccessful MAC source address search due to 8269 * the expiration of search timer for this MSDU. 8270 * 8271 * valid_da 8272 * When set, OLE found a valid DA entry for this MSDU. 8273 * 8274 * da_mcbc 8275 * Field Only valid if valid_da is set. Indicates the DA address 8276 * is a Multicast or Broadcast address for this MSDU. 8277 * 8278 * da_idx_timeout 8279 * Indicates, an unsuccessful MAC destination address search due 8280 * to the expiration of search timer for this MSDU. 8281 */ 8282 8283 struct ath12k_rx_msdu_desc { 8284 uint32_t info0; 8285 } __packed; 8286 8287 /* rx_msdu_desc 8288 * 8289 * first_msdu_in_mpdu 8290 * Indicates first msdu in mpdu. 8291 * 8292 * last_msdu_in_mpdu 8293 * Indicates last msdu in mpdu. This flag can be true only when 8294 * 'Msdu_continuation' set to 0. This implies that when an msdu 8295 * is spread out over multiple buffers and thus msdu_continuation 8296 * is set, only for the very last buffer of the msdu, can the 8297 * 'last_msdu_in_mpdu' be set. 8298 * 8299 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 8300 * the MPDU that this MSDU belongs to only contains a single MSDU. 8301 * 8302 * msdu_continuation 8303 * When set, this MSDU buffer was not able to hold the entire MSDU. 8304 * The next buffer will therefore contain additional information 8305 * related to this MSDU. 8306 * 8307 * msdu_length 8308 * Field is only valid in combination with the 'first_msdu_in_mpdu' 8309 * being set. Full MSDU length in bytes after decapsulation. This 8310 * field is still valid for MPDU frames without A-MSDU. It still 8311 * represents MSDU length after decapsulation Or in case of RAW 8312 * MPDUs, it indicates the length of the entire MPDU (without FCS 8313 * field). 8314 * 8315 * msdu_drop 8316 * Indicates that REO shall drop this MSDU and not forward it to 8317 * any other ring. 8318 * 8319 * valid_sa 8320 * Indicates OLE found a valid SA entry for this MSDU. 8321 * 8322 * valid_da 8323 * When set, OLE found a valid DA entry for this MSDU. 8324 * 8325 * da_mcbc 8326 * Field Only valid if valid_da is set. Indicates the DA address 8327 * is a Multicast or Broadcast address for this MSDU. 8328 * 8329 * l3_header_padding_msb 8330 * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as 8331 * the LSB is always zero). Number of bytes padded to make sure 8332 * that the L3 header will always start of a Dword boundary 8333 * 8334 * tcp_udp_checksum_fail 8335 * Passed on from 'RX_ATTENTION' TLV 8336 * Indicates that the computed checksum did not match the checksum 8337 * in the TCP/UDP header. 8338 * 8339 * ip_checksum_fail 8340 * Passed on from 'RX_ATTENTION' TLV 8341 * Indicates that the computed checksum did not match the checksum 8342 * in the IP header. 8343 * 8344 * from_DS 8345 * Set if the 'from DS' bit is set in the frame control. 8346 * 8347 * to_DS 8348 * Set if the 'to DS' bit is set in the frame control. 8349 * 8350 * intra_bss 8351 * This packet needs intra-BSS routing by SW as the 'vdev_id' 8352 * for the destination is the same as the 'vdev_id' that this 8353 * MSDU was got in. 8354 * 8355 * dest_chip_id 8356 * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 8357 * to support intra-BSS routing with multi-chip multi-link operation. 8358 * This indicates into which chip's TCL the packet should be queued. 8359 * 8360 * decap_format 8361 * Indicates the format after decapsulation: 8362 */ 8363 8364 8365 enum hal_reo_dest_ring_buffer_type { 8366 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 8367 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 8368 }; 8369 8370 enum hal_reo_dest_ring_push_reason { 8371 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 8372 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 8373 }; 8374 8375 enum hal_reo_dest_ring_error_code { 8376 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 8377 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 8378 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 8379 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 8380 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 8381 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 8382 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 8383 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 8384 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 8385 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 8386 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 8387 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 8388 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 8389 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 8390 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 8391 HAL_REO_DEST_RING_ERROR_CODE_MAX, 8392 }; 8393 8394 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8395 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE (1 << 8) 8396 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 8397 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 8398 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 8399 8400 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID (1 << 0) 8401 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 8402 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 8403 8404 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 8405 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 8406 8407 struct hal_reo_dest_ring { 8408 struct ath12k_buffer_addr buf_addr_info; 8409 struct rx_mpdu_desc rx_mpdu_info; 8410 struct rx_msdu_desc rx_msdu_info; 8411 uint32_t queue_addr_lo; 8412 uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */ 8413 uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */ 8414 uint32_t rsvd0; 8415 uint32_t rsvd1; 8416 uint32_t rsvd2; 8417 uint32_t rsvd3; 8418 uint32_t rsvd4; 8419 uint32_t rsvd5; 8420 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8421 } __packed; 8422 8423 /* hal_reo_dest_ring 8424 * 8425 * Producer: RXDMA 8426 * Consumer: REO/SW/FW 8427 * 8428 * buf_addr_info 8429 * Details of the physical address of a buffer or MSDU 8430 * link descriptor. 8431 * 8432 * rx_mpdu_info 8433 * General information related to the MPDU that is passed 8434 * on from REO entrance ring to the REO destination ring. 8435 * 8436 * rx_msdu_info 8437 * General information related to the MSDU that is passed 8438 * on from RXDMA all the way to the REO destination ring. 8439 * 8440 * queue_addr_lo 8441 * Address (lower 32 bits) of the REO queue descriptor. 8442 * 8443 * queue_addr_hi 8444 * Address (upper 8 bits) of the REO queue descriptor. 8445 * 8446 * buffer_type 8447 * Indicates the type of address provided in the buf_addr_info. 8448 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8449 * 8450 * push_reason 8451 * Reason for pushing this frame to this exit ring. Values are 8452 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8453 * 8454 * error_code 8455 * Valid only when 'push_reason' is set. All error codes are 8456 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 8457 * 8458 * rx_queue_num 8459 * Indicates the REO MPDU reorder queue id from which this frame 8460 * originated. 8461 * 8462 * reorder_info_valid 8463 * When set, REO has been instructed to not perform the actual 8464 * re-ordering of frames for this queue, but just to insert 8465 * the reorder opcodes. 8466 * 8467 * reorder_opcode 8468 * Field is valid when 'reorder_info_valid' is set. This field is 8469 * always valid for debug purpose as well. 8470 * 8471 * reorder_slot_idx 8472 * Valid only when 'reorder_info_valid' is set. 8473 * 8474 * ring_id 8475 * The buffer pointer ring id. 8476 * 0 - Idle ring 8477 * 1 - N refers to other rings. 8478 * 8479 * looping_count 8480 * Indicates the number of times the producer of entries into 8481 * this ring has looped around the ring. 8482 */ 8483 8484 struct ath12k_hal_reo_dest_ring { 8485 struct ath12k_buffer_addr buf_addr_info; 8486 struct rx_mpdu_desc rx_mpdu_info; 8487 struct ath12k_rx_msdu_desc rx_msdu_info; 8488 uint32_t buf_va_lo; 8489 uint32_t buf_va_hi; 8490 uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */ 8491 } __packed; 8492 8493 /* hal_reo_dest_ring 8494 * 8495 * Producer: RXDMA 8496 * Consumer: REO/SW/FW 8497 * 8498 * buf_addr_info 8499 * Details of the physical address of a buffer or MSDU 8500 * link descriptor. 8501 * 8502 * rx_mpdu_info 8503 * General information related to the MPDU that is passed 8504 * on from REO entrance ring to the REO destination ring. 8505 * 8506 * rx_msdu_info 8507 * General information related to the MSDU that is passed 8508 * on from RXDMA all the way to the REO destination ring. 8509 * 8510 * buf_va_lo 8511 * Field only valid if Reo_dest_buffer_type is set to 8512 * MSDU_buf_address. 8513 * Lower 32 bits of the 64-bit virtual address corresponding 8514 * to Buf_or_link_desc_addr_info 8515 * 8516 * buf_va_hi 8517 * Address (upper 32 bits) of the REO queue descriptor. 8518 * Upper 32 bits of the 64-bit virtual address corresponding 8519 * to Buf_or_link_desc_addr_info 8520 * 8521 * buffer_type 8522 * Indicates the type of address provided in the buf_addr_info. 8523 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8524 * 8525 * push_reason 8526 * Reason for pushing this frame to this exit ring. Values are 8527 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8528 * 8529 * error_code 8530 * Valid only when 'push_reason' is set. All error codes are 8531 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 8532 * 8533 * captured_msdu_data_size 8534 * The number of following REO_DESTINATION STRUCTs that have 8535 * been replaced with msdu_data extracted from the msdu_buffer 8536 * and copied into the ring for easy FW/SW access. 8537 * 8538 * sw_exception 8539 * This field has the same setting as the SW_exception field 8540 * in the corresponding REO_entrance_ring descriptor. 8541 * When set, the REO entrance descriptor is generated by FW, 8542 * and the MPDU was processed in the following way: 8543 * - NO re-order function is needed. 8544 * - MPDU delinking is determined by the setting of Entrance 8545 * ring field: SW_exception_mpdu_delink 8546 * - Destination ring selection is based on the setting of 8547 * the Entrance ring field SW_exception_destination _ring_valid 8548 * 8549 * src_link_id 8550 * Set to the link ID of the PMAC that received the frame 8551 * 8552 * signature 8553 * Set to value 0x8 when msdu capture mode is enabled for this ring 8554 * 8555 * ring_id 8556 * The buffer pointer ring id. 8557 * 0 - Idle ring 8558 * 1 - N refers to other rings. 8559 * 8560 * looping_count 8561 * Indicates the number of times the producer of entries into 8562 * this ring has looped around the ring. 8563 */ 8564 8565 enum hal_reo_entr_rxdma_ecode { 8566 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 8567 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 8568 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 8569 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 8570 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 8571 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 8572 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 8573 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 8574 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 8575 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 8576 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 8577 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 8578 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 8579 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 8580 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 8581 }; 8582 8583 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8584 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 8585 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 8586 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 8587 8588 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 8589 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 8590 8591 struct hal_reo_entrance_ring { 8592 struct ath12k_buffer_addr buf_addr_info; 8593 struct rx_mpdu_desc rx_mpdu_info; 8594 uint32_t queue_addr_lo; 8595 uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 8596 uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 8597 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8598 } __packed; 8599 8600 /* hal_reo_entrance_ring 8601 * 8602 * Producer: RXDMA 8603 * Consumer: REO 8604 * 8605 * buf_addr_info 8606 * Details of the physical address of a buffer or MSDU 8607 * link descriptor. 8608 * 8609 * rx_mpdu_info 8610 * General information related to the MPDU that is passed 8611 * on from REO entrance ring to the REO destination ring. 8612 * 8613 * queue_addr_lo 8614 * Address (lower 32 bits) of the REO queue descriptor. 8615 * 8616 * queue_addr_hi 8617 * Address (upper 8 bits) of the REO queue descriptor. 8618 * 8619 * mpdu_byte_count 8620 * An approximation of the number of bytes received in this MPDU. 8621 * Used to keeps stats on the amount of data flowing 8622 * through a queue. 8623 * 8624 * reo_destination_indication 8625 * The id of the reo exit ring where the msdu frame shall push 8626 * after (MPDU level) reordering has finished. Values are defined 8627 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 8628 * 8629 * frameless_bar 8630 * Indicates that this REO entrance ring struct contains BAR info 8631 * from a multi TID BAR frame. The original multi TID BAR frame 8632 * itself contained all the REO info for the first TID, but all 8633 * the subsequent TID info and their linkage to the REO descriptors 8634 * is passed down as 'frameless' BAR info. 8635 * 8636 * The only fields valid in this descriptor when this bit is set 8637 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 8638 * bar_frame and peer_meta_data. 8639 * 8640 * rxdma_push_reason 8641 * Reason for pushing this frame to this exit ring. Values are 8642 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8643 * 8644 * rxdma_error_code 8645 * Valid only when 'push_reason' is set. All error codes are 8646 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 8647 * 8648 * ring_id 8649 * The buffer pointer ring id. 8650 * 0 - Idle ring 8651 * 1 - N refers to other rings. 8652 * 8653 * looping_count 8654 * Indicates the number of times the producer of entries into 8655 * this ring has looped around the ring. 8656 */ 8657 8658 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 8659 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 8660 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) 8661 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) 8662 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) 8663 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) 8664 8665 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 8666 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) 8667 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 8668 8669 struct hal_sw_monitor_ring { 8670 struct ath12k_buffer_addr buf_addr_info; 8671 struct rx_mpdu_desc rx_mpdu_info; 8672 struct ath12k_buffer_addr status_buf_addr_info; 8673 uint32_t info0; 8674 uint32_t info1; 8675 } __packed; 8676 8677 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 8678 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 8679 8680 struct hal_reo_cmd_hdr { 8681 uint32_t info0; 8682 } __packed; 8683 8684 8685 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 8686 8687 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 8688 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 8689 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 8690 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 8691 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 8692 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 8693 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 8694 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 8695 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 8696 8697 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ 8698 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 8699 #define HAL_REO_CMD_UPD0_VLD BIT(9) 8700 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 8701 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 8702 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 8703 #define HAL_REO_CMD_UPD0_AC BIT(13) 8704 #define HAL_REO_CMD_UPD0_BAR BIT(14) 8705 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 8706 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 8707 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 8708 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 8709 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 8710 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 8711 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 8712 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 8713 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 8714 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 8715 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 8716 #define HAL_REO_CMD_UPD0_SSN BIT(26) 8717 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 8718 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 8719 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 8720 #define HAL_REO_CMD_UPD0_PN BIT(30) 8721 8722 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */ 8723 #define HAL_REO_CMD_UPD1_VLD BIT(16) 8724 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 8725 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 8726 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 8727 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 8728 #define HAL_REO_CMD_UPD1_BAR BIT(23) 8729 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 8730 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 8731 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 8732 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 8733 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 8734 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 8735 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 8736 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 8737 8738 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */ 8739 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 8740 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 8741 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 8742 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 8743 8744 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 8745 8746 struct ath12k_hal_reo_cmd { 8747 uint32_t addr_lo; 8748 uint32_t flag; 8749 uint32_t upd0; 8750 uint32_t upd1; 8751 uint32_t upd2; 8752 uint32_t pn[4]; 8753 uint16_t rx_queue_num; 8754 uint16_t min_rel; 8755 uint16_t min_fwd; 8756 uint8_t addr_hi; 8757 uint8_t ac_list; 8758 uint8_t blocking_idx; 8759 uint16_t ba_window_size; 8760 uint8_t pn_size; 8761 }; 8762 8763 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8764 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 8765 8766 struct hal_reo_get_queue_stats { 8767 struct hal_reo_cmd_hdr cmd; 8768 uint32_t queue_addr_lo; 8769 uint32_t info0; 8770 uint32_t rsvd0[6]; 8771 uint32_t tlv64_pad; 8772 } __packed; 8773 8774 /* hal_reo_get_queue_stats 8775 * Producer: SW 8776 * Consumer: REO 8777 * 8778 * cmd 8779 * Details for command execution tracking purposes. 8780 * 8781 * queue_addr_lo 8782 * Address (lower 32 bits) of the REO queue descriptor. 8783 * 8784 * queue_addr_hi 8785 * Address (upper 8 bits) of the REO queue descriptor. 8786 * 8787 * clear_stats 8788 * Clear stats settings. When set, Clear the stats after 8789 * generating the status. 8790 * 8791 * Following stats will be cleared. 8792 * Timeout_count 8793 * Forward_due_to_bar_count 8794 * Duplicate_count 8795 * Frames_in_order_count 8796 * BAR_received_count 8797 * MPDU_Frames_processed_count 8798 * MSDU_Frames_processed_count 8799 * Total_processed_byte_count 8800 * Late_receive_MPDU_count 8801 * window_jump_2k 8802 * Hole_count 8803 */ 8804 8805 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 8806 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 8807 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 8808 8809 struct hal_reo_flush_queue { 8810 struct hal_reo_cmd_hdr cmd; 8811 uint32_t desc_addr_lo; 8812 uint32_t info0; 8813 uint32_t rsvd0[6]; 8814 } __packed; 8815 8816 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 8817 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 8818 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 8819 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 8820 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 8821 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 8822 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 8823 8824 struct hal_reo_flush_cache { 8825 struct hal_reo_cmd_hdr cmd; 8826 uint32_t cache_addr_lo; 8827 uint32_t info0; 8828 uint32_t rsvd0[6]; 8829 } __packed; 8830 8831 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 8832 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 8833 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 8834 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 8835 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 8836 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 8837 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 8838 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 8839 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 8840 8841 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 8842 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 8843 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 8844 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 8845 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 8846 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 8847 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 8848 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 8849 8850 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 8851 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 8852 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 8853 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 8854 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 8855 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 8856 8857 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 8858 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 8859 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 8860 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) 8861 8862 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 8863 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 8864 8865 enum hal_encrypt_type { 8866 HAL_ENCRYPT_TYPE_WEP_40, 8867 HAL_ENCRYPT_TYPE_WEP_104, 8868 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 8869 HAL_ENCRYPT_TYPE_WEP_128, 8870 HAL_ENCRYPT_TYPE_TKIP_MIC, 8871 HAL_ENCRYPT_TYPE_WAPI, 8872 HAL_ENCRYPT_TYPE_CCMP_128, 8873 HAL_ENCRYPT_TYPE_OPEN, 8874 HAL_ENCRYPT_TYPE_CCMP_256, 8875 HAL_ENCRYPT_TYPE_GCMP_128, 8876 HAL_ENCRYPT_TYPE_AES_GCMP_256, 8877 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 8878 }; 8879 8880 enum hal_tcl_encap_type { 8881 HAL_TCL_ENCAP_TYPE_RAW, 8882 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 8883 HAL_TCL_ENCAP_TYPE_ETHERNET, 8884 HAL_TCL_ENCAP_TYPE_802_3 = 3, 8885 }; 8886 8887 enum hal_tcl_desc_type { 8888 HAL_TCL_DESC_TYPE_BUFFER, 8889 HAL_TCL_DESC_TYPE_EXT_DESC, 8890 }; 8891 8892 enum hal_wbm_htt_tx_comp_status { 8893 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 8894 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 8895 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 8896 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 8897 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 8898 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 8899 }; 8900 8901 struct hal_tcl_data_cmd { 8902 struct ath12k_buffer_addr buf_addr_info; 8903 uint32_t info0; 8904 uint32_t info1; 8905 uint32_t info2; 8906 uint32_t info3; 8907 uint32_t info4; 8908 uint32_t info5; 8909 } __packed; 8910 8911 /* hal_tcl_data_cmd 8912 * 8913 * buf_addr_info 8914 * Details of the physical address of a buffer or MSDU 8915 * link descriptor. 8916 * 8917 * tcl_cmd_type 8918 * used to select the type of TCL Command descriptor 8919 * 8920 * desc_type 8921 * Indicates the type of address provided in the buf_addr_info. 8922 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8923 * 8924 * bank_id 8925 * used to select one of the TCL register banks for fields removed 8926 * from 'TCL_DATA_CMD' that do not change often within one virtual 8927 * device or a set of virtual devices: 8928 * 8929 * tx_notify_frame 8930 * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. 8931 * 8932 * hdr_length_read_sel 8933 * used to select the per 'encap_type' register set for MSDU header 8934 * read length 8935 * 8936 * buffer_timestamp 8937 * buffer_timestamp_valid 8938 * Frame system entrance timestamp. It shall be filled by first 8939 * module (SW, TCL or TQM) that sees the frames first. 8940 * 8941 * cmd_num 8942 * This number can be used to match against status. 8943 * 8944 * data_length 8945 * MSDU length in case of direct descriptor. Length of link 8946 * extension descriptor in case of Link extension descriptor. 8947 * 8948 * *_checksum_en 8949 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 8950 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 8951 * 8952 * to_fw 8953 * Forward packet to FW along with classification result. The 8954 * packet will not be forward to TQM when this bit is set. 8955 * 1'b0: Use classification result to forward the packet. 8956 * 1'b1: Override classification result & forward packet only to fw 8957 * 8958 * packet_offset 8959 * Packet offset from Metadata in case of direct buffer descriptor. 8960 * 8961 * hlos_tid_overwrite 8962 * 8963 * When set, TCL shall ignore the IP DSCP and VLAN PCP 8964 * fields and use HLOS_TID as the final TID. Otherwise TCL 8965 * shall consider the DSCP and PCP fields as well as HLOS_TID 8966 * and choose a final TID based on the configured priority 8967 * 8968 * flow_override_enable 8969 * TCL uses this to select the flow pointer from the peer table, 8970 * which can be overridden by SW for pre-encrypted raw WiFi packets 8971 * that cannot be parsed for UDP or for other MLO 8972 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4 8973 * or IPv6 header. 8974 * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and 8975 * flow_override fields to select the flow-pointer 8976 * 8977 * who_classify_info_sel 8978 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. 8979 * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the 8980 * peer table in case more than 2 flows are mapped to a single TID. 8981 * 0: To choose Flow 0 and 1 of any TID use this value. 8982 * 1: To choose Flow 2 and 3 of any TID use this value. 8983 * 2: To choose Flow 4 and 5 of any TID use this value. 8984 * 3: To choose Flow 6 and 7 of any TID use this value. 8985 * 8986 * If who_classify_info sel is not in sync with the num_tx_classify_info 8987 * field from address search, then TCL will set 'who_classify_info_sel' 8988 * to 0 use flows 0 and 1. 8989 * 8990 * hlos_tid 8991 * HLOS MSDU priority 8992 * Field is used when HLOS_TID_overwrite is set. 8993 * 8994 * flow_override 8995 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE 8996 * TCL uses this to select the flow pointer from the peer table, 8997 * which can be overridden by SW for pre-encrypted raw WiFi packets 8998 * that cannot be parsed for UDP or for other MLO 8999 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0) 9000 * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1) 9001 * 9002 * pmac_id 9003 * TCL uses this PMAC_ID in address search, i.e, while 9004 * finding matching entry for the packet in AST corresponding 9005 * to given PMAC_ID 9006 * 9007 * If PMAC ID is all 1s (=> value 3), it indicates wildcard 9008 * match for any PMAC 9009 * 9010 * vdev_id 9011 * Virtual device ID to check against the address search entry to 9012 * avoid security issues from transmitting packets from an incorrect 9013 * virtual device 9014 * 9015 * search_index 9016 * The index that will be used for index based address or 9017 * flow search. The field is valid when 'search_type' is 1 or 2. 9018 * 9019 * cache_set_num 9020 * 9021 * Cache set number that should be used to cache the index 9022 * based search results, for address and flow search. This 9023 * value should be equal to LSB four bits of the hash value of 9024 * match data, in case of search index points to an entry which 9025 * may be used in content based search also. The value can be 9026 * anything when the entry pointed by search index will not be 9027 * used for content based search. 9028 * 9029 * index_loop_override 9030 * When set, address search and packet routing is forced to use 9031 * 'search_index' instead of following the register configuration 9032 * selected by Bank_id. 9033 * 9034 * ring_id 9035 * The buffer pointer ring ID. 9036 * 0 refers to the IDLE ring 9037 * 1 - N refers to other rings 9038 * 9039 * looping_count 9040 * 9041 * A count value that indicates the number of times the 9042 * producer of entries into the Ring has looped around the 9043 * ring. 9044 * 9045 * At initialization time, this value is set to 0. On the 9046 * first loop, this value is set to 1. After the max value is 9047 * reached allowed by the number of bits for this field, the 9048 * count value continues with 0 again. 9049 * 9050 * In case SW is the consumer of the ring entries, it can 9051 * use this field to figure out up to where the producer of 9052 * entries has created new entries. This eliminates the need to 9053 * check where the head pointer' of the ring is located once 9054 * the SW starts processing an interrupt indicating that new 9055 * entries have been put into this ring... 9056 * 9057 * Also note that SW if it wants only needs to look at the 9058 * LSB bit of this count value. 9059 */ 9060 9061 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 9062 9063 enum hal_tcl_gse_ctrl { 9064 HAL_TCL_GSE_CTRL_RD_STAT, 9065 HAL_TCL_GSE_CTRL_SRCH_DIS, 9066 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 9067 HAL_TCL_GSE_CTRL_WR_BK_ALL, 9068 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 9069 HAL_TCL_GSE_CTRL_INVAL_ALL, 9070 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 9071 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 9072 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 9073 }; 9074 9075 /* hal_tcl_gse_ctrl 9076 * 9077 * rd_stat 9078 * Report or Read statistics 9079 * srch_dis 9080 * Search disable. Report only Hash. 9081 * wr_bk_single 9082 * Write Back single entry 9083 * wr_bk_all 9084 * Write Back entire cache entry 9085 * inval_single 9086 * Invalidate single cache entry 9087 * inval_all 9088 * Invalidate entire cache 9089 * wr_bk_inval_single 9090 * Write back and invalidate single entry in cache 9091 * wr_bk_inval_all 9092 * Write back and invalidate entire cache 9093 * clr_stat_single 9094 * Clear statistics for single entry 9095 */ 9096 9097 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 9098 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 9099 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 9100 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 9101 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 9102 9103 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 9104 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 9105 9106 struct hal_tcl_gse_cmd { 9107 uint32_t ctrl_buf_addr_lo; 9108 uint32_t info0; 9109 uint32_t meta_data[2]; 9110 uint32_t rsvd0[2]; 9111 uint32_t info1; 9112 } __packed; 9113 9114 /* hal_tcl_gse_cmd 9115 * 9116 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 9117 * Address of a control buffer containing additional info needed 9118 * for this command execution. 9119 * 9120 * gse_ctrl 9121 * GSE control operations. This includes cache operations and table 9122 * entry statistics read/clear operation. Values are defined in 9123 * enum %HAL_TCL_GSE_CTRL. 9124 * 9125 * gse_sel 9126 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 9127 * 0: FSE select 1: ASE select 9128 * 9129 * status_destination_ring_id 9130 * TCL status ring to which the GSE status needs to be send. 9131 * 9132 * swap 9133 * Bit to enable byte swapping of contents of buffer. 9134 * 9135 * meta_data 9136 * Meta data to be returned in the status descriptor 9137 */ 9138 9139 enum hal_tcl_cache_op_res { 9140 HAL_TCL_CACHE_OP_RES_DONE, 9141 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 9142 HAL_TCL_CACHE_OP_RES_TIMEOUT, 9143 }; 9144 9145 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 9146 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 9147 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 9148 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 9149 9150 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 9151 9152 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 9153 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 9154 9155 struct hal_tcl_status_ring { 9156 uint32_t info0; 9157 uint32_t msdu_byte_count; 9158 uint32_t msdu_timestamp; 9159 uint32_t meta_data[2]; 9160 uint32_t info1; 9161 uint32_t rsvd0; 9162 uint32_t info2; 9163 } __packed; 9164 9165 /* hal_tcl_status_ring 9166 * 9167 * gse_ctrl 9168 * GSE control operations. This includes cache operations and table 9169 * entry statistics read/clear operation. Values are defined in 9170 * enum %HAL_TCL_GSE_CTRL. 9171 * 9172 * gse_sel 9173 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 9174 * 0: FSE select 1: ASE select 9175 * 9176 * cache_op_res 9177 * Cache operation result. Values are defined in enum 9178 * %HAL_TCL_CACHE_OP_RES_. 9179 * 9180 * msdu_cnt 9181 * msdu_byte_count 9182 * MSDU count of Entry and MSDU byte count for entry 1. 9183 * 9184 * hash_indx 9185 * Hash value of the entry in case of search failed or disabled. 9186 */ 9187 9188 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 9189 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 9190 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 9191 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 9192 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 9193 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 9194 9195 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 9196 9197 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 9198 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 9199 9200 struct hal_ce_srng_src_desc { 9201 uint32_t buffer_addr_low; 9202 uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 9203 uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 9204 uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 9205 } __packed; 9206 9207 /* 9208 * hal_ce_srng_src_desc 9209 * 9210 * buffer_addr_lo 9211 * LSB 32 bits of the 40 Bit Pointer to the source buffer 9212 * 9213 * buffer_addr_hi 9214 * MSB 8 bits of the 40 Bit Pointer to the source buffer 9215 * 9216 * toeplitz_en 9217 * Enable generation of 32-bit Toeplitz-LFSR hash for 9218 * data transfer. In case of gather field in first source 9219 * ring entry of the gather copy cycle in taken into account. 9220 * 9221 * src_swap 9222 * Treats source memory organization as big-endian. For 9223 * each dword read (4 bytes), the byte 0 is swapped with byte 3 9224 * and byte 1 is swapped with byte 2. 9225 * In case of gather field in first source ring entry of 9226 * the gather copy cycle in taken into account. 9227 * 9228 * dest_swap 9229 * Treats destination memory organization as big-endian. 9230 * For each dword write (4 bytes), the byte 0 is swapped with 9231 * byte 3 and byte 1 is swapped with byte 2. 9232 * In case of gather field in first source ring entry of 9233 * the gather copy cycle in taken into account. 9234 * 9235 * gather 9236 * Enables gather of multiple copy engine source 9237 * descriptors to one destination. 9238 * 9239 * ce_res_0 9240 * Reserved 9241 * 9242 * 9243 * length 9244 * Length of the buffer in units of octets of the current 9245 * descriptor 9246 * 9247 * fw_metadata 9248 * Meta data used by FW. 9249 * In case of gather field in first source ring entry of 9250 * the gather copy cycle in taken into account. 9251 * 9252 * ce_res_1 9253 * Reserved 9254 * 9255 * ce_res_2 9256 * Reserved 9257 * 9258 * ring_id 9259 * The buffer pointer ring ID. 9260 * 0 refers to the IDLE ring 9261 * 1 - N refers to other rings 9262 * Helps with debugging when dumping ring contents. 9263 * 9264 * looping_count 9265 * A count value that indicates the number of times the 9266 * producer of entries into the Ring has looped around the 9267 * ring. 9268 * 9269 * At initialization time, this value is set to 0. On the 9270 * first loop, this value is set to 1. After the max value is 9271 * reached allowed by the number of bits for this field, the 9272 * count value continues with 0 again. 9273 * 9274 * In case SW is the consumer of the ring entries, it can 9275 * use this field to figure out up to where the producer of 9276 * entries has created new entries. This eliminates the need to 9277 * check where the head pointer' of the ring is located once 9278 * the SW starts processing an interrupt indicating that new 9279 * entries have been put into this ring... 9280 * 9281 * Also note that SW if it wants only needs to look at the 9282 * LSB bit of this count value. 9283 */ 9284 9285 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 9286 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 9287 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 9288 9289 struct hal_ce_srng_dest_desc { 9290 uint32_t buffer_addr_low; 9291 uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 9292 } __packed; 9293 9294 /* hal_ce_srng_dest_desc 9295 * 9296 * dst_buffer_low 9297 * LSB 32 bits of the 40 Bit Pointer to the Destination 9298 * buffer 9299 * 9300 * dst_buffer_high 9301 * MSB 8 bits of the 40 Bit Pointer to the Destination 9302 * buffer 9303 * 9304 * ce_res_4 9305 * Reserved 9306 * 9307 * ring_id 9308 * The buffer pointer ring ID. 9309 * 0 refers to the IDLE ring 9310 * 1 - N refers to other rings 9311 * Helps with debugging when dumping ring contents. 9312 * 9313 * looping_count 9314 * A count value that indicates the number of times the 9315 * producer of entries into the Ring has looped around the 9316 * ring. 9317 * 9318 * At initialization time, this value is set to 0. On the 9319 * first loop, this value is set to 1. After the max value is 9320 * reached allowed by the number of bits for this field, the 9321 * count value continues with 0 again. 9322 * 9323 * In case SW is the consumer of the ring entries, it can 9324 * use this field to figure out up to where the producer of 9325 * entries has created new entries. This eliminates the need to 9326 * check where the head pointer' of the ring is located once 9327 * the SW starts processing an interrupt indicating that new 9328 * entries have been put into this ring... 9329 * 9330 * Also note that SW if it wants only needs to look at the 9331 * LSB bit of this count value. 9332 */ 9333 9334 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 9335 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 9336 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 9337 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 9338 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 9339 9340 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 9341 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 9342 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 9343 9344 struct hal_ce_srng_dst_status_desc { 9345 uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 9346 uint32_t toeplitz_hash0; 9347 uint32_t toeplitz_hash1; 9348 uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 9349 } __packed; 9350 9351 /* hal_ce_srng_dst_status_desc 9352 * 9353 * ce_res_5 9354 * Reserved 9355 * 9356 * toeplitz_en 9357 * 9358 * src_swap 9359 * Source memory buffer swapped 9360 * 9361 * dest_swap 9362 * Destination memory buffer swapped 9363 * 9364 * gather 9365 * Gather of multiple copy engine source descriptors to one 9366 * destination enabled 9367 * 9368 * ce_res_6 9369 * Reserved 9370 * 9371 * length 9372 * Sum of all the Lengths of the source descriptor in the 9373 * gather chain 9374 * 9375 * toeplitz_hash_0 9376 * 32 LS bits of 64 bit Toeplitz LFSR hash result 9377 * 9378 * toeplitz_hash_1 9379 * 32 MS bits of 64 bit Toeplitz LFSR hash result 9380 * 9381 * fw_metadata 9382 * Meta data used by FW 9383 * In case of gather field in first source ring entry of 9384 * the gather copy cycle in taken into account. 9385 * 9386 * ce_res_7 9387 * Reserved 9388 * 9389 * ring_id 9390 * The buffer pointer ring ID. 9391 * 0 refers to the IDLE ring 9392 * 1 - N refers to other rings 9393 * Helps with debugging when dumping ring contents. 9394 * 9395 * looping_count 9396 * A count value that indicates the number of times the 9397 * producer of entries into the Ring has looped around the 9398 * ring. 9399 * 9400 * At initialization time, this value is set to 0. On the 9401 * first loop, this value is set to 1. After the max value is 9402 * reached allowed by the number of bits for this field, the 9403 * count value continues with 0 again. 9404 * 9405 * In case SW is the consumer of the ring entries, it can 9406 * use this field to figure out up to where the producer of 9407 * entries has created new entries. This eliminates the need to 9408 * check where the head pointer' of the ring is located once 9409 * the SW starts processing an interrupt indicating that new 9410 * entries have been put into this ring... 9411 * 9412 * Also note that SW if it wants only needs to look at the 9413 * LSB bit of this count value. 9414 */ 9415 9416 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 9417 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 9418 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 9419 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 9420 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 9421 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 9422 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 9423 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 9424 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 9425 9426 enum hal_tx_rate_stats_bw { 9427 HAL_TX_RATE_STATS_BW_20, 9428 HAL_TX_RATE_STATS_BW_40, 9429 HAL_TX_RATE_STATS_BW_80, 9430 HAL_TX_RATE_STATS_BW_160, 9431 }; 9432 9433 enum hal_tx_rate_stats_pkt_type { 9434 HAL_TX_RATE_STATS_PKT_TYPE_11A, 9435 HAL_TX_RATE_STATS_PKT_TYPE_11B, 9436 HAL_TX_RATE_STATS_PKT_TYPE_11N, 9437 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 9438 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 9439 }; 9440 9441 enum hal_tx_rate_stats_sgi { 9442 HAL_TX_RATE_STATS_SGI_08US, 9443 HAL_TX_RATE_STATS_SGI_04US, 9444 HAL_TX_RATE_STATS_SGI_16US, 9445 HAL_TX_RATE_STATS_SGI_32US, 9446 }; 9447 9448 struct hal_tx_rate_stats { 9449 uint32_t info0; 9450 uint32_t tsf; 9451 } __packed; 9452 9453 struct hal_wbm_link_desc { 9454 struct ath12k_buffer_addr buf_addr_info; 9455 } __packed; 9456 9457 /* hal_wbm_link_desc 9458 * 9459 * Producer: WBM 9460 * Consumer: WBM 9461 * 9462 * buf_addr_info 9463 * Details of the physical address of a buffer or MSDU 9464 * link descriptor. 9465 */ 9466 9467 enum hal_wbm_rel_src_module { 9468 HAL_WBM_REL_SRC_MODULE_TQM, 9469 HAL_WBM_REL_SRC_MODULE_RXDMA, 9470 HAL_WBM_REL_SRC_MODULE_REO, 9471 HAL_WBM_REL_SRC_MODULE_FW, 9472 HAL_WBM_REL_SRC_MODULE_SW, 9473 }; 9474 9475 enum hal_wbm_rel_desc_type { 9476 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 9477 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 9478 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 9479 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 9480 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 9481 }; 9482 9483 /* hal_wbm_rel_desc_type 9484 * 9485 * msdu_buffer 9486 * The address points to an MSDU buffer 9487 * 9488 * msdu_link_descriptor 9489 * The address points to an Tx MSDU link descriptor 9490 * 9491 * mpdu_link_descriptor 9492 * The address points to an MPDU link descriptor 9493 * 9494 * msdu_ext_descriptor 9495 * The address points to an MSDU extension descriptor 9496 * 9497 * queue_ext_descriptor 9498 * The address points to an TQM queue extension descriptor. WBM should 9499 * treat this is the same way as a link descriptor. 9500 */ 9501 9502 enum hal_wbm_rel_bm_act { 9503 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 9504 HAL_WBM_REL_BM_ACT_REL_MSDU, 9505 }; 9506 9507 /* hal_wbm_rel_bm_act 9508 * 9509 * put_in_idle_list 9510 * Put the buffer or descriptor back in the idle list. In case of MSDU or 9511 * MDPU link descriptor, BM does not need to check to release any 9512 * individual MSDU buffers. 9513 * 9514 * release_msdu_list 9515 * This BM action can only be used in combination with desc_type being 9516 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 9517 * pointer in the MSDU link descriptor is the first of an MPDU that is 9518 * released. BM shall release all the MSDU buffers linked to this first 9519 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 9520 * set to value 0, which represents the 'NULL' pointer. When all MSDU 9521 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 9522 * descriptor itself shall also be released. 9523 */ 9524 9525 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 9526 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 9527 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 9528 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 9529 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 9530 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 9531 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 9532 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 9533 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 9534 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 9535 9536 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 9537 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 9538 9539 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 9540 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 9541 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 9542 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 9543 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 9544 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 9545 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 9546 9547 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 9548 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 9549 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 9550 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 9551 9552 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 9553 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 9554 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 9555 9556 struct hal_wbm_release_ring { 9557 struct ath12k_buffer_addr buf_addr_info; 9558 uint32_t info0; 9559 uint32_t info1; 9560 uint32_t info2; 9561 struct hal_tx_rate_stats rate_stats; 9562 uint32_t info3; 9563 } __packed; 9564 9565 /* hal_wbm_release_ring 9566 * 9567 * Producer: SW/TQM/RXDMA/REO/SWITCH 9568 * Consumer: WBM/SW/FW 9569 * 9570 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 9571 * for software based completions. 9572 * 9573 * buf_addr_info 9574 * Details of the physical address of the buffer or link descriptor. 9575 * 9576 * release_source_module 9577 * Indicates which module initiated the release of this buffer/descriptor. 9578 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 9579 * 9580 * bm_action 9581 * Field only valid when the field return_buffer_manager in 9582 * Released_buff_or_desc_addr_info indicates: 9583 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 9584 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 9585 * 9586 * buffer_or_desc_type 9587 * Field only valid when WBM is marked as the return_buffer_manager in 9588 * the Released_Buffer_address_info. Indicates that type of buffer or 9589 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 9590 * 9591 * first_msdu_index 9592 * Field only valid for the bm_action release_msdu_list. The index of the 9593 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 9594 * 9595 * tqm_release_reason 9596 * Field only valid when Release_source_module is set to release_source_TQM 9597 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 9598 * 9599 * rxdma_push_reason 9600 * reo_push_reason 9601 * Indicates why rxdma/reo pushed the frame to this ring and values are 9602 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 9603 * 9604 * rxdma_error_code 9605 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 9606 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 9607 * 9608 * reo_error_code 9609 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 9610 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 9611 * 9612 * wbm_internal_error 9613 * Is set when WBM got a buffer pointer but the action was to push it to 9614 * the idle link descriptor ring or do link related activity OR 9615 * Is set when WBM got a link buffer pointer but the action was to push it 9616 * to the buffer descriptor ring. 9617 * 9618 * tqm_status_number 9619 * The value in this field is equal to tqm_cmd_number in TQM command. It is 9620 * used to correlate the statu with TQM commands. Only valid when 9621 * release_source_module is TQM. 9622 * 9623 * transmit_count 9624 * The number of times the frame has been transmitted, valid only when 9625 * release source in TQM. 9626 * 9627 * ack_frame_rssi 9628 * This field is only valid when the source is TQM. If this frame is 9629 * removed as the result of the reception of an ACK or BA, this field 9630 * indicates the RSSI of the received ACK or BA frame. 9631 * 9632 * sw_release_details_valid 9633 * This is set when WMB got a 'release_msdu_list' command from TQM and 9634 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 9635 * and pass them one at a time on to the 'buffer owner'. 9636 * 9637 * first_msdu 9638 * Field only valid when SW_release_details_valid is set. 9639 * When set, this MSDU is the first MSDU pointed to in the 9640 * 'release_msdu_list' command. 9641 * 9642 * last_msdu 9643 * Field only valid when SW_release_details_valid is set. 9644 * When set, this MSDU is the last MSDU pointed to in the 9645 * 'release_msdu_list' command. 9646 * 9647 * msdu_part_of_amsdu 9648 * Field only valid when SW_release_details_valid is set. 9649 * When set, this MSDU was part of an A-MSDU in MPDU 9650 * 9651 * fw_tx_notify_frame 9652 * Field only valid when SW_release_details_valid is set. 9653 * 9654 * buffer_timestamp 9655 * Field only valid when SW_release_details_valid is set. 9656 * This is the Buffer_timestamp field from the 9657 * Timestamp in units of 1024 us 9658 * 9659 * struct hal_tx_rate_stats rate_stats 9660 * Details for command execution tracking purposes. 9661 * 9662 * sw_peer_id 9663 * tid 9664 * Field only valid when Release_source_module is set to 9665 * release_source_TQM 9666 * 9667 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 9668 * not fetched and hence sw_peer_id and tid = 0 9669 * 9670 * buffer_or_desc_type = e_num 0 9671 * MSDU_rel_buffertqm_release_reason = e_num 1 9672 * tqm_rr_rem_cmd_rem 9673 * 9674 * 2) Release of msdu buffer due to Flow is not fetched and 9675 * hence sw_peer_id and tid = 0 9676 * 9677 * buffer_or_desc_type = e_num 0 9678 * MSDU_rel_buffertqm_release_reason = e_num 1 9679 * tqm_rr_rem_cmd_rem 9680 * 9681 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 9682 * command. 9683 * 9684 * buffer_or_desc_type = e_num1 9685 * msdu_link_descriptortqm_release_reason can be:e_num 1 9686 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 9687 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 9688 * 9689 * This field represents the TID from the TX_MSDU_FLOW 9690 * descriptor or TX_MPDU_QUEUE descriptor 9691 * 9692 * rind_id 9693 * For debugging. 9694 * This field is filled in by the SRNG module. 9695 * It help to identify the ring that is being looked 9696 * 9697 * looping_count 9698 * A count value that indicates the number of times the 9699 * producer of entries into the Buffer Manager Ring has looped 9700 * around the ring. 9701 * 9702 * At initialization time, this value is set to 0. On the 9703 * first loop, this value is set to 1. After the max value is 9704 * reached allowed by the number of bits for this field, the 9705 * count value continues with 0 again. 9706 * 9707 * In case SW is the consumer of the ring entries, it can 9708 * use this field to figure out up to where the producer of 9709 * entries has created new entries. This eliminates the need to 9710 * check where the head pointer' of the ring is located once 9711 * the SW starts processing an interrupt indicating that new 9712 * entries have been put into this ring... 9713 * 9714 * Also note that SW if it wants only needs to look at the 9715 * LSB bit of this count value. 9716 */ 9717 9718 /** 9719 * enum hal_wbm_tqm_rel_reason - TQM release reason code 9720 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 9721 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 9722 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 9723 * initiated by sw. 9724 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 9725 * initiated by sw. 9726 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 9727 * mpdus. 9728 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 9729 * fw with fw_reason1. 9730 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 9731 * fw with fw_reason2. 9732 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 9733 * fw with fw_reason3. 9734 */ 9735 enum hal_wbm_tqm_rel_reason { 9736 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 9737 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 9738 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 9739 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 9740 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 9741 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 9742 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 9743 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 9744 }; 9745 9746 struct hal_wbm_buffer_ring { 9747 struct ath12k_buffer_addr buf_addr_info; 9748 }; 9749 9750 enum hal_desc_owner { 9751 HAL_DESC_OWNER_WBM, 9752 HAL_DESC_OWNER_SW, 9753 HAL_DESC_OWNER_TQM, 9754 HAL_DESC_OWNER_RXDMA, 9755 HAL_DESC_OWNER_REO, 9756 HAL_DESC_OWNER_SWITCH, 9757 }; 9758 9759 enum hal_desc_buf_type { 9760 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 9761 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 9762 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 9763 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 9764 HAL_DESC_BUF_TYPE_TX_FLOW, 9765 HAL_DESC_BUF_TYPE_TX_BUFFER, 9766 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 9767 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 9768 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 9769 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 9770 HAL_DESC_BUF_TYPE_RX_BUFFER, 9771 HAL_DESC_BUF_TYPE_IDLE_LINK, 9772 }; 9773 9774 #define HAL_DESC_REO_OWNED 4 9775 #define HAL_DESC_REO_QUEUE_DESC 8 9776 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 9777 #define HAL_DESC_REO_NON_QOS_TID 16 9778 9779 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 9780 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 9781 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 9782 9783 struct hal_desc_header { 9784 uint32_t info0; 9785 } __packed; 9786 9787 struct hal_rx_mpdu_link_ptr { 9788 struct ath12k_buffer_addr addr_info; 9789 } __packed; 9790 9791 struct hal_rx_msdu_details { 9792 struct ath12k_buffer_addr buf_addr_info; 9793 struct rx_msdu_desc rx_msdu_info; 9794 } __packed; 9795 9796 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 9797 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 9798 9799 struct hal_rx_msdu_link { 9800 struct hal_desc_header desc_hdr; 9801 struct ath12k_buffer_addr buf_addr_info; 9802 uint32_t info0; 9803 uint32_t pn[4]; 9804 struct hal_rx_msdu_details msdu_link[6]; 9805 } __packed; 9806 9807 struct hal_rx_reo_queue_ext { 9808 struct hal_desc_header desc_hdr; 9809 uint32_t rsvd; 9810 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 9811 } __packed; 9812 9813 /* hal_rx_reo_queue_ext 9814 * Consumer: REO 9815 * Producer: REO 9816 * 9817 * descriptor_header 9818 * Details about which module owns this struct. 9819 * 9820 * mpdu_link 9821 * Pointer to the next MPDU_link descriptor in the MPDU queue. 9822 */ 9823 9824 enum hal_rx_reo_queue_pn_size { 9825 HAL_RX_REO_QUEUE_PN_SIZE_24, 9826 HAL_RX_REO_QUEUE_PN_SIZE_48, 9827 HAL_RX_REO_QUEUE_PN_SIZE_128, 9828 }; 9829 9830 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 9831 9832 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 9833 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 9834 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 9835 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 9836 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 9837 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 9838 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 9839 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 9840 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 9841 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 9842 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 9843 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 9844 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 9845 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 9846 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 9847 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 9848 9849 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 9850 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 9851 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 9852 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 9853 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 9854 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 9855 9856 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 9857 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 9858 9859 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 9860 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 9861 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 9862 9863 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 9864 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 9865 9866 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 9867 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 9868 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 9869 9870 struct hal_rx_reo_queue { 9871 struct hal_desc_header desc_hdr; 9872 uint32_t rx_queue_num; 9873 uint32_t info0; 9874 uint32_t info1; 9875 uint32_t pn[4]; 9876 uint32_t last_rx_enqueue_timestamp; 9877 uint32_t last_rx_dequeue_timestamp; 9878 uint32_t next_aging_queue[2]; 9879 uint32_t prev_aging_queue[2]; 9880 uint32_t rx_bitmap[8]; 9881 uint32_t info2; 9882 uint32_t info3; 9883 uint32_t info4; 9884 uint32_t processed_mpdus; 9885 uint32_t processed_msdus; 9886 uint32_t processed_total_bytes; 9887 uint32_t info5; 9888 uint32_t rsvd[3]; 9889 struct hal_rx_reo_queue_ext ext_desc[]; 9890 } __packed; 9891 9892 /* hal_rx_reo_queue 9893 * 9894 * descriptor_header 9895 * Details about which module owns this struct. Note that sub field 9896 * Buffer_type shall be set to receive_reo_queue_descriptor. 9897 * 9898 * receive_queue_number 9899 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 9900 * 9901 * vld 9902 * Valid bit indicating a session is established and the queue descriptor 9903 * is valid. 9904 * associated_link_descriptor_counter 9905 * Indicates which of the 3 link descriptor counters shall be incremented 9906 * or decremented when link descriptors are added or removed from this 9907 * flow queue. 9908 * disable_duplicate_detection 9909 * When set, do not perform any duplicate detection. 9910 * soft_reorder_enable 9911 * When set, REO has been instructed to not perform the actual re-ordering 9912 * of frames for this queue, but just to insert the reorder opcodes. 9913 * ac 9914 * Indicates the access category of the queue descriptor. 9915 * bar 9916 * Indicates if BAR has been received. 9917 * retry 9918 * Retry bit is checked if this bit is set. 9919 * chk_2k_mode 9920 * Indicates what type of operation is expected from Reo when the received 9921 * frame SN falls within the 2K window. 9922 * oor_mode 9923 * Indicates what type of operation is expected when the received frame 9924 * falls within the OOR window. 9925 * ba_window_size 9926 * Indicates the negotiated (window size + 1). Max of 256 bits. 9927 * 9928 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 9929 * session, with window size of 0). The 3 values here are the main values 9930 * validated, but other values should work as well. 9931 * 9932 * A BA window size of 0 (=> one frame entry bitmat), means that there is 9933 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 9934 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 9935 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 9936 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 9937 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 9938 * pn_size 9939 * REO shall perform the PN increment check, even number check, uneven 9940 * number check, PN error check and size of the PN field check. 9941 * ignore_ampdu_flag 9942 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 9943 * 9944 * svld 9945 * Sequence number in next field is valid one. 9946 * ssn 9947 * Starting Sequence number of the session. 9948 * current_index 9949 * Points to last forwarded packet 9950 * seq_2k_error_detected_flag 9951 * REO has detected a 2k error jump in the sequence number and from that 9952 * moment forward, all new frames are forwarded directly to FW, without 9953 * duplicate detect, reordering, etc. 9954 * pn_error_detected_flag 9955 * REO has detected a PN error. 9956 */ 9957 9958 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 9959 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 9960 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 9961 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 9962 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 9963 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 9964 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 9965 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 9966 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 9967 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 9968 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 9969 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 9970 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 9971 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 9972 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 9973 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 9974 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 9975 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 9976 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 9977 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 9978 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 9979 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 9980 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 9981 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 9982 9983 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 9984 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 9985 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 9986 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 9987 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 9988 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 9989 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 9990 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 9991 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 9992 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 9993 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 9994 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 9995 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 9996 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 9997 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 9998 9999 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 10000 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 10001 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 10002 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 10003 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 10004 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 10005 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 10006 10007 struct hal_reo_update_rx_queue { 10008 struct hal_reo_cmd_hdr cmd; 10009 uint32_t queue_addr_lo; 10010 uint32_t info0; 10011 uint32_t info1; 10012 uint32_t info2; 10013 uint32_t pn[4]; 10014 } __packed; 10015 10016 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 10017 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 10018 10019 struct hal_reo_unblock_cache { 10020 struct hal_reo_cmd_hdr cmd; 10021 uint32_t info0; 10022 uint32_t rsvd[7]; 10023 } __packed; 10024 10025 enum hal_reo_exec_status { 10026 HAL_REO_EXEC_STATUS_SUCCESS, 10027 HAL_REO_EXEC_STATUS_BLOCKED, 10028 HAL_REO_EXEC_STATUS_FAILED, 10029 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 10030 }; 10031 10032 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 10033 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 10034 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 10035 10036 #define HAL_HASH_ROUTING_RING_TCL 0 10037 #define HAL_HASH_ROUTING_RING_SW1 1 10038 #define HAL_HASH_ROUTING_RING_SW2 2 10039 #define HAL_HASH_ROUTING_RING_SW3 3 10040 #define HAL_HASH_ROUTING_RING_SW4 4 10041 #define HAL_HASH_ROUTING_RING_REL 5 10042 #define HAL_HASH_ROUTING_RING_FW 6 10043 10044 struct hal_reo_status_hdr { 10045 uint32_t info0; 10046 uint32_t timestamp; 10047 } __packed; 10048 10049 /* hal_reo_status_hdr 10050 * Producer: REO 10051 * Consumer: SW 10052 * 10053 * status_num 10054 * The value in this field is equal to value of the reo command 10055 * number. This field helps to correlate the statuses with the REO 10056 * commands. 10057 * 10058 * execution_time (in us) 10059 * The amount of time REO took to execute the command. Note that 10060 * this time does not include the duration of the command waiting 10061 * in the command ring, before the execution started. 10062 * 10063 * execution_status 10064 * Execution status of the command. Values are defined in 10065 * enum %HAL_REO_EXEC_STATUS_. 10066 */ 10067 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 10068 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 10069 10070 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 10071 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 10072 10073 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 10074 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 10075 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 10076 10077 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 10078 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 10079 10080 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 10081 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 10082 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 10083 10084 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 10085 10086 struct hal_reo_get_queue_stats_status { 10087 struct hal_reo_status_hdr hdr; 10088 uint32_t info0; 10089 uint32_t pn[4]; 10090 uint32_t last_rx_enqueue_timestamp; 10091 uint32_t last_rx_dequeue_timestamp; 10092 uint32_t rx_bitmap[8]; 10093 uint32_t info1; 10094 uint32_t info2; 10095 uint32_t info3; 10096 uint32_t num_mpdu_frames; 10097 uint32_t num_msdu_frames; 10098 uint32_t total_bytes; 10099 uint32_t info4; 10100 uint32_t info5; 10101 } __packed; 10102 10103 /* hal_reo_get_queue_stats_status 10104 * Producer: REO 10105 * Consumer: SW 10106 * 10107 * status_hdr 10108 * Details that can link this status with the original command. It 10109 * also contains info on how long REO took to execute this command. 10110 * 10111 * ssn 10112 * Starting Sequence number of the session, this changes whenever 10113 * window moves (can be filled by SW then maintained by REO). 10114 * 10115 * current_index 10116 * Points to last forwarded packet. 10117 * 10118 * pn 10119 * Bits of the PN number. 10120 * 10121 * last_rx_enqueue_timestamp 10122 * last_rx_dequeue_timestamp 10123 * Timestamp of arrival of the last MPDU for this queue and 10124 * Timestamp of forwarding an MPDU accordingly. 10125 * 10126 * rx_bitmap 10127 * When a bit is set, the corresponding frame is currently held 10128 * in the re-order queue. The bitmap is Fully managed by HW. 10129 * 10130 * current_mpdu_count 10131 * current_msdu_count 10132 * The number of MPDUs and MSDUs in the queue. 10133 * 10134 * timeout_count 10135 * The number of times REO started forwarding frames even though 10136 * there is a hole in the bitmap. Forwarding reason is timeout. 10137 * 10138 * forward_due_to_bar_count 10139 * The number of times REO started forwarding frames even though 10140 * there is a hole in the bitmap. Fwd reason is reception of BAR. 10141 * 10142 * duplicate_count 10143 * The number of duplicate frames that have been detected. 10144 * 10145 * frames_in_order_count 10146 * The number of frames that have been received in order (without 10147 * a hole that prevented them from being forwarded immediately). 10148 * 10149 * bar_received_count 10150 * The number of times a BAR frame is received. 10151 * 10152 * mpdu_frames_processed_count 10153 * msdu_frames_processed_count 10154 * The total number of MPDU/MSDU frames that have been processed. 10155 * 10156 * total_bytes 10157 * An approximation of the number of bytes received for this queue. 10158 * 10159 * late_receive_mpdu_count 10160 * The number of MPDUs received after the window had already moved 10161 * on. The 'late' sequence window is defined as 10162 * (Window SSN - 256) - (Window SSN - 1). 10163 * 10164 * window_jump_2k 10165 * The number of times the window moved more than 2K 10166 * 10167 * hole_count 10168 * The number of times a hole was created in the receive bitmap. 10169 * 10170 * looping_count 10171 * A count value that indicates the number of times the producer of 10172 * entries into this Ring has looped around the ring. 10173 */ 10174 10175 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 10176 10177 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 10178 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 10179 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 10180 10181 struct hal_reo_flush_queue_status { 10182 struct hal_reo_status_hdr hdr; 10183 uint32_t info0; 10184 uint32_t rsvd0[21]; 10185 uint32_t info1; 10186 } __packed; 10187 10188 /* hal_reo_flush_queue_status 10189 * Producer: REO 10190 * Consumer: SW 10191 * 10192 * status_hdr 10193 * Details that can link this status with the original command. It 10194 * also contains info on how long REO took to execute this command. 10195 * 10196 * error_detected 10197 * Status of blocking resource 10198 * 10199 * 0 - No error has been detected while executing this command 10200 * 1 - Error detected. The resource to be used for blocking was 10201 * already in use. 10202 * 10203 * looping_count 10204 * A count value that indicates the number of times the producer of 10205 * entries into this Ring has looped around the ring. 10206 */ 10207 10208 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 10209 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 10210 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 10211 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 10212 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 10213 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 10214 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 10215 10216 struct hal_reo_flush_cache_status { 10217 struct hal_reo_status_hdr hdr; 10218 uint32_t info0; 10219 uint32_t rsvd0[21]; 10220 uint32_t info1; 10221 } __packed; 10222 10223 /* hal_reo_flush_cache_status 10224 * Producer: REO 10225 * Consumer: SW 10226 * 10227 * status_hdr 10228 * Details that can link this status with the original command. It 10229 * also contains info on how long REO took to execute this command. 10230 * 10231 * error_detected 10232 * Status for blocking resource handling 10233 * 10234 * 0 - No error has been detected while executing this command 10235 * 1 - An error in the blocking resource management was detected 10236 * 10237 * block_error_details 10238 * only valid when error_detected is set 10239 * 10240 * 0 - No blocking related errors found 10241 * 1 - Blocking resource is already in use 10242 * 2 - Resource requested to be unblocked, was not blocked 10243 * 10244 * cache_controller_flush_status_hit 10245 * The status that the cache controller returned on executing the 10246 * flush command. 10247 * 10248 * 0 - miss; 1 - hit 10249 * 10250 * cache_controller_flush_status_desc_type 10251 * Flush descriptor type 10252 * 10253 * cache_controller_flush_status_client_id 10254 * Module who made the flush request 10255 * 10256 * In REO, this is always 0 10257 * 10258 * cache_controller_flush_status_error 10259 * Error condition 10260 * 10261 * 0 - No error found 10262 * 1 - HW interface is still busy 10263 * 2 - Line currently locked. Used for one line flush command 10264 * 3 - At least one line is still locked. 10265 * Used for cache flush command. 10266 * 10267 * cache_controller_flush_count 10268 * The number of lines that were actually flushed out 10269 * 10270 * looping_count 10271 * A count value that indicates the number of times the producer of 10272 * entries into this Ring has looped around the ring. 10273 */ 10274 10275 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 10276 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 10277 10278 struct hal_reo_unblock_cache_status { 10279 struct hal_reo_status_hdr hdr; 10280 uint32_t info0; 10281 uint32_t rsvd0[21]; 10282 uint32_t info1; 10283 } __packed; 10284 10285 /* hal_reo_unblock_cache_status 10286 * Producer: REO 10287 * Consumer: SW 10288 * 10289 * status_hdr 10290 * Details that can link this status with the original command. It 10291 * also contains info on how long REO took to execute this command. 10292 * 10293 * error_detected 10294 * 0 - No error has been detected while executing this command 10295 * 1 - The blocking resource was not in use, and therefore it could 10296 * not be unblocked. 10297 * 10298 * unblock_type 10299 * Reference to the type of unblock command 10300 * 0 - Unblock a blocking resource 10301 * 1 - The entire cache usage is unblock 10302 * 10303 * looping_count 10304 * A count value that indicates the number of times the producer of 10305 * entries into this Ring has looped around the ring. 10306 */ 10307 10308 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 10309 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 10310 10311 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 10312 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 10313 10314 struct hal_reo_flush_timeout_list_status { 10315 struct hal_reo_status_hdr hdr; 10316 uint32_t info0; 10317 uint32_t info1; 10318 uint32_t rsvd0[20]; 10319 uint32_t info2; 10320 } __packed; 10321 10322 /* hal_reo_flush_timeout_list_status 10323 * Producer: REO 10324 * Consumer: SW 10325 * 10326 * status_hdr 10327 * Details that can link this status with the original command. It 10328 * also contains info on how long REO took to execute this command. 10329 * 10330 * error_detected 10331 * 0 - No error has been detected while executing this command 10332 * 1 - Command not properly executed and returned with error 10333 * 10334 * timeout_list_empty 10335 * When set, REO has depleted the timeout list and all entries are 10336 * gone. 10337 * 10338 * release_desc_count 10339 * Producer: SW; Consumer: REO 10340 * The number of link descriptor released 10341 * 10342 * forward_buf_count 10343 * Producer: SW; Consumer: REO 10344 * The number of buffers forwarded to the REO destination rings 10345 * 10346 * looping_count 10347 * A count value that indicates the number of times the producer of 10348 * entries into this Ring has looped around the ring. 10349 */ 10350 10351 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 10352 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 10353 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 10354 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 10355 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 10356 10357 struct hal_reo_desc_thresh_reached_status { 10358 struct hal_reo_status_hdr hdr; 10359 uint32_t info0; 10360 uint32_t info1; 10361 uint32_t info2; 10362 uint32_t info3; 10363 uint32_t info4; 10364 uint32_t rsvd0[17]; 10365 uint32_t info5; 10366 } __packed; 10367 10368 /* hal_reo_desc_thresh_reached_status 10369 * Producer: REO 10370 * Consumer: SW 10371 * 10372 * status_hdr 10373 * Details that can link this status with the original command. It 10374 * also contains info on how long REO took to execute this command. 10375 * 10376 * threshold_index 10377 * The index of the threshold register whose value got reached 10378 * 10379 * link_descriptor_counter0 10380 * link_descriptor_counter1 10381 * link_descriptor_counter2 10382 * link_descriptor_counter_sum 10383 * Value of the respective counters at generation of this message 10384 * 10385 * looping_count 10386 * A count value that indicates the number of times the producer of 10387 * entries into this Ring has looped around the ring. 10388 */ 10389 10390 struct hal_tcl_entrance_from_ppe_ring { 10391 uint32_t buffer_addr; 10392 uint32_t info0; 10393 } __packed; 10394 10395 struct hal_mon_buf_ring { 10396 uint32_t paddr_lo; 10397 uint32_t paddr_hi; 10398 uint64_t cookie; 10399 }; 10400 10401 /* hal_mon_buf_ring 10402 * Producer : SW 10403 * Consumer : Monitor 10404 * 10405 * paddr_lo 10406 * Lower 32-bit physical address of the buffer pointer from the source ring. 10407 * paddr_hi 10408 * bit range 7-0 : upper 8 bit of the physical address. 10409 * bit range 31-8 : reserved. 10410 * cookie 10411 * Consumer: RxMon/TxMon 64 bit cookie of the buffers. 10412 */ 10413 10414 struct hal_mon_dest_desc { 10415 uint32_t cookie; 10416 uint32_t reserved; 10417 uint32_t ppdu_id; 10418 uint32_t info0; 10419 }; 10420 10421 /* hal_mon_dest_ring 10422 * Producer : TxMon/RxMon 10423 * Consumer : SW 10424 * cookie 10425 * bit 0 -17 buf_id to track the skb's vaddr. 10426 * ppdu_id 10427 * Phy ppdu_id 10428 * end_offset 10429 * The offset into status buffer where DMA ended, ie., offset to the last 10430 * TLV + last TLV size. 10431 * flush_detected 10432 * Indicates whether 'tx_flush' or 'rx_flush' occurred. 10433 * end_of_ppdu 10434 * Indicates end of ppdu. 10435 * pmac_id 10436 * Indicates PMAC that received from frame. 10437 * empty_descriptor 10438 * This descriptor is written on flush or end of ppdu or end of status 10439 * buffer. 10440 * ring_id 10441 * updated by SRNG. 10442 * looping_count 10443 * updated by SRNG. 10444 */ 10445 10446 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF 10447 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF 10448 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF 10449 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF 10450 10451 #define HAL_TX_ADDRX_EN 1 10452 #define HAL_TX_ADDRY_EN 2 10453 10454 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 10455 #define HAL_TX_ADDR_SEARCH_INDEX 1 10456 10457 /* 10458 * Copy Engine 10459 */ 10460 10461 #define CE_COUNT_MAX 16 10462 10463 /* Byte swap data words */ 10464 #define CE_ATTR_BYTE_SWAP_DATA 2 10465 10466 /* no interrupt on copy completion */ 10467 #define CE_ATTR_DIS_INTR 8 10468 10469 /* Host software's Copy Engine configuration. */ 10470 #ifdef __BIG_ENDIAN 10471 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA 10472 #else 10473 #define CE_ATTR_FLAGS 0 10474 #endif 10475 10476 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 10477 #define ATH12K_CE_USAGE_THRESHOLD 32 10478 10479 /* 10480 * Directions for interconnect pipe configuration. 10481 * These definitions may be used during configuration and are shared 10482 * between Host and Target. 10483 * 10484 * Pipe Directions are relative to the Host, so PIPEDIR_IN means 10485 * "coming IN over air through Target to Host" as with a WiFi Rx operation. 10486 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 10487 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 10488 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 10489 * over the interconnect. 10490 */ 10491 #define PIPEDIR_NONE 0 10492 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 10493 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 10494 #define PIPEDIR_INOUT 3 /* bidirectional */ 10495 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 10496 10497 /* CE address/mask */ 10498 #define CE_HOST_IE_ADDRESS 0x00A1803C 10499 #define CE_HOST_IE_2_ADDRESS 0x00A18040 10500 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS 10501 10502 /* CE IE registers are different for IPQ5018 */ 10503 #define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C 10504 #define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050 10505 #define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS 10506 10507 #define CE_HOST_IE_3_SHIFT 0xC 10508 10509 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 10510 10511 /* 10512 * Establish a mapping between a service/direction and a pipe. 10513 * Configuration information for a Copy Engine pipe and services. 10514 * Passed from Host to Target through QMI message and must be in 10515 * little endian format. 10516 */ 10517 struct service_to_pipe { 10518 uint32_t service_id; 10519 uint32_t pipedir; 10520 uint32_t pipenum; 10521 }; 10522 10523 /* 10524 * Configuration information for a Copy Engine pipe. 10525 * Passed from Host to Target through QMI message during startup (one per CE). 10526 * 10527 * NOTE: Structure is shared between Host software and Target firmware! 10528 */ 10529 struct ce_pipe_config { 10530 uint32_t pipenum; 10531 uint32_t pipedir; 10532 uint32_t nentries; 10533 uint32_t nbytes_max; 10534 uint32_t flags; 10535 uint32_t reserved; 10536 }; 10537 10538 /* 10539 * HTC 10540 */ 10541 10542 #define HTC_HDR_ENDPOINTID GENMASK(7, 0) 10543 #define HTC_HDR_FLAGS GENMASK(15, 8) 10544 #define HTC_HDR_PAYLOADLEN GENMASK(31, 16) 10545 #define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0) 10546 #define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8) 10547 #define HTC_HDR_RESERVED GENMASK(31, 16) 10548 10549 #define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16) 10550 #define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0) 10551 #define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16) 10552 #define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16) 10553 #define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0) 10554 #define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16) 10555 10556 #define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0) 10557 #define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8) 10558 10559 #define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16) 10560 #define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0) 10561 #define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8) 10562 #define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16) 10563 #define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0) 10564 10565 #define HTC_MSG_MESSAGEID GENMASK(15, 0) 10566 #define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0) 10567 #define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0) 10568 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8) 10569 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16) 10570 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24) 10571 10572 enum ath12k_htc_tx_flags { 10573 ATH12K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01, 10574 ATH12K_HTC_FLAG_SEND_BUNDLE = 0x02 10575 }; 10576 10577 enum ath12k_htc_rx_flags { 10578 ATH12K_HTC_FLAG_TRAILER_PRESENT = 0x02, 10579 ATH12K_HTC_FLAG_BUNDLE_MASK = 0xF0 10580 }; 10581 10582 10583 struct ath12k_htc_hdr { 10584 uint32_t htc_info; 10585 uint32_t ctrl_info; 10586 } __packed __aligned(4); 10587 10588 enum ath12k_htc_msg_id { 10589 ATH12K_HTC_MSG_READY_ID = 1, 10590 ATH12K_HTC_MSG_CONNECT_SERVICE_ID = 2, 10591 ATH12K_HTC_MSG_CONNECT_SERVICE_RESP_ID = 3, 10592 ATH12K_HTC_MSG_SETUP_COMPLETE_ID = 4, 10593 ATH12K_HTC_MSG_SETUP_COMPLETE_EX_ID = 5, 10594 ATH12K_HTC_MSG_SEND_SUSPEND_COMPLETE = 6, 10595 ATH12K_HTC_MSG_NACK_SUSPEND = 7, 10596 ATH12K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID = 8, 10597 }; 10598 10599 enum ath12k_htc_version { 10600 ATH12K_HTC_VERSION_2P0 = 0x00, /* 2.0 */ 10601 ATH12K_HTC_VERSION_2P1 = 0x01, /* 2.1 */ 10602 }; 10603 10604 #define ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0) 10605 #define ATH12K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8) 10606 10607 enum ath12k_htc_conn_flags { 10608 ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH = 0x0, 10609 ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF = 0x1, 10610 ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS = 0x2, 10611 ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY = 0x3, 10612 ATH12K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE = 0x4, 10613 ATH12K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL = 0x8, 10614 }; 10615 10616 enum ath12k_htc_conn_svc_status { 10617 ATH12K_HTC_CONN_SVC_STATUS_SUCCESS = 0, 10618 ATH12K_HTC_CONN_SVC_STATUS_NOT_FOUND = 1, 10619 ATH12K_HTC_CONN_SVC_STATUS_FAILED = 2, 10620 ATH12K_HTC_CONN_SVC_STATUS_NO_RESOURCES = 3, 10621 ATH12K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4 10622 }; 10623 10624 struct ath12k_htc_ready { 10625 uint32_t id_credit_count; 10626 uint32_t size_ep; 10627 } __packed; 10628 10629 struct ath12k_htc_ready_extended { 10630 struct ath12k_htc_ready base; 10631 uint32_t ver_bundle; 10632 } __packed; 10633 10634 struct ath12k_htc_conn_svc { 10635 uint32_t msg_svc_id; 10636 uint32_t flags_len; 10637 } __packed; 10638 10639 struct ath12k_htc_conn_svc_resp { 10640 uint32_t msg_svc_id; 10641 uint32_t flags_len; 10642 uint32_t svc_meta_pad; 10643 } __packed; 10644 10645 #define ATH12K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1) 10646 10647 struct ath12k_htc_setup_complete_extended { 10648 uint32_t msg_id; 10649 uint32_t flags; 10650 uint32_t max_msgs_per_bundled_recv; 10651 } __packed; 10652 10653 struct ath12k_htc_msg { 10654 uint32_t msg_svc_id; 10655 uint32_t flags_len; 10656 } __packed __aligned(4); 10657 10658 enum ath12k_htc_record_id { 10659 ATH12K_HTC_RECORD_NULL = 0, 10660 ATH12K_HTC_RECORD_CREDITS = 1 10661 }; 10662 10663 struct ath12k_htc_record_hdr { 10664 uint8_t id; /* @enum ath12k_htc_record_id */ 10665 uint8_t len; 10666 uint8_t pad0; 10667 uint8_t pad1; 10668 } __packed; 10669 10670 struct ath12k_htc_credit_report { 10671 uint8_t eid; /* @enum ath12k_htc_ep_id */ 10672 uint8_t credits; 10673 uint8_t pad0; 10674 uint8_t pad1; 10675 } __packed; 10676 10677 struct ath12k_htc_record { 10678 struct ath12k_htc_record_hdr hdr; 10679 union { 10680 struct ath12k_htc_credit_report credit_report[0]; 10681 uint8_t payload[0]; 10682 }; 10683 } __packed __aligned(4); 10684 10685 /* note: the trailer offset is dynamic depending 10686 * on payload length. this is only a struct layout draft 10687 */ 10688 struct ath12k_htc_frame { 10689 struct ath12k_htc_hdr hdr; 10690 union { 10691 struct ath12k_htc_msg msg; 10692 uint8_t payload[0]; 10693 }; 10694 struct ath12k_htc_record trailer[0]; 10695 } __packed __aligned(4); 10696 10697 enum ath12k_htc_svc_gid { 10698 ATH12K_HTC_SVC_GRP_RSVD = 0, 10699 ATH12K_HTC_SVC_GRP_WMI = 1, 10700 ATH12K_HTC_SVC_GRP_NMI = 2, 10701 ATH12K_HTC_SVC_GRP_HTT = 3, 10702 ATH12K_HTC_SVC_GRP_CFG = 4, 10703 ATH12K_HTC_SVC_GRP_IPA = 5, 10704 ATH12K_HTC_SVC_GRP_PKTLOG = 6, 10705 10706 ATH12K_HTC_SVC_GRP_TEST = 254, 10707 ATH12K_HTC_SVC_GRP_LAST = 255, 10708 }; 10709 10710 #define SVC(group, idx) \ 10711 (int)(((int)(group) << 8) | (int)(idx)) 10712 10713 enum ath12k_htc_svc_id { 10714 /* NOTE: service ID of 0x0000 is reserved and should never be used */ 10715 ATH12K_HTC_SVC_ID_RESERVED = 0x0000, 10716 ATH12K_HTC_SVC_ID_UNUSED = ATH12K_HTC_SVC_ID_RESERVED, 10717 10718 ATH12K_HTC_SVC_ID_RSVD_CTRL = SVC(ATH12K_HTC_SVC_GRP_RSVD, 1), 10719 ATH12K_HTC_SVC_ID_WMI_CONTROL = SVC(ATH12K_HTC_SVC_GRP_WMI, 0), 10720 ATH12K_HTC_SVC_ID_WMI_DATA_BE = SVC(ATH12K_HTC_SVC_GRP_WMI, 1), 10721 ATH12K_HTC_SVC_ID_WMI_DATA_BK = SVC(ATH12K_HTC_SVC_GRP_WMI, 2), 10722 ATH12K_HTC_SVC_ID_WMI_DATA_VI = SVC(ATH12K_HTC_SVC_GRP_WMI, 3), 10723 ATH12K_HTC_SVC_ID_WMI_DATA_VO = SVC(ATH12K_HTC_SVC_GRP_WMI, 4), 10724 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1 = SVC(ATH12K_HTC_SVC_GRP_WMI, 5), 10725 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC2 = SVC(ATH12K_HTC_SVC_GRP_WMI, 6), 10726 ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG = SVC(ATH12K_HTC_SVC_GRP_WMI, 7), 10727 10728 ATH12K_HTC_SVC_ID_NMI_CONTROL = SVC(ATH12K_HTC_SVC_GRP_NMI, 0), 10729 ATH12K_HTC_SVC_ID_NMI_DATA = SVC(ATH12K_HTC_SVC_GRP_NMI, 1), 10730 10731 ATH12K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH12K_HTC_SVC_GRP_HTT, 0), 10732 10733 /* raw stream service (i.e. flash, tcmd, calibration apps) */ 10734 ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH12K_HTC_SVC_GRP_TEST, 0), 10735 ATH12K_HTC_SVC_ID_IPA_TX = SVC(ATH12K_HTC_SVC_GRP_IPA, 0), 10736 ATH12K_HTC_SVC_ID_PKT_LOG = SVC(ATH12K_HTC_SVC_GRP_PKTLOG, 0), 10737 }; 10738 10739 #undef SVC 10740 10741 enum ath12k_htc_ep_id { 10742 ATH12K_HTC_EP_UNUSED = -1, 10743 ATH12K_HTC_EP_0 = 0, 10744 ATH12K_HTC_EP_1 = 1, 10745 ATH12K_HTC_EP_2, 10746 ATH12K_HTC_EP_3, 10747 ATH12K_HTC_EP_4, 10748 ATH12K_HTC_EP_5, 10749 ATH12K_HTC_EP_6, 10750 ATH12K_HTC_EP_7, 10751 ATH12K_HTC_EP_8, 10752 ATH12K_HTC_EP_COUNT, 10753 }; 10754 10755 /* 10756 * hw.h 10757 */ 10758 10759 /* Target configuration defines */ 10760 10761 /* Num VDEVS per radio */ 10762 #define TARGET_NUM_VDEVS (16 + 1) 10763 10764 #define TARGET_NUM_PEERS_PDEV_SINGLE (TARGET_NUM_STATIONS_SINGLE + \ 10765 TARGET_NUM_VDEVS) 10766 #define TARGET_NUM_PEERS_PDEV_DBS (TARGET_NUM_STATIONS_DBS + \ 10767 TARGET_NUM_VDEVS) 10768 #define TARGET_NUM_PEERS_PDEV_DBS_SBS (TARGET_NUM_STATIONS_DBS_SBS + \ 10769 TARGET_NUM_VDEVS) 10770 10771 /* Num of peers for Single Radio mode */ 10772 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV_SINGLE) 10773 10774 /* Num of peers for DBS */ 10775 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV_DBS) 10776 10777 /* Num of peers for DBS_SBS */ 10778 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV_DBS_SBS) 10779 10780 /* Max num of stations for Single Radio mode */ 10781 #define TARGET_NUM_STATIONS_SINGLE 512 10782 10783 /* Max num of stations for DBS */ 10784 #define TARGET_NUM_STATIONS_DBS 128 10785 10786 /* Max num of stations for DBS_SBS */ 10787 #define TARGET_NUM_STATIONS_DBS_SBS 128 10788 10789 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x 10790 #define TARGET_NUM_PEER_KEYS 2 10791 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \ 10792 4 * TARGET_NUM_VDEVS + 8) 10793 10794 #define TARGET_AST_SKID_LIMIT 16 10795 #define TARGET_NUM_OFFLD_PEERS 4 10796 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 10797 10798 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10799 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10800 #define TARGET_RX_TIMEOUT_LO_PRI 100 10801 #define TARGET_RX_TIMEOUT_HI_PRI 40 10802 10803 #define TARGET_DECAP_MODE_RAW 0 10804 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 10805 #define TARGET_DECAP_MODE_ETH 2 10806 10807 #define TARGET_SCAN_MAX_PENDING_REQS 4 10808 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 10809 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 10810 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 10811 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 10812 #define TARGET_NUM_MCAST_GROUPS 12 10813 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 10814 #define TARGET_MCAST2UCAST_MODE 2 10815 #define TARGET_TX_DBG_LOG_SIZE 1024 10816 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 10817 #define TARGET_VOW_CONFIG 0 10818 #define TARGET_NUM_MSDU_DESC (2500) 10819 #define TARGET_MAX_FRAG_ENTRIES 6 10820 #define TARGET_MAX_BCN_OFFLD 16 10821 #define TARGET_NUM_WDS_ENTRIES 32 10822 #define TARGET_DMA_BURST_SIZE 1 10823 #define TARGET_RX_BATCHMODE 1 10824 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 10825 10826 #define ATH12K_HW_MAX_QUEUES 4 10827 #define ATH12K_QUEUE_LEN 4096 10828 10829 #define ATH12k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 10830 10831 enum ath12k_hw_rate_cck { 10832 ATH12K_HW_RATE_CCK_LP_11M = 0, 10833 ATH12K_HW_RATE_CCK_LP_5_5M, 10834 ATH12K_HW_RATE_CCK_LP_2M, 10835 ATH12K_HW_RATE_CCK_LP_1M, 10836 ATH12K_HW_RATE_CCK_SP_11M, 10837 ATH12K_HW_RATE_CCK_SP_5_5M, 10838 ATH12K_HW_RATE_CCK_SP_2M, 10839 }; 10840 10841 enum ath12k_hw_rate_ofdm { 10842 ATH12K_HW_RATE_OFDM_48M = 0, 10843 ATH12K_HW_RATE_OFDM_24M, 10844 ATH12K_HW_RATE_OFDM_12M, 10845 ATH12K_HW_RATE_OFDM_6M, 10846 ATH12K_HW_RATE_OFDM_54M, 10847 ATH12K_HW_RATE_OFDM_36M, 10848 ATH12K_HW_RATE_OFDM_18M, 10849 ATH12K_HW_RATE_OFDM_9M, 10850 }; 10851 10852 enum ath12k_bus { 10853 ATH12K_BUS_AHB, 10854 ATH12K_BUS_PCI, 10855 }; 10856 10857 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 10858 10859 /* 10860 * rx_desc.h 10861 */ 10862 10863 enum dp_rx_decap_type { 10864 DP_RX_DECAP_TYPE_RAW, 10865 DP_RX_DECAP_TYPE_NATIVE_WIFI, 10866 DP_RX_DECAP_TYPE_ETHERNET2_DIX, 10867 DP_RX_DECAP_TYPE_8023, 10868 }; 10869 10870 enum rx_desc_decap_type { 10871 RX_DESC_DECAP_TYPE_RAW, 10872 RX_DESC_DECAP_TYPE_NATIVE_WIFI, 10873 RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 10874 RX_DESC_DECAP_TYPE_8023, 10875 }; 10876 10877 enum rx_desc_decrypt_status_code { 10878 RX_DESC_DECRYPT_STATUS_CODE_OK, 10879 RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME, 10880 RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR, 10881 RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID, 10882 RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID, 10883 RX_DESC_DECRYPT_STATUS_CODE_OTHER, 10884 }; 10885 10886 #define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0) 10887 #define RX_MPDU_START_INFO0_LMAC_PEER_ID_MSB GENMASK(6, 5) 10888 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7) 10889 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8) 10890 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9) 10891 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10) 10892 #define RX_MPDU_START_INFO0_RXDMA0_SRC_RING_SEL GENMASK(13, 11) 10893 #define RX_MPDU_START_INFO0_RXDMA0_DST_RING_SEL GENMASK(16, 14) 10894 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17) 10895 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18) 10896 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19) 10897 #define RX_MPDU_START_INFO0_USE_PPE BIT(20) 10898 #define RX_MPDU_START_INFO0_PPE_ROUTING_EN BIT(21) 10899 10900 #define RX_MPDU_START_INFO1_REO_QUEUE_DESC_HI GENMASK(7, 0) 10901 #define RX_MPDU_START_INFO1_RECV_QUEUE_NUM GENMASK(23, 8) 10902 #define RX_MPDU_START_INFO1_PRE_DELIM_ERR_WARN BIT(24) 10903 #define RX_MPDU_START_INFO1_FIRST_DELIM_ERR BIT(25) 10904 10905 #define RX_MPDU_START_INFO2_EPD_EN BIT(0) 10906 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1) 10907 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2) 10908 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 10909 #define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8) 10910 #define RX_MPDU_START_INFO2_BSSID_HIT BIT(10) 10911 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(14, 11) 10912 #define RX_MPDU_START_INFO2_TID GENMASK(18, 15) 10913 10914 #define RX_MPDU_START_INFO3_RXPCU_MPDU_FLTR GENMASK(1, 0) 10915 #define RX_MPDU_START_INFO3_SW_FRAME_GRP_ID GENMASK(8, 2) 10916 #define RX_MPDU_START_INFO3_NDP_FRAME BIT(9) 10917 #define RX_MPDU_START_INFO3_PHY_ERR BIT(10) 10918 #define RX_MPDU_START_INFO3_PHY_ERR_MPDU_HDR BIT(11) 10919 #define RX_MPDU_START_INFO3_PROTO_VER_ERR BIT(12) 10920 #define RX_MPDU_START_INFO3_AST_LOOKUP_VALID BIT(13) 10921 #define RX_MPDU_START_INFO3_RANGING BIT(14) 10922 10923 #define RX_MPDU_START_INFO4_MPDU_FCTRL_VALID BIT(0) 10924 #define RX_MPDU_START_INFO4_MPDU_DUR_VALID BIT(1) 10925 #define RX_MPDU_START_INFO4_MAC_ADDR1_VALID BIT(2) 10926 #define RX_MPDU_START_INFO4_MAC_ADDR2_VALID BIT(3) 10927 #define RX_MPDU_START_INFO4_MAC_ADDR3_VALID BIT(4) 10928 #define RX_MPDU_START_INFO4_MAC_ADDR4_VALID BIT(5) 10929 #define RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID BIT(6) 10930 #define RX_MPDU_START_INFO4_MPDU_QOS_CTRL_VALID BIT(7) 10931 #define RX_MPDU_START_INFO4_MPDU_HT_CTRL_VALID BIT(8) 10932 #define RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID BIT(9) 10933 #define RX_MPDU_START_INFO4_MPDU_FRAG_NUMBER GENMASK(13, 10) 10934 #define RX_MPDU_START_INFO4_MORE_FRAG_FLAG BIT(14) 10935 #define RX_MPDU_START_INFO4_FROM_DS BIT(16) 10936 #define RX_MPDU_START_INFO4_TO_DS BIT(17) 10937 #define RX_MPDU_START_INFO4_ENCRYPTED BIT(18) 10938 #define RX_MPDU_START_INFO4_MPDU_RETRY BIT(19) 10939 #define RX_MPDU_START_INFO4_MPDU_SEQ_NUM GENMASK(31, 20) 10940 10941 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0) 10942 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8) 10943 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9) 10944 #define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10) 10945 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12) 10946 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13) 10947 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14) 10948 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15) 10949 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16) 10950 #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28) 10951 #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29) 10952 #define RX_MPDU_START_INFO5_RAW_MPDU BIT(30) 10953 10954 #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0) 10955 #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14) 10956 #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15) 10957 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16) 10958 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17) 10959 #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18) 10960 #define RX_MPDU_START_INFO6_NON_QOS BIT(19) 10961 #define RX_MPDU_START_INFO6_NULL_DATA BIT(20) 10962 #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21) 10963 #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22) 10964 #define RX_MPDU_START_INFO6_MORE_DATA BIT(23) 10965 #define RX_MPDU_START_INFO6_EOSP BIT(24) 10966 #define RX_MPDU_START_INFO6_FRAGMENT BIT(25) 10967 #define RX_MPDU_START_INFO6_ORDER BIT(26) 10968 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27) 10969 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28) 10970 #define RX_MPDU_START_INFO6_DIRECTED BIT(29) 10971 #define RX_MPDU_START_INFO6_AMSDU_PRESENT BIT(30) 10972 10973 #define RX_MPDU_START_INFO7_VDEV_ID GENMASK(7, 0) 10974 #define RX_MPDU_START_INFO7_SERVICE_CODE GENMASK(16, 8) 10975 #define RX_MPDU_START_INFO7_PRIORITY_VALID BIT(17) 10976 #define RX_MPDU_START_INFO7_SRC_INFO GENMASK(29, 18) 10977 10978 #define RX_MPDU_START_INFO8_AUTH_TO_SEND_WDS BIT(0) 10979 10980 struct rx_mpdu_start_qcn9274 { 10981 uint32_t info0; 10982 uint32_t reo_queue_desc_lo; 10983 uint32_t info1; 10984 uint32_t pn[4]; 10985 uint32_t info2; 10986 uint32_t peer_meta_data; 10987 uint16_t info3; 10988 uint16_t phy_ppdu_id; 10989 uint16_t ast_index; 10990 uint16_t sw_peer_id; 10991 uint32_t info4; 10992 uint32_t info5; 10993 uint32_t info6; 10994 uint16_t frame_ctrl; 10995 uint16_t duration; 10996 uint8_t addr1[IEEE80211_ADDR_LEN]; 10997 uint8_t addr2[IEEE80211_ADDR_LEN]; 10998 uint8_t addr3[IEEE80211_ADDR_LEN]; 10999 uint16_t seq_ctrl; 11000 uint8_t addr4[IEEE80211_ADDR_LEN]; 11001 uint16_t qos_ctrl; 11002 uint32_t ht_ctrl; 11003 uint32_t info7; 11004 uint8_t multi_link_addr1[IEEE80211_ADDR_LEN]; 11005 uint8_t multi_link_addr2[IEEE80211_ADDR_LEN]; 11006 uint32_t info8; 11007 uint32_t res0; 11008 uint32_t res1; 11009 } __packed; 11010 11011 #define QCN9274_MPDU_START_SELECT_MPDU_START_TAG BIT(0) 11012 #define QCN9274_MPDU_START_SELECT_INFO0_REO_QUEUE_DESC_LO BIT(1) 11013 #define QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 BIT(2) 11014 #define QCN9274_MPDU_START_SELECT_PN_95_32 BIT(3) 11015 #define QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 BIT(4) 11016 #define QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID BIT(5) 11017 #define QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 BIT(6) 11018 #define QCN9274_MPDU_START_SELECT_INFO5_INFO6 BIT(7) 11019 #define QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 BIT(8) 11020 #define QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 BIT(9) 11021 #define QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL BIT(10) 11022 #define QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL BIT(11) 11023 #define QCN9274_MPDU_START_SELECT_HT_CTRL_INFO7 BIT(12) 11024 #define QCN9274_MPDU_START_SELECT_ML_ADDR1_47_0_ML_ADDR2_15_0 BIT(13) 11025 #define QCN9274_MPDU_START_SELECT_ML_ADDR2_47_16_INFO8 BIT(14) 11026 #define QCN9274_MPDU_START_SELECT_RES_0_RES_1 BIT(15) 11027 11028 #define QCN9274_MPDU_START_WMASK (QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 | \ 11029 QCN9274_MPDU_START_SELECT_PN_95_32 | \ 11030 QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 | \ 11031 QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID | \ 11032 QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 | \ 11033 QCN9274_MPDU_START_SELECT_INFO5_INFO6 | \ 11034 QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 | \ 11035 QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 | \ 11036 QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL | \ 11037 QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL) 11038 11039 /* The below rx_mpdu_start_qcn9274_compact structure is tied with the mask 11040 * value QCN9274_MPDU_START_WMASK. If the mask value changes the structure 11041 * will also change. 11042 */ 11043 11044 struct rx_mpdu_start_qcn9274_compact { 11045 uint32_t info1; 11046 uint32_t pn[4]; 11047 uint32_t info2; 11048 uint32_t peer_meta_data; 11049 uint16_t info3; 11050 uint16_t phy_ppdu_id; 11051 uint16_t ast_index; 11052 uint16_t sw_peer_id; 11053 uint32_t info4; 11054 uint32_t info5; 11055 uint32_t info6; 11056 uint16_t frame_ctrl; 11057 uint16_t duration; 11058 uint8_t addr1[IEEE80211_ADDR_LEN]; 11059 uint8_t addr2[IEEE80211_ADDR_LEN]; 11060 uint8_t addr3[IEEE80211_ADDR_LEN]; 11061 uint16_t seq_ctrl; 11062 uint8_t addr4[IEEE80211_ADDR_LEN]; 11063 uint16_t qos_ctrl; 11064 } __packed; 11065 11066 /* rx_mpdu_start 11067 * 11068 * reo_destination_indication 11069 * The id of the reo exit ring where the msdu frame shall push 11070 * after (MPDU level) reordering has finished. Values are defined 11071 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 11072 * 11073 * lmac_peer_id_msb 11074 * 11075 * If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 11076 * is 2'b00, Rx OLE uses a REO destination indicati'n of {1'b1, 11077 * hash[3:0]} using the chosen Toeplitz hash from Common Parser 11078 * if flow search fails. 11079 * If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 11080 * 's not 2'b00, Rx OLE uses a REO destination indication of 11081 * {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 11082 * hash from Common Parser if flow search fails. 11083 * 11084 * use_flow_id_toeplitz_clfy 11085 * Indication to Rx OLE to enable REO destination routing based 11086 * on the chosen Toeplitz hash from Common Parser, in case 11087 * flow search fails 11088 * 11089 * pkt_selection_fp_ucast_data 11090 * Filter pass Unicast data frame (matching rxpcu_filter_pass 11091 * and sw_frame_group_Unicast_data) routing selection 11092 * 11093 * pkt_selection_fp_mcast_data 11094 * Filter pass Multicast data frame (matching rxpcu_filter_pass 11095 * and sw_frame_group_Multicast_data) routing selection 11096 * 11097 * pkt_selection_fp_ctrl_bar 11098 * Filter pass BAR frame (matching rxpcu_filter_pass 11099 * and sw_frame_group_ctrl_1000) routing selection 11100 * 11101 * rxdma0_src_ring_selection 11102 * Field only valid when for the received frame type the corresponding 11103 * pkt_selection_fp_... bit is set 11104 * 11105 * rxdma0_dst_ring_selection 11106 * Field only valid when for the received frame type the corresponding 11107 * pkt_selection_fp_... bit is set 11108 * 11109 * mcast_echo_drop_enable 11110 * If set, for multicast packets, multicast echo check (i.e. 11111 * SA search with mcast_echo_check = 1) shall be performed 11112 * by RXOLE, and any multicast echo packets should be indicated 11113 * to RXDMA for release to WBM 11114 * 11115 * wds_learning_detect_en 11116 * If set, WDS learning detection based on SA search and notification 11117 * to FW (using RXDMA0 status ring) is enabled and the "timestamp" 11118 * field in address search failure cache-only entry should 11119 * be used to avoid multiple WDS learning notifications. 11120 * 11121 * intrabss_check_en 11122 * If set, intra-BSS routing detection is enabled 11123 * 11124 * use_ppe 11125 * Indicates to RXDMA to ignore the REO_destination_indication 11126 * and use a programmed value corresponding to the REO2PPE 11127 * ring 11128 * This override to REO2PPE for packets requiring multiple 11129 * buffers shall be disabled based on an RXDMA configuration, 11130 * as PPE may not support such packets. 11131 * 11132 * Supported only in full AP chips, not in client/soft 11133 * chips 11134 * 11135 * ppe_routing_enable 11136 * Global enable/disable bit for routing to PPE, used to disable 11137 * PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 11138 * This is set by SW for peers which are being handled by a 11139 * host SW/accelerator subsystem that also handles packet 11140 * buffer management for WiFi-to-PPE routing. 11141 * 11142 * This is cleared by SW for peers which are being handled 11143 * by a different subsystem, completely disabling WiFi-to-PPE 11144 * routing for such peers. 11145 * 11146 * rx_reo_queue_desc_addr_lo 11147 * Address (lower 32 bits) of the REO queue descriptor. 11148 * 11149 * rx_reo_queue_desc_addr_hi 11150 * Address (upper 8 bits) of the REO queue descriptor. 11151 * 11152 * receive_queue_number 11153 * Indicates the MPDU queue ID to which this MPDU link 11154 * descriptor belongs. 11155 * 11156 * pre_delim_err_warning 11157 * Indicates that a delimiter FCS error was found in between the 11158 * previous MPDU and this MPDU. Note that this is just a warning, 11159 * and does not mean that this MPDU is corrupted in any way. If 11160 * it is, there will be other errors indicated such as FCS or 11161 * decrypt errors. 11162 * 11163 * first_delim_err 11164 * Indicates that the first delimiter had a FCS failure. 11165 * 11166 * pn 11167 * The PN number. 11168 * 11169 * epd_en 11170 * Field only valid when AST_based_lookup_valid == 1. 11171 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 11172 * this field will be set to 0 11173 * If set to one use EPD instead of LPD 11174 * In case of ndp or phy_err, this field will never be set. 11175 * 11176 * all_frames_shall_be_encrypted 11177 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 11178 * this field will be set to 0 11179 * 11180 * When set, all frames (data only ?) shall be encrypted. If 11181 * not, RX CRYPTO shall set an error flag. 11182 * 11183 * 11184 * encrypt_type 11185 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 11186 * this field will be set to 0 11187 * 11188 * Indicates type of decrypt cipher used (as defined in the 11189 * peer entry) 11190 * 11191 * wep_key_width_for_variable_key 11192 * 11193 * Field only valid when key_type is set to wep_varied_width. 11194 * 11195 * mesh_sta 11196 * 11197 * bssid_hit 11198 * When set, the BSSID of the incoming frame matched one of 11199 * the 8 BSSID register values 11200 * bssid_number 11201 * Field only valid when bssid_hit is set. 11202 * This number indicates which one out of the 8 BSSID register 11203 * values matched the incoming frame 11204 * 11205 * tid 11206 * Field only valid when mpdu_qos_control_valid is set 11207 * The TID field in the QoS control field 11208 * 11209 * peer_meta_data 11210 * Meta data that SW has programmed in the Peer table entry 11211 * of the transmitting STA. 11212 * 11213 * rxpcu_mpdu_filter_in_category 11214 * Field indicates what the reason was that this mpdu frame 11215 * was allowed to come into the receive path by rxpcu. Values 11216 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11217 * 11218 * sw_frame_group_id 11219 * SW processes frames based on certain classifications. Values 11220 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11221 * 11222 * ndp_frame 11223 * When set, the received frame was an NDP frame, and thus 11224 * there will be no MPDU data. 11225 * phy_err 11226 * When set, a PHY error was received before MAC received any 11227 * data, and thus there will be no MPDU data. 11228 * 11229 * phy_err_during_mpdu_header 11230 * When set, a PHY error was received before MAC received the 11231 * complete MPDU header which was needed for proper decoding 11232 * 11233 * protocol_version_err 11234 * Set when RXPCU detected a version error in the Frame control 11235 * field 11236 * 11237 * ast_based_lookup_valid 11238 * When set, AST based lookup for this frame has found a valid 11239 * result. 11240 * 11241 * ranging 11242 * When set, a ranging NDPA or a ranging NDP was received. 11243 * 11244 * phy_ppdu_id 11245 * A ppdu counter value that PHY increments for every PPDU 11246 * received. The counter value wraps around. 11247 * 11248 * ast_index 11249 * 11250 * This field indicates the index of the AST entry corresponding 11251 * to this MPDU. It is provided by the GSE module instantiated 11252 * in RXPCU. 11253 * A value of 0xFFFF indicates an invalid AST index, meaning 11254 * that No AST entry was found or NO AST search was performed 11255 * 11256 * sw_peer_id 11257 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 11258 * this field will be set to 0 11259 * This field indicates a unique peer identifier. It is set 11260 * equal to field 'sw_peer_id' from the AST entry 11261 * 11262 * frame_control_valid 11263 * When set, the field Mpdu_Frame_control_field has valid information 11264 * 11265 * frame_duration_valid 11266 * When set, the field Mpdu_duration_field has valid information 11267 * 11268 * mac_addr_ad1..4_valid 11269 * When set, the fields mac_addr_adx_..... have valid information 11270 * 11271 * mpdu_seq_ctrl_valid 11272 * 11273 * When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 11274 * have valid information as well as field 11275 * For MPDUs without a sequence control field, this field will 11276 * not be set. 11277 * 11278 * mpdu_qos_ctrl_valid, mpdu_ht_ctrl_valid 11279 * 11280 * When set, the field mpdu_qos_control_field, mpdu_ht_control has valid 11281 * information, For MPDUs without a QoS,HT control field, this field 11282 * will not be set. 11283 * 11284 * frame_encryption_info_valid 11285 * 11286 * When set, the encryption related info fields, like IV and 11287 * PN are valid 11288 * For MPDUs that are not encrypted, this will not be set. 11289 * 11290 * mpdu_fragment_number 11291 * 11292 * Field only valid when Mpdu_sequence_control_valid is set 11293 * AND Fragment_flag is set. The fragment number from the 802.11 header 11294 * 11295 * more_fragment_flag 11296 * 11297 * The More Fragment bit setting from the MPDU header of the 11298 * received frame 11299 * 11300 * fr_ds 11301 * 11302 * Field only valid when Mpdu_frame_control_valid is set 11303 * Set if the from DS bit is set in the frame control. 11304 * 11305 * to_ds 11306 * 11307 * Field only valid when Mpdu_frame_control_valid is set 11308 * Set if the to DS bit is set in the frame control. 11309 * 11310 * encrypted 11311 * 11312 * Field only valid when Mpdu_frame_control_valid is set. 11313 * Protected bit from the frame control. 11314 * 11315 * mpdu_retry 11316 * Field only valid when Mpdu_frame_control_valid is set. 11317 * Retry bit from the frame control. Only valid when first_msdu is set 11318 * 11319 * mpdu_sequence_number 11320 * Field only valid when Mpdu_sequence_control_valid is set. 11321 * 11322 * The sequence number from the 802.11 header. 11323 * key_id 11324 * The key ID octet from the IV. 11325 * Field only valid when Frame_encryption_info_valid is set 11326 * 11327 * new_peer_entry 11328 * Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 11329 * doesn't follow so RX DECRYPTION module either uses old peer 11330 * entry or not decrypt. 11331 * 11332 * decrypt_needed 11333 * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout', 11334 * RXPCU will also ensure that this bit is NOT set. CRYPTO for that 11335 * reason only needs to evaluate this bit and non of the other ones 11336 * 11337 * decap_type 11338 * Used by the OLE during decapsulation. Values are defined in 11339 * enum %MPDU_START_DECAP_TYPE_*. 11340 * 11341 * rx_insert_vlan_c_tag_padding 11342 * rx_insert_vlan_s_tag_padding 11343 * Insert 4 byte of all zeros as VLAN tag or double VLAN tag if 11344 * the rx payload does not have VLAN. 11345 * 11346 * strip_vlan_c_tag_decap 11347 * strip_vlan_s_tag_decap 11348 * Strip VLAN or double VLAN during decapsulation. 11349 * 11350 * pre_delim_count 11351 * The number of delimiters before this MPDU. Note that this 11352 * number is cleared at PPDU start. If this MPDU is the first 11353 * received MPDU in the PPDU and this MPDU gets filtered-in, 11354 * this field will indicate the number of delimiters located 11355 * after the last MPDU in the previous PPDU. 11356 * 11357 * If this MPDU is located after the first received MPDU in 11358 * an PPDU, this field will indicate the number of delimiters 11359 * located between the previous MPDU and this MPDU. 11360 * 11361 * ampdu_flag 11362 * Received frame was part of an A-MPDU. 11363 * 11364 * bar_frame 11365 * Received frame is a BAR frame 11366 * 11367 * raw_mpdu 11368 * Set when no 802.11 to nwifi/ethernet hdr conversion is done 11369 * 11370 * mpdu_length 11371 * MPDU length before decapsulation. 11372 * 11373 * first_mpdu 11374 * Indicates the first MSDU of the PPDU. If both first_mpdu 11375 * and last_mpdu are set in the MSDU then this is a not an 11376 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 11377 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 11378 * 0. The PPDU start status will only be valid when this bit 11379 * is set. 11380 * 11381 * mcast_bcast 11382 * Multicast / broadcast indicator. Only set when the MAC 11383 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 11384 * matches one of the 4 BSSID registers. Only set when 11385 * first_msdu is set. 11386 * 11387 * ast_index_not_found 11388 * Only valid when first_msdu is set. Indicates no AST matching 11389 * entries within the max search count. 11390 * 11391 * ast_index_timeout 11392 * Only valid when first_msdu is set. Indicates an unsuccessful 11393 * search in the address search table due to timeout. 11394 * 11395 * power_mgmt 11396 * Power management bit set in the 802.11 header. Only set 11397 * when first_msdu is set. 11398 * 11399 * non_qos 11400 * Set if packet is not a non-QoS data frame. Only set when 11401 * first_msdu is set. 11402 * 11403 * null_data 11404 * Set if frame type indicates either null data or QoS null 11405 * data format. Only set when first_msdu is set. 11406 * 11407 * mgmt_type 11408 * Set if packet is a management packet. Only set when 11409 * first_msdu is set. 11410 * 11411 * ctrl_type 11412 * Set if packet is a control packet. Only set when first_msdu 11413 * is set. 11414 * 11415 * more_data 11416 * Set if more bit in frame control is set. Only set when 11417 * first_msdu is set. 11418 * 11419 * eosp 11420 * Set if the EOSP (end of service period) bit in the QoS 11421 * control field is set. Only set when first_msdu is set. 11422 * 11423 * 11424 * fragment_flag 11425 * Fragment indication 11426 * 11427 * order 11428 * Set if the order bit in the frame control is set. Only 11429 * set when first_msdu is set. 11430 * 11431 * u_apsd_trigger 11432 * U-APSD trigger frame 11433 * 11434 * encrypt_required 11435 * Indicates that this data type frame is not encrypted even if 11436 * the policy for this MPDU requires encryption as indicated in 11437 * the peer table key type. 11438 * 11439 * directed 11440 * MPDU is a directed packet which means that the RA matched 11441 * our STA addresses. In proxySTA it means that the TA matched 11442 * an entry in our address search table with the corresponding 11443 * 'no_ack' bit is the address search entry cleared. 11444 * amsdu_present 11445 * AMSDU present 11446 * 11447 * mpdu_frame_control_field 11448 * Frame control field in header. Only valid when the field is marked valid. 11449 * 11450 * mpdu_duration_field 11451 * Duration field in header. Only valid when the field is marked valid. 11452 * 11453 * mac_addr_adx 11454 * MAC addresses in the received frame. Only valid when corresponding 11455 * address valid bit is set 11456 * 11457 * mpdu_qos_control_field, mpdu_ht_control_field 11458 * QoS/HT control fields from header. Valid only when corresponding fields 11459 * are marked valid 11460 * 11461 * vdev_id 11462 * Virtual device associated with this peer 11463 * RXOLE uses this to determine intra-BSS routing. 11464 * 11465 * service_code 11466 * Opaque service code between PPE and Wi-Fi 11467 * This field gets passed on by REO to PPE in the EDMA descriptor 11468 * ('REO_TO_PPE_RING'). 11469 * 11470 * priority_valid 11471 * This field gets passed on by REO to PPE in the EDMA descriptor 11472 * ('REO_TO_PPE_RING'). 11473 * 11474 * src_info 11475 * Source (virtual) device/interface info. associated with 11476 * this peer 11477 * This field gets passed on by REO to PPE in the EDMA descriptor 11478 * ('REO_TO_PPE_RING'). 11479 * 11480 * multi_link_addr_ad1_ad2_valid 11481 * If set, Rx OLE shall convert Address1 and Address2 of received 11482 * data frames to multi-link addresses during decapsulation to eth/nwifi 11483 * 11484 * multi_link_addr_ad1,ad2 11485 * Multi-link receiver address1,2. Only valid when corresponding 11486 * valid bit is set 11487 * 11488 * authorize_to_send_wds 11489 * If not set, RXDMA shall perform error-routing for WDS packets 11490 * as the sender is not authorized and might misuse WDS frame 11491 * format to inject packets with arbitrary DA/SA. 11492 * 11493 */ 11494 11495 enum rx_msdu_start_pkt_type { 11496 RX_MSDU_START_PKT_TYPE_11A, 11497 RX_MSDU_START_PKT_TYPE_11B, 11498 RX_MSDU_START_PKT_TYPE_11N, 11499 RX_MSDU_START_PKT_TYPE_11AC, 11500 RX_MSDU_START_PKT_TYPE_11AX, 11501 }; 11502 11503 enum rx_msdu_start_sgi { 11504 RX_MSDU_START_SGI_0_8_US, 11505 RX_MSDU_START_SGI_0_4_US, 11506 RX_MSDU_START_SGI_1_6_US, 11507 RX_MSDU_START_SGI_3_2_US, 11508 }; 11509 11510 enum rx_msdu_start_recv_bw { 11511 RX_MSDU_START_RECV_BW_20MHZ, 11512 RX_MSDU_START_RECV_BW_40MHZ, 11513 RX_MSDU_START_RECV_BW_80MHZ, 11514 RX_MSDU_START_RECV_BW_160MHZ, 11515 }; 11516 11517 enum rx_msdu_start_reception_type { 11518 RX_MSDU_START_RECEPTION_TYPE_SU, 11519 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 11520 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 11521 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 11522 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 11523 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 11524 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 11525 }; 11526 11527 #define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22) 11528 11529 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 11530 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 11531 11532 #define RX_MSDU_END_INFO1_REPORTED_MPDU_LENGTH GENMASK(13, 0) 11533 11534 #define RX_MSDU_END_INFO2_CCE_SUPER_RULE GENMASK(13, 8) 11535 #define RX_MSDU_END_INFO2_CCND_TRUNCATE BIT(14) 11536 #define RX_MSDU_END_INFO2_CCND_CCE_DIS BIT(15) 11537 11538 #define RX_MSDU_END_INFO3_DA_OFFSET GENMASK(5, 0) 11539 #define RX_MSDU_END_INFO3_SA_OFFSET GENMASK(11, 6) 11540 #define RX_MSDU_END_INFO3_DA_OFFSET_VALID BIT(12) 11541 #define RX_MSDU_END_INFO3_SA_OFFSET_VALID BIT(13) 11542 11543 #define RX_MSDU_END_INFO4_TCP_FLAG GENMASK(8, 0) 11544 #define RX_MSDU_END_INFO4_LRO_ELIGIBLE BIT(9) 11545 11546 #define RX_MSDU_END_INFO5_SA_IDX_TIMEOUT BIT(0) 11547 #define RX_MSDU_END_INFO5_DA_IDX_TIMEOUT BIT(1) 11548 #define RX_MSDU_END_INFO5_TO_DS BIT(2) 11549 #define RX_MSDU_END_INFO5_TID GENMASK(6, 3) 11550 #define RX_MSDU_END_INFO5_SA_IS_VALID BIT(7) 11551 #define RX_MSDU_END_INFO5_DA_IS_VALID BIT(8) 11552 #define RX_MSDU_END_INFO5_DA_IS_MCBC BIT(9) 11553 #define RX_MSDU_END_INFO5_L3_HDR_PADDING GENMASK(11, 10) 11554 #define RX_MSDU_END_INFO5_FIRST_MSDU BIT(12) 11555 #define RX_MSDU_END_INFO5_LAST_MSDU BIT(13) 11556 #define RX_MSDU_END_INFO5_FROM_DS BIT(14) 11557 #define RX_MSDU_END_INFO5_IP_CHKSUM_FAIL_COPY BIT(15) 11558 11559 #define RX_MSDU_END_INFO6_MSDU_DROP BIT(0) 11560 #define RX_MSDU_END_INFO6_REO_DEST_IND GENMASK(5, 1) 11561 #define RX_MSDU_END_INFO6_FLOW_IDX GENMASK(25, 6) 11562 #define RX_MSDU_END_INFO6_USE_PPE BIT(26) 11563 #define RX_MSDU_END_INFO6_MESH_STA GENMASK(28, 27) 11564 #define RX_MSDU_END_INFO6_VLAN_CTAG_STRIPPED BIT(29) 11565 #define RX_MSDU_END_INFO6_VLAN_STAG_STRIPPED BIT(30) 11566 #define RX_MSDU_END_INFO6_FRAGMENT_FLAG BIT(31) 11567 11568 #define RX_MSDU_END_INFO7_AGGR_COUNT GENMASK(7, 0) 11569 #define RX_MSDU_END_INFO7_FLOW_AGGR_CONTN BIT(8) 11570 #define RX_MSDU_END_INFO7_FISA_TIMEOUT BIT(9) 11571 11572 #define RX_MSDU_END_INFO7_TCPUDP_CSUM_FAIL_CPY BIT(10) 11573 #define RX_MSDU_END_INFO7_MSDU_LIMIT_ERROR BIT(11) 11574 #define RX_MSDU_END_INFO7_FLOW_IDX_TIMEOUT BIT(12) 11575 #define RX_MSDU_END_INFO7_FLOW_IDX_INVALID BIT(13) 11576 #define RX_MSDU_END_INFO7_CCE_MATCH BIT(14) 11577 #define RX_MSDU_END_INFO7_AMSDU_PARSER_ERR BIT(15) 11578 11579 #define RX_MSDU_END_INFO8_KEY_ID GENMASK(7, 0) 11580 11581 #define RX_MSDU_END_INFO9_SERVICE_CODE GENMASK(14, 6) 11582 #define RX_MSDU_END_INFO9_PRIORITY_VALID BIT(15) 11583 #define RX_MSDU_END_INFO9_INRA_BSS BIT(16) 11584 #define RX_MSDU_END_INFO9_DEST_CHIP_ID GENMASK(18, 17) 11585 #define RX_MSDU_END_INFO9_MCAST_ECHO BIT(19) 11586 #define RX_MSDU_END_INFO9_WDS_LEARN_EVENT BIT(20) 11587 #define RX_MSDU_END_INFO9_WDS_ROAM_EVENT BIT(21) 11588 #define RX_MSDU_END_INFO9_WDS_KEEP_ALIVE_EVENT BIT(22) 11589 11590 #define RX_MSDU_END_INFO10_MSDU_LENGTH GENMASK(13, 0) 11591 #define RX_MSDU_END_INFO10_STBC BIT(14) 11592 #define RX_MSDU_END_INFO10_IPSEC_ESP BIT(15) 11593 #define RX_MSDU_END_INFO10_L3_OFFSET GENMASK(22, 16) 11594 #define RX_MSDU_END_INFO10_IPSEC_AH BIT(23) 11595 #define RX_MSDU_END_INFO10_L4_OFFSET GENMASK(31, 24) 11596 11597 #define RX_MSDU_END_INFO11_MSDU_NUMBER GENMASK(7, 0) 11598 #define RX_MSDU_END_INFO11_DECAP_FORMAT GENMASK(9, 8) 11599 #define RX_MSDU_END_INFO11_IPV4 BIT(10) 11600 #define RX_MSDU_END_INFO11_IPV6 BIT(11) 11601 #define RX_MSDU_END_INFO11_TCP BIT(12) 11602 #define RX_MSDU_END_INFO11_UDP BIT(13) 11603 #define RX_MSDU_END_INFO11_IP_FRAG BIT(14) 11604 #define RX_MSDU_END_INFO11_TCP_ONLY_ACK BIT(15) 11605 #define RX_MSDU_END_INFO11_DA_IS_BCAST_MCAST BIT(16) 11606 #define RX_MSDU_END_INFO11_SEL_TOEPLITZ_HASH GENMASK(18, 17) 11607 #define RX_MSDU_END_INFO11_IP_FIXED_HDR_VALID BIT(19) 11608 #define RX_MSDU_END_INFO11_IP_EXTN_HDR_VALID BIT(20) 11609 #define RX_MSDU_END_INFO11_IP_TCP_UDP_HDR_VALID BIT(21) 11610 #define RX_MSDU_END_INFO11_MESH_CTRL_PRESENT BIT(22) 11611 #define RX_MSDU_END_INFO11_LDPC BIT(23) 11612 #define RX_MSDU_END_INFO11_IP4_IP6_NXT_HDR GENMASK(31, 24) 11613 11614 #define RX_MSDU_END_INFO12_USER_RSSI GENMASK(7, 0) 11615 #define RX_MSDU_END_INFO12_PKT_TYPE GENMASK(11, 8) 11616 #define RX_MSDU_END_INFO12_SGI GENMASK(13, 12) 11617 #define RX_MSDU_END_INFO12_RATE_MCS GENMASK(17, 14) 11618 #define RX_MSDU_END_INFO12_RECV_BW GENMASK(20, 18) 11619 #define RX_MSDU_END_INFO12_RECEPTION_TYPE GENMASK(23, 21) 11620 11621 #define RX_MSDU_END_INFO12_MIMO_SS_BITMAP GENMASK(30, 24) 11622 #define RX_MSDU_END_INFO12_MIMO_DONE_COPY BIT(31) 11623 11624 #define RX_MSDU_END_INFO13_FIRST_MPDU BIT(0) 11625 #define RX_MSDU_END_INFO13_MCAST_BCAST BIT(2) 11626 #define RX_MSDU_END_INFO13_AST_IDX_NOT_FOUND BIT(3) 11627 #define RX_MSDU_END_INFO13_AST_IDX_TIMEDOUT BIT(4) 11628 #define RX_MSDU_END_INFO13_POWER_MGMT BIT(5) 11629 #define RX_MSDU_END_INFO13_NON_QOS BIT(6) 11630 #define RX_MSDU_END_INFO13_NULL_DATA BIT(7) 11631 #define RX_MSDU_END_INFO13_MGMT_TYPE BIT(8) 11632 #define RX_MSDU_END_INFO13_CTRL_TYPE BIT(9) 11633 #define RX_MSDU_END_INFO13_MORE_DATA BIT(10) 11634 #define RX_MSDU_END_INFO13_EOSP BIT(11) 11635 #define RX_MSDU_END_INFO13_A_MSDU_ERROR BIT(12) 11636 #define RX_MSDU_END_INFO13_ORDER BIT(14) 11637 #define RX_MSDU_END_INFO13_OVERFLOW_ERR BIT(16) 11638 #define RX_MSDU_END_INFO13_MSDU_LEN_ERR BIT(17) 11639 #define RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL BIT(18) 11640 #define RX_MSDU_END_INFO13_IP_CKSUM_FAIL BIT(19) 11641 #define RX_MSDU_END_INFO13_SA_IDX_INVALID BIT(20) 11642 #define RX_MSDU_END_INFO13_DA_IDX_INVALID BIT(21) 11643 #define RX_MSDU_END_INFO13_AMSDU_ADDR_MISMATCH BIT(22) 11644 #define RX_MSDU_END_INFO13_RX_IN_TX_DECRYPT_BYP BIT(23) 11645 #define RX_MSDU_END_INFO13_ENCRYPT_REQUIRED BIT(24) 11646 #define RX_MSDU_END_INFO13_DIRECTED BIT(25) 11647 #define RX_MSDU_END_INFO13_BUFFER_FRAGMENT BIT(26) 11648 #define RX_MSDU_END_INFO13_MPDU_LEN_ERR BIT(27) 11649 #define RX_MSDU_END_INFO13_TKIP_MIC_ERR BIT(28) 11650 #define RX_MSDU_END_INFO13_DECRYPT_ERR BIT(29) 11651 #define RX_MSDU_END_INFO13_UNDECRYPT_FRAME_ERR BIT(30) 11652 #define RX_MSDU_END_INFO13_FCS_ERR BIT(31) 11653 11654 #define RX_MSDU_END_INFO13_WIFI_PARSER_ERR BIT(15) 11655 11656 #define RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE GENMASK(12, 10) 11657 #define RX_MSDU_END_INFO14_RX_BITMAP_NOT_UPDED BIT(13) 11658 #define RX_MSDU_END_INFO14_MSDU_DONE BIT(31) 11659 11660 struct rx_msdu_end_qcn9274 { 11661 uint16_t info0; 11662 uint16_t phy_ppdu_id; 11663 uint16_t ip_hdr_cksum; 11664 uint16_t info1; 11665 uint16_t info2; 11666 uint16_t cumulative_l3_checksum; 11667 uint32_t rule_indication0; 11668 uint32_t ipv6_options_crc; 11669 uint16_t info3; 11670 uint16_t l3_type; 11671 uint32_t rule_indication1; 11672 uint32_t tcp_seq_num; 11673 uint32_t tcp_ack_num; 11674 uint16_t info4; 11675 uint16_t window_size; 11676 uint16_t sa_sw_peer_id; 11677 uint16_t info5; 11678 uint16_t sa_idx; 11679 uint16_t da_idx_or_sw_peer_id; 11680 uint32_t info6; 11681 uint32_t fse_metadata; 11682 uint16_t cce_metadata; 11683 uint16_t tcp_udp_cksum; 11684 uint16_t info7; 11685 uint16_t cumulative_ip_length; 11686 uint32_t info8; 11687 uint32_t info9; 11688 uint32_t info10; 11689 uint32_t info11; 11690 uint16_t vlan_ctag_ci; 11691 uint16_t vlan_stag_ci; 11692 uint32_t peer_meta_data; 11693 uint32_t info12; 11694 uint32_t flow_id_toeplitz; 11695 uint32_t ppdu_start_timestamp_63_32; 11696 uint32_t phy_meta_data; 11697 uint32_t ppdu_start_timestamp_31_0; 11698 uint32_t toeplitz_hash_2_or_4; 11699 uint16_t res0; 11700 uint16_t sa_15_0; 11701 uint32_t sa_47_16; 11702 uint32_t info13; 11703 uint32_t info14; 11704 } __packed; 11705 11706 #define QCN9274_MSDU_END_SELECT_MSDU_END_TAG BIT(0) 11707 #define QCN9274_MSDU_END_SELECT_INFO0_PHY_PPDUID_IP_HDR_CSUM_INFO1 BIT(1) 11708 #define QCN9274_MSDU_END_SELECT_INFO2_CUMULATIVE_CSUM_RULE_IND_0 BIT(2) 11709 #define QCN9274_MSDU_END_SELECT_IPV6_OP_CRC_INFO3_TYPE13 BIT(3) 11710 #define QCN9274_MSDU_END_SELECT_RULE_IND_1_TCP_SEQ_NUM BIT(4) 11711 #define QCN9274_MSDU_END_SELECT_TCP_ACK_NUM_INFO4_WINDOW_SIZE BIT(5) 11712 #define QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID BIT(6) 11713 #define QCN9274_MSDU_END_SELECT_INFO6_FSE_METADATA BIT(7) 11714 #define QCN9274_MSDU_END_SELECT_CCE_MDATA_TCP_UDP_CSUM_INFO7_IP_LEN BIT(8) 11715 #define QCN9274_MSDU_END_SELECT_INFO8_INFO9 BIT(9) 11716 #define QCN9274_MSDU_END_SELECT_INFO10_INFO11 BIT(10) 11717 #define QCN9274_MSDU_END_SELECT_VLAN_CTAG_STAG_CI_PEER_MDATA BIT(11) 11718 #define QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ BIT(12) 11719 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA BIT(13) 11720 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_31_0_TOEPLITZ_HASH_2_4 BIT(14) 11721 #define QCN9274_MSDU_END_SELECT_RES0_SA_47_0 BIT(15) 11722 #define QCN9274_MSDU_END_SELECT_INFO13_INFO14 BIT(16) 11723 11724 #define QCN9274_MSDU_END_WMASK (QCN9274_MSDU_END_SELECT_MSDU_END_TAG | \ 11725 QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID | \ 11726 QCN9274_MSDU_END_SELECT_INFO10_INFO11 | \ 11727 QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ | \ 11728 QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA | \ 11729 QCN9274_MSDU_END_SELECT_INFO13_INFO14) 11730 11731 /* The below rx_msdu_end_qcn9274_compact structure is tied with the mask value 11732 * QCN9274_MSDU_END_WMASK. If the mask value changes the structure will also 11733 * change. 11734 */ 11735 11736 struct rx_msdu_end_qcn9274_compact { 11737 uint64_t msdu_end_tag; 11738 uint16_t sa_sw_peer_id; 11739 uint16_t info5; 11740 uint16_t sa_idx; 11741 uint16_t da_idx_or_sw_peer_id; 11742 uint32_t info10; 11743 uint32_t info11; 11744 uint32_t info12; 11745 uint32_t flow_id_toeplitz; 11746 uint32_t ppdu_start_timestamp_63_32; 11747 uint32_t phy_meta_data; 11748 uint32_t info13; 11749 uint32_t info14; 11750 } __packed; 11751 11752 /* rx_msdu_end 11753 * 11754 * rxpcu_mpdu_filter_in_category 11755 * Field indicates what the reason was that this mpdu frame 11756 * was allowed to come into the receive path by rxpcu. Values 11757 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11758 * 11759 * sw_frame_group_id 11760 * SW processes frames based on certain classifications. Values 11761 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11762 * 11763 * phy_ppdu_id 11764 * A ppdu counter value that PHY increments for every PPDU 11765 * received. The counter value wraps around. 11766 * 11767 * ip_hdr_cksum 11768 * This can include the IP header checksum or the pseudo 11769 * header checksum used by TCP/UDP checksum. 11770 * 11771 * reported_mpdu_length 11772 * MPDU length before decapsulation. Only valid when first_msdu is 11773 * set. This field is taken directly from the length field of the 11774 * A-MPDU delimiter or the preamble length field for non-A-MPDU 11775 * frames. 11776 * 11777 * cce_super_rule 11778 * Indicates the super filter rule. 11779 * 11780 * cce_classify_not_done_truncate 11781 * Classification failed due to truncated frame. 11782 * 11783 * cce_classify_not_done_cce_dis 11784 * Classification failed due to CCE global disable 11785 * 11786 * cumulative_l3_checksum 11787 * FISA: IP header checksum including the total MSDU length 11788 * that is part of this flow aggregated so far, reported if 11789 * 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 11790 * 11791 * rule_indication 11792 * Bitmap indicating which of rules have matched. 11793 * 11794 * ipv6_options_crc 11795 * 32 bit CRC computed out of IP v6 extension headers. 11796 * 11797 * da_offset 11798 * Offset into MSDU buffer for DA. 11799 * 11800 * sa_offset 11801 * Offset into MSDU buffer for SA. 11802 * 11803 * da_offset_valid 11804 * da_offset field is valid. This will be set to 0 in case 11805 * of a dynamic A-MSDU when DA is compressed. 11806 * 11807 * sa_offset_valid 11808 * sa_offset field is valid. This will be set to 0 in case 11809 * of a dynamic A-MSDU when SA is compressed. 11810 * 11811 * l3_type 11812 * The 16-bit type value indicating the type of L3 later 11813 * extracted from LLC/SNAP, set to zero if SNAP is not 11814 * available. 11815 * 11816 * tcp_seq_number 11817 * TCP sequence number. 11818 * 11819 * tcp_ack_number 11820 * TCP acknowledge number. 11821 * 11822 * tcp_flag 11823 * TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}. 11824 * 11825 * lro_eligible 11826 * Computed out of TCP and IP fields to indicate that this 11827 * MSDU is eligible for LRO. 11828 * 11829 * window_size 11830 * TCP receive window size. 11831 * 11832 * sa_sw_peer_id 11833 * sw_peer_id from the address search entry corresponding to the 11834 * source address of the MSDU. 11835 * 11836 * sa_idx_timeout 11837 * Indicates an unsuccessful MAC source address search due to the 11838 * expiring of the search timer. 11839 * 11840 * da_idx_timeout 11841 * Indicates an unsuccessful MAC destination address search due to 11842 * the expiring of the search timer. 11843 * 11844 * to_ds 11845 * Set if the to DS bit is set in the frame control. 11846 * 11847 * tid 11848 * TID field in the QoS control field 11849 * 11850 * sa_is_valid 11851 * Indicates that OLE found a valid SA entry. 11852 * 11853 * da_is_valid 11854 * Indicates that OLE found a valid DA entry. 11855 * 11856 * da_is_mcbc 11857 * Field Only valid if da_is_valid is set. Indicates the DA address 11858 * was a Multicast of Broadcast address. 11859 * 11860 * l3_header_padding 11861 * Number of bytes padded to make sure that the L3 header will 11862 * always start of a Dword boundary. 11863 * 11864 * first_msdu 11865 * Indicates the first MSDU of A-MSDU. If both first_msdu and 11866 * last_msdu are set in the MSDU then this is a non-aggregated MSDU 11867 * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both 11868 * first_mpdu and last_mpdu bits set to 0. 11869 * 11870 * last_msdu 11871 * Indicates the last MSDU of the A-MSDU. MPDU end status is only 11872 * valid when last_msdu is set. 11873 * 11874 * fr_ds 11875 * Set if the from DS bit is set in the frame control. 11876 * 11877 * ip_chksum_fail_copy 11878 * Indicates that the computed checksum did not match the 11879 * checksum in the IP header. 11880 * 11881 * sa_idx 11882 * The offset in the address table which matches the MAC source 11883 * address. 11884 * 11885 * da_idx_or_sw_peer_id 11886 * Based on a register configuration in RXOLE, this field will 11887 * contain: 11888 * The offset in the address table which matches the MAC destination 11889 * address 11890 * OR: 11891 * sw_peer_id from the address search entry corresponding to 11892 * the destination address of the MSDU 11893 * 11894 * msdu_drop 11895 * REO shall drop this MSDU and not forward it to any other ring. 11896 * 11897 * The id of the reo exit ring where the msdu frame shall push 11898 * after (MPDU level) reordering has finished. Values are defined 11899 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 11900 * 11901 * flow_idx 11902 * Flow table index. 11903 * 11904 * use_ppe 11905 * Indicates to RXDMA to ignore the REO_destination_indication 11906 * and use a programmed value corresponding to the REO2PPE 11907 * ring 11908 * 11909 * mesh_sta 11910 * When set, this is a Mesh (11s) STA. 11911 * 11912 * vlan_ctag_stripped 11913 * Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the 11914 * packet 11915 * 11916 * vlan_stag_stripped 11917 * Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the 11918 * packet 11919 * 11920 * fragment_flag 11921 * Indicates that this is an 802.11 fragment frame. This is 11922 * set when either the more_frag bit is set in the frame control 11923 * or the fragment number is not zero. Only set when first_msdu 11924 * is set. 11925 * 11926 * fse_metadata 11927 * FSE related meta data. 11928 * 11929 * cce_metadata 11930 * CCE related meta data. 11931 * 11932 * tcp_udp_chksum 11933 * The value of the computed TCP/UDP checksum. A mode bit 11934 * selects whether this checksum is the full checksum or the 11935 * partial checksum which does not include the pseudo header. 11936 * 11937 * aggregation_count 11938 * Number of MSDU's aggregated so far 11939 * 11940 * flow_aggregation_continuation 11941 * To indicate that this MSDU can be aggregated with 11942 * the previous packet with the same flow id 11943 * 11944 * fisa_timeout 11945 * To indicate that the aggregation has restarted for 11946 * this flow due to timeout 11947 * 11948 * tcp_udp_chksum_fail 11949 * Indicates that the computed checksum (tcp_udp_chksum) did 11950 * not match the checksum in the TCP/UDP header. 11951 * 11952 * msdu_limit_error 11953 * Indicates that the MSDU threshold was exceeded and thus all the 11954 * rest of the MSDUs will not be scattered and will not be 11955 * decapsulated but will be DMA'ed in RAW format as a single MSDU. 11956 * 11957 * flow_idx_timeout 11958 * Indicates an unsuccessful flow search due to the expiring of 11959 * the search timer. 11960 * 11961 * flow_idx_invalid 11962 * flow id is not valid. 11963 * 11964 * cce_match 11965 * Indicates that this status has a corresponding MSDU that 11966 * requires FW processing. The OLE will have classification 11967 * ring mask registers which will indicate the ring(s) for 11968 * packets and descriptors which need FW attention. 11969 * 11970 * amsdu_parser_error 11971 * A-MSDU could not be properly de-agregated. 11972 * 11973 * cumulative_ip_length 11974 * Total MSDU length that is part of this flow aggregated 11975 * so far 11976 * 11977 * key_id 11978 * The key ID octet from the IV. Only valid when first_msdu is set. 11979 * 11980 * service_code 11981 * Opaque service code between PPE and Wi-Fi 11982 * 11983 * priority_valid 11984 * This field gets passed on by REO to PPE in the EDMA descriptor 11985 * 11986 * intra_bss 11987 * This packet needs intra-BSS routing by SW as the 'vdev_id' 11988 * for the destination is the same as 'vdev_id' (from 'RX_MPDU_PCU_START') 11989 * that this MSDU was got in. 11990 * 11991 * dest_chip_id 11992 * If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 11993 * to support intra-BSS routing with multi-chip multi-link 11994 * operation. This indicates into which chip's TCL the packet should be 11995 * queueued 11996 * 11997 * multicast_echo 11998 * If set, this packet is a multicast echo, i.e. the DA is 11999 * multicast and Rx OLE SA search with mcast_echo_check = 1 12000 * passed. RXDMA should release such packets to WBM. 12001 * 12002 * wds_learning_event 12003 * If set, this packet has an SA search failure with WDS learning 12004 * enabled for the peer. RXOLE should route this TLV to the 12005 * RXDMA0 status ring to notify FW. 12006 * 12007 * wds_roaming_event 12008 * If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' 12009 * of the peer through which the packet was got, indicating 12010 * the SA node has roamed. RXOLE should route this TLV to 12011 * the RXDMA0 status ring to notify FW. 12012 * 12013 * wds_keep_alive_event 12014 * If set, the AST timestamp for this packet's SA is older 12015 * than the current timestamp by more than a threshold programmed 12016 * in RXOLE. RXOLE should route this TLV to the RXDMA0 status 12017 * ring to notify FW to keep the AST entry for the SA alive. 12018 * 12019 * msdu_length 12020 * MSDU length in bytes after decapsulation. 12021 * This field is still valid for MPDU frames without A-MSDU. 12022 * It still represents MSDU length after decapsulation 12023 * 12024 * stbc 12025 * When set, use STBC transmission rates. 12026 * 12027 * ipsec_esp 12028 * Set if IPv4/v6 packet is using IPsec ESP. 12029 * 12030 * l3_offset 12031 * Depending upon mode bit, this field either indicates the 12032 * L3 offset in bytes from the start of the RX_HEADER or the IP 12033 * offset in bytes from the start of the packet after 12034 * decapsulation. The latter is only valid if ipv4_proto or 12035 * ipv6_proto is set. 12036 * 12037 * ipsec_ah 12038 * Set if IPv4/v6 packet is using IPsec AH 12039 * 12040 * l4_offset 12041 * Depending upon mode bit, this field either indicates the 12042 * L4 offset in bytes from the start of RX_HEADER (only valid 12043 * if either ipv4_proto or ipv6_proto is set to 1) or indicates 12044 * the offset in bytes to the start of TCP or UDP header from 12045 * the start of the IP header after decapsulation (Only valid if 12046 * tcp_proto or udp_proto is set). The value 0 indicates that 12047 * the offset is longer than 127 bytes. 12048 * 12049 * msdu_number 12050 * Indicates the MSDU number within a MPDU. This value is 12051 * reset to zero at the start of each MPDU. If the number of 12052 * MSDU exceeds 255 this number will wrap using modulo 256. 12053 * 12054 * decap_type 12055 * Indicates the format after decapsulation. Values are defined in 12056 * enum %MPDU_START_DECAP_TYPE_*. 12057 * 12058 * ipv4_proto 12059 * Set if L2 layer indicates IPv4 protocol. 12060 * 12061 * ipv6_proto 12062 * Set if L2 layer indicates IPv6 protocol. 12063 * 12064 * tcp_proto 12065 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 12066 * indicates TCP. 12067 * 12068 * udp_proto 12069 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 12070 * indicates UDP. 12071 * 12072 * ip_frag 12073 * Indicates that either the IP More frag bit is set or IP frag 12074 * number is non-zero. If set indicates that this is a fragmented 12075 * IP packet. 12076 * 12077 * tcp_only_ack 12078 * Set if only the TCP Ack bit is set in the TCP flags and if 12079 * the TCP payload is 0. 12080 * 12081 * da_is_bcast_mcast 12082 * The destination address is broadcast or multicast. 12083 * 12084 * toeplitz_hash 12085 * Actual chosen Hash. 12086 * 0 - Toeplitz hash of 2-tuple (IP source address, IP 12087 * destination address) 12088 * 1 - Toeplitz hash of 4-tuple (IP source address, 12089 * IP destination address, L4 (TCP/UDP) source port, 12090 * L4 (TCP/UDP) destination port) 12091 * 2 - Toeplitz of flow_id 12092 * 3 - Zero is used 12093 * 12094 * ip_fixed_header_valid 12095 * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 12096 * fully within first 256 bytes of the packet 12097 * 12098 * ip_extn_header_valid 12099 * IPv6/IPv6 header, including IPv4 options and 12100 * recognizable extension headers parsed fully within first 256 12101 * bytes of the packet 12102 * 12103 * tcp_udp_header_valid 12104 * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 12105 * header parsed fully within first 256 bytes of the packet 12106 * 12107 * mesh_control_present 12108 * When set, this MSDU includes the 'Mesh Control' field 12109 * 12110 * ldpc 12111 * 12112 * ip4_protocol_ip6_next_header 12113 * For IPv4, this is the 8 bit protocol field set). For IPv6 this 12114 * is the 8 bit next_header field. 12115 * 12116 * 12117 * vlan_ctag_ci 12118 * 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC 12119 * 12120 * vlan_stag_ci 12121 * 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC 12122 * in case of double VLAN 12123 * 12124 * peer_meta_data 12125 * Meta data that SW has programmed in the Peer table entry 12126 * of the transmitting STA. 12127 * 12128 * user_rssi 12129 * RSSI for this user 12130 * 12131 * pkt_type 12132 * Values are defined in enum %RX_MSDU_START_PKT_TYPE_*. 12133 * 12134 * sgi 12135 * Field only valid when pkt type is HT, VHT or HE. Values are 12136 * defined in enum %RX_MSDU_START_SGI_*. 12137 * 12138 * rate_mcs 12139 * MCS Rate used. 12140 * 12141 * receive_bandwidth 12142 * Full receive Bandwidth. Values are defined in enum 12143 * %RX_MSDU_START_RECV_*. 12144 * 12145 * reception_type 12146 * Indicates what type of reception this is and defined in enum 12147 * %RX_MSDU_START_RECEPTION_TYPE_*. 12148 * 12149 * mimo_ss_bitmap 12150 * Field only valid when 12151 * Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or 12152 * RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO. 12153 * 12154 * Bitmap, with each bit indicating if the related spatial 12155 * stream is used for this STA 12156 * 12157 * LSB related to SS 0 12158 * 12159 * 0 - spatial stream not used for this reception 12160 * 1 - spatial stream used for this reception 12161 * 12162 * msdu_done_copy 12163 * If set indicates that the RX packet data, RX header data, 12164 * RX PPDU start descriptor, RX MPDU start/end descriptor, 12165 * RX MSDU start/end descriptors and RX Attention descriptor 12166 * are all valid. This bit is in the last 64-bit of the descriptor 12167 * expected to be subscribed in future hardware. 12168 * 12169 * flow_id_toeplitz 12170 * Toeplitz hash of 5-tuple 12171 * {IP source address, IP destination address, IP source port, IP 12172 * destination port, L4 protocol} in case of non-IPSec. 12173 * 12174 * In case of IPSec - Toeplitz hash of 4-tuple 12175 * {IP source address, IP destination address, SPI, L4 protocol} 12176 * 12177 * The relevant Toeplitz key registers are provided in RxOLE's 12178 * instance of common parser module. These registers are separate 12179 * from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 12180 * The actual value will be passed on from common parser module 12181 * to RxOLE in one of the WHO_* TLVs. 12182 * 12183 * ppdu_start_timestamp 12184 * Timestamp that indicates when the PPDU that contained this MPDU 12185 * started on the medium. 12186 * 12187 * phy_meta_data 12188 * SW programmed Meta data provided by the PHY. Can be used for SW 12189 * to indicate the channel the device is on. 12190 * 12191 * toeplitz_hash_2_or_4 12192 * Controlled by multiple RxOLE registers for TCP/UDP over 12193 * IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple 12194 * IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz 12195 * hash computed over 4-tuple IPv4 or IPv6 src/dest addresses 12196 * and src/dest ports is reported. The Flow_id_toeplitz hash 12197 * can also be reported here. Usually the hash reported here 12198 * is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 12199 * in 'RXPT_CLASSIFY_INFO'). 12200 * 12201 * sa 12202 * Source MAC address 12203 * 12204 * first_mpdu 12205 * Indicates the first MSDU of the PPDU. If both first_mpdu 12206 * and last_mpdu are set in the MSDU then this is a not an 12207 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 12208 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 12209 * 0. The PPDU start status will only be valid when this bit 12210 * is set. 12211 * 12212 * mcast_bcast 12213 * Multicast / broadcast indicator. Only set when the MAC 12214 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 12215 * matches one of the 4 BSSID registers. Only set when 12216 * first_msdu is set. 12217 * 12218 * ast_index_not_found 12219 * Only valid when first_msdu is set. Indicates no AST matching 12220 * entries within the max search count. 12221 * 12222 * ast_index_timeout 12223 * Only valid when first_msdu is set. Indicates an unsuccessful 12224 * search in the address search table due to timeout. 12225 * 12226 * power_mgmt 12227 * Power management bit set in the 802.11 header. Only set 12228 * when first_msdu is set. 12229 * 12230 * non_qos 12231 * Set if packet is not a non-QoS data frame. Only set when 12232 * first_msdu is set. 12233 * 12234 * null_data 12235 * Set if frame type indicates either null data or QoS null 12236 * data format. Only set when first_msdu is set. 12237 * 12238 * mgmt_type 12239 * Set if packet is a management packet. Only set when 12240 * first_msdu is set. 12241 * 12242 * ctrl_type 12243 * Set if packet is a control packet. Only set when first_msdu 12244 * is set. 12245 * 12246 * more_data 12247 * Set if more bit in frame control is set. Only set when 12248 * first_msdu is set. 12249 * 12250 * eosp 12251 * Set if the EOSP (end of service period) bit in the QoS 12252 * control field is set. Only set when first_msdu is set. 12253 * 12254 * a_msdu_error 12255 * Set if number of MSDUs in A-MSDU is above a threshold or if the 12256 * size of the MSDU is invalid. This receive buffer will contain 12257 * all of the remainder of MSDUs in this MPDU w/o decapsulation. 12258 * 12259 * order 12260 * Set if the order bit in the frame control is set. Only 12261 * set when first_msdu is set. 12262 * 12263 * wifi_parser_error 12264 * Indicates that the WiFi frame has one of the following errors 12265 * 12266 * overflow_err 12267 * RXPCU Receive FIFO ran out of space to receive the full MPDU. 12268 * Therefore this MPDU is terminated early and is thus corrupted. 12269 * 12270 * This MPDU will not be ACKed. 12271 * 12272 * RXPCU might still be able to correctly receive the following 12273 * MPDUs in the PPDU if enough fifo space became available in time. 12274 * 12275 * mpdu_length_err 12276 * Set by RXPCU if the expected MPDU length does not correspond 12277 * with the actually received number of bytes in the MPDU. 12278 * 12279 * tcp_udp_chksum_fail 12280 * Indicates that the computed checksum (tcp_udp_chksum) did 12281 * not match the checksum in the TCP/UDP header. 12282 * 12283 * ip_chksum_fail 12284 * Indicates that the computed checksum did not match the 12285 * checksum in the IP header. 12286 * 12287 * sa_idx_invalid 12288 * Indicates no matching entry was found in the address search 12289 * table for the source MAC address. 12290 * 12291 * da_idx_invalid 12292 * Indicates no matching entry was found in the address search 12293 * table for the destination MAC address. 12294 * 12295 * amsdu_addr_mismatch 12296 * Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching 12297 * TA or an A-MDU with 'to DS = 0' had a DA mismatching RA 12298 * 12299 * rx_in_tx_decrypt_byp 12300 * Indicates that RX packet is not decrypted as Crypto is busy 12301 * with TX packet processing. 12302 * 12303 * encrypt_required 12304 * Indicates that this data type frame is not encrypted even if 12305 * the policy for this MPDU requires encryption as indicated in 12306 * the peer table key type. 12307 * 12308 * directed 12309 * MPDU is a directed packet which means that the RA matched 12310 * our STA addresses. In proxySTA it means that the TA matched 12311 * an entry in our address search table with the corresponding 12312 * 'no_ack' bit is the address search entry cleared. 12313 * 12314 * buffer_fragment 12315 * Indicates that at least one of the rx buffers has been 12316 * fragmented. If set the FW should look at the rx_frag_info 12317 * descriptor described below. 12318 * 12319 * mpdu_length_err 12320 * Indicates that the MPDU was pre-maturely terminated 12321 * resulting in a truncated MPDU. Don't trust the MPDU length 12322 * field. 12323 * 12324 * tkip_mic_err 12325 * Indicates that the MPDU Michael integrity check failed 12326 * 12327 * decrypt_err 12328 * Indicates that the MPDU decrypt integrity check failed 12329 * 12330 * fcs_err 12331 * Indicates that the MPDU FCS check failed 12332 * 12333 * flow_idx_timeout 12334 * Indicates an unsuccessful flow search due to the expiring of 12335 * the search timer. 12336 * 12337 * flow_idx_invalid 12338 * flow id is not valid. 12339 * 12340 * decrypt_status_code 12341 * Field provides insight into the decryption performed. Values 12342 * are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*. 12343 * 12344 * rx_bitmap_not_updated 12345 * Frame is received, but RXPCU could not update the receive bitmap 12346 * due to (temporary) fifo constraints. 12347 * 12348 * msdu_done 12349 * If set indicates that the RX packet data, RX header data, RX 12350 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 12351 * start/end descriptors and RX Attention descriptor are all 12352 * valid. This bit must be in the last octet of the 12353 * descriptor. 12354 * 12355 */ 12356 12357 struct hal_rx_desc_qcn9274 { 12358 struct rx_msdu_end_qcn9274 msdu_end; 12359 struct rx_mpdu_start_qcn9274 mpdu_start; 12360 uint8_t msdu_payload[]; 12361 } __packed; 12362 12363 struct hal_rx_desc_qcn9274_compact { 12364 struct rx_msdu_end_qcn9274_compact msdu_end; 12365 struct rx_mpdu_start_qcn9274_compact mpdu_start; 12366 uint8_t msdu_payload[]; 12367 } __packed; 12368 12369 #define RX_BE_PADDING0_BYTES 8 12370 #define RX_BE_PADDING1_BYTES 8 12371 12372 #define HAL_RX_BE_PKT_HDR_TLV_LEN 112 12373 12374 struct rx_pkt_hdr_tlv { 12375 uint64_t tag; 12376 uint64_t phy_ppdu_id; 12377 uint8_t rx_pkt_hdr[HAL_RX_BE_PKT_HDR_TLV_LEN]; 12378 }; 12379 12380 struct hal_rx_desc_wcn7850 { 12381 uint64_t msdu_end_tag; 12382 struct rx_msdu_end_qcn9274 msdu_end; 12383 uint8_t rx_padding0[RX_BE_PADDING0_BYTES]; 12384 uint64_t mpdu_start_tag; 12385 struct rx_mpdu_start_qcn9274 mpdu_start; 12386 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 12387 uint8_t msdu_payload[]; 12388 } __packed; 12389 12390 struct hal_rx_desc { 12391 union { 12392 struct hal_rx_desc_qcn9274 qcn9274; 12393 struct hal_rx_desc_qcn9274_compact qcn9274_compact; 12394 struct hal_rx_desc_wcn7850 wcn7850; 12395 } u; 12396 } __packed; 12397 12398 #define HAL_RX_RU_ALLOC_TYPE_MAX 6 12399 #define RU_26 1 12400 #define RU_52 2 12401 #define RU_106 4 12402 #define RU_242 9 12403 #define RU_484 18 12404 #define RU_996 37 12405 12406 /* 12407 * dp.h 12408 */ 12409 12410 /* HTT definitions */ 12411 12412 #define HTT_TCL_META_DATA_TYPE BIT(0) 12413 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 12414 12415 /* vdev meta data */ 12416 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 12417 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 12418 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 12419 12420 /* peer meta data */ 12421 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 12422 12423 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 12424 12425 #define HTT_INVALID_PEER_ID 0xffff 12426 12427 /* HTT tx completion is overlaid in wbm_release_ring */ 12428 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 12429 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 12430 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 12431 12432 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 12433 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0) 12434 #define HTT_TX_WBM_COMP_INFO2_VALID BIT(21) 12435 12436 struct htt_tx_wbm_completion { 12437 uint32_t info0; 12438 uint32_t info1; 12439 uint32_t info2; 12440 uint32_t info3; 12441 } __packed; 12442 12443 enum htt_h2t_msg_type { 12444 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 12445 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 12446 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 12447 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 12448 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 12449 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 12450 }; 12451 12452 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 12453 12454 struct htt_ver_req_cmd { 12455 uint32_t ver_reg_info; 12456 } __packed; 12457 12458 enum htt_srng_ring_type { 12459 HTT_HW_TO_SW_RING, 12460 HTT_SW_TO_HW_RING, 12461 HTT_SW_TO_SW_RING, 12462 }; 12463 12464 enum htt_srng_ring_id { 12465 HTT_RXDMA_HOST_BUF_RING, 12466 HTT_RXDMA_MONITOR_STATUS_RING, 12467 HTT_RXDMA_MONITOR_BUF_RING, 12468 HTT_RXDMA_MONITOR_DESC_RING, 12469 HTT_RXDMA_MONITOR_DEST_RING, 12470 HTT_HOST1_TO_FW_RXBUF_RING, 12471 HTT_HOST2_TO_FW_RXBUF_RING, 12472 HTT_RXDMA_NON_MONITOR_DEST_RING, 12473 }; 12474 12475 /* host -> target HTT_SRING_SETUP message 12476 * 12477 * After target is booted up, Host can send SRING setup message for 12478 * each host facing LMAC SRING. Target setups up HW registers based 12479 * on setup message and confirms back to Host if response_required is set. 12480 * Host should wait for confirmation message before sending new SRING 12481 * setup message 12482 * 12483 * The message would appear as follows: 12484 * 12485 * |31 24|23 20|19|18 16|15|14 8|7 0| 12486 * |--------------- +-----------------+----------------+------------------| 12487 * | ring_type | ring_id | pdev_id | msg_type | 12488 * |----------------------------------------------------------------------| 12489 * | ring_base_addr_lo | 12490 * |----------------------------------------------------------------------| 12491 * | ring_base_addr_hi | 12492 * |----------------------------------------------------------------------| 12493 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 12494 * |----------------------------------------------------------------------| 12495 * | ring_head_offset32_remote_addr_lo | 12496 * |----------------------------------------------------------------------| 12497 * | ring_head_offset32_remote_addr_hi | 12498 * |----------------------------------------------------------------------| 12499 * | ring_tail_offset32_remote_addr_lo | 12500 * |----------------------------------------------------------------------| 12501 * | ring_tail_offset32_remote_addr_hi | 12502 * |----------------------------------------------------------------------| 12503 * | ring_msi_addr_lo | 12504 * |----------------------------------------------------------------------| 12505 * | ring_msi_addr_hi | 12506 * |----------------------------------------------------------------------| 12507 * | ring_msi_data | 12508 * |----------------------------------------------------------------------| 12509 * | intr_timer_th |IM| intr_batch_counter_th | 12510 * |----------------------------------------------------------------------| 12511 * | reserved |RR|PTCF| intr_low_threshold | 12512 * |----------------------------------------------------------------------| 12513 * Where 12514 * IM = sw_intr_mode 12515 * RR = response_required 12516 * PTCF = prefetch_timer_cfg 12517 * 12518 * The message is interpreted as follows: 12519 * dword0 - b'0:7 - msg_type: This will be set to 12520 * HTT_H2T_MSG_TYPE_SRING_SETUP 12521 * b'8:15 - pdev_id: 12522 * 0 (for rings at SOC/UMAC level), 12523 * 1/2/3 mac id (for rings at LMAC level) 12524 * b'16:23 - ring_id: identify which ring is to setup, 12525 * more details can be got from enum htt_srng_ring_id 12526 * b'24:31 - ring_type: identify type of host rings, 12527 * more details can be got from enum htt_srng_ring_type 12528 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 12529 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 12530 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 12531 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 12532 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 12533 * SW_TO_HW_RING. 12534 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 12535 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 12536 * Lower 32 bits of memory address of the remote variable 12537 * storing the 4-byte word offset that identifies the head 12538 * element within the ring. 12539 * (The head offset variable has type uint32_t.) 12540 * Valid for HW_TO_SW and SW_TO_SW rings. 12541 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 12542 * Upper 32 bits of memory address of the remote variable 12543 * storing the 4-byte word offset that identifies the head 12544 * element within the ring. 12545 * (The head offset variable has type uint32_t.) 12546 * Valid for HW_TO_SW and SW_TO_SW rings. 12547 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 12548 * Lower 32 bits of memory address of the remote variable 12549 * storing the 4-byte word offset that identifies the tail 12550 * element within the ring. 12551 * (The tail offset variable has type uint32_t.) 12552 * Valid for HW_TO_SW and SW_TO_SW rings. 12553 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 12554 * Upper 32 bits of memory address of the remote variable 12555 * storing the 4-byte word offset that identifies the tail 12556 * element within the ring. 12557 * (The tail offset variable has type uint32_t.) 12558 * Valid for HW_TO_SW and SW_TO_SW rings. 12559 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 12560 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12561 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 12562 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12563 * dword10 - b'0:31 - ring_msi_data: MSI data 12564 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 12565 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12566 * dword11 - b'0:14 - intr_batch_counter_th: 12567 * batch counter threshold is in units of 4-byte words. 12568 * HW internally maintains and increments batch count. 12569 * (see SRING spec for detail description). 12570 * When batch count reaches threshold value, an interrupt 12571 * is generated by HW. 12572 * b'15 - sw_intr_mode: 12573 * This configuration shall be static. 12574 * Only programmed at power up. 12575 * 0: generate pulse style sw interrupts 12576 * 1: generate level style sw interrupts 12577 * b'16:31 - intr_timer_th: 12578 * The timer init value when timer is idle or is 12579 * initialized to start downcounting. 12580 * In 8us units (to cover a range of 0 to 524 ms) 12581 * dword12 - b'0:15 - intr_low_threshold: 12582 * Used only by Consumer ring to generate ring_sw_int_p. 12583 * Ring entries low threshold water mark, that is used 12584 * in combination with the interrupt timer as well as 12585 * the clearing of the level interrupt. 12586 * b'16:18 - prefetch_timer_cfg: 12587 * Used only by Consumer ring to set timer mode to 12588 * support Application prefetch handling. 12589 * The external tail offset/pointer will be updated 12590 * at following intervals: 12591 * 3'b000: (Prefetch feature disabled; used only for debug) 12592 * 3'b001: 1 usec 12593 * 3'b010: 4 usec 12594 * 3'b011: 8 usec (default) 12595 * 3'b100: 16 usec 12596 * Others: Reserved 12597 * b'19 - response_required: 12598 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 12599 * b'20:31 - reserved: reserved for future use 12600 */ 12601 12602 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12603 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12604 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 12605 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 12606 12607 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 12608 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 12609 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 12610 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 12611 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 12612 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 12613 12614 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 12615 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 12616 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 12617 12618 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 12619 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 12620 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 12621 12622 struct htt_srng_setup_cmd { 12623 uint32_t info0; 12624 uint32_t ring_base_addr_lo; 12625 uint32_t ring_base_addr_hi; 12626 uint32_t info1; 12627 uint32_t ring_head_off32_remote_addr_lo; 12628 uint32_t ring_head_off32_remote_addr_hi; 12629 uint32_t ring_tail_off32_remote_addr_lo; 12630 uint32_t ring_tail_off32_remote_addr_hi; 12631 uint32_t ring_msi_addr_lo; 12632 uint32_t ring_msi_addr_hi; 12633 uint32_t msi_data; 12634 uint32_t intr_info; 12635 uint32_t info2; 12636 } __packed; 12637 12638 /* host -> target FW PPDU_STATS config message 12639 * 12640 * @details 12641 * The following field definitions describe the format of the HTT host 12642 * to target FW for PPDU_STATS_CFG msg. 12643 * The message allows the host to configure the PPDU_STATS_IND messages 12644 * produced by the target. 12645 * 12646 * |31 24|23 16|15 8|7 0| 12647 * |-----------------------------------------------------------| 12648 * | REQ bit mask | pdev_mask | msg type | 12649 * |-----------------------------------------------------------| 12650 * Header fields: 12651 * - MSG_TYPE 12652 * Bits 7:0 12653 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 12654 * Value: 0x11 12655 * - PDEV_MASK 12656 * Bits 8:15 12657 * Purpose: identifies which pdevs this PPDU stats configuration applies to 12658 * Value: This is a overloaded field, refer to usage and interpretation of 12659 * PDEV in interface document. 12660 * Bit 8 : Reserved for SOC stats 12661 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 12662 * Indicates MACID_MASK in DBS 12663 * - REQ_TLV_BIT_MASK 12664 * Bits 16:31 12665 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 12666 * needs to be included in the target's PPDU_STATS_IND messages. 12667 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 12668 * 12669 */ 12670 12671 struct htt_ppdu_stats_cfg_cmd { 12672 uint32_t msg; 12673 } __packed; 12674 12675 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 12676 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 12677 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 12678 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 12679 12680 enum htt_ppdu_stats_tag_type { 12681 HTT_PPDU_STATS_TAG_COMMON, 12682 HTT_PPDU_STATS_TAG_USR_COMMON, 12683 HTT_PPDU_STATS_TAG_USR_RATE, 12684 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 12685 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 12686 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 12687 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 12688 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 12689 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 12690 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 12691 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 12692 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 12693 HTT_PPDU_STATS_TAG_INFO, 12694 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 12695 12696 /* New TLV's are added above to this line */ 12697 HTT_PPDU_STATS_TAG_MAX, 12698 }; 12699 12700 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 12701 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 12702 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 12703 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 12704 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 12705 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 12706 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 12707 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 12708 12709 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 12710 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 12711 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 12712 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 12713 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 12714 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 12715 HTT_PPDU_STATS_TAG_DEFAULT) 12716 12717 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 12718 * 12719 * details: 12720 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 12721 * configure RXDMA rings. 12722 * The configuration is per ring based and includes both packet subtypes 12723 * and PPDU/MPDU TLVs. 12724 * 12725 * The message would appear as follows: 12726 * 12727 * |31 26|25|24|23 16|15 8|7 0| 12728 * |-----------------+----------------+----------------+---------------| 12729 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 12730 * |-------------------------------------------------------------------| 12731 * | rsvd2 | ring_buffer_size | 12732 * |-------------------------------------------------------------------| 12733 * | packet_type_enable_flags_0 | 12734 * |-------------------------------------------------------------------| 12735 * | packet_type_enable_flags_1 | 12736 * |-------------------------------------------------------------------| 12737 * | packet_type_enable_flags_2 | 12738 * |-------------------------------------------------------------------| 12739 * | packet_type_enable_flags_3 | 12740 * |-------------------------------------------------------------------| 12741 * | tlv_filter_in_flags | 12742 * |-------------------------------------------------------------------| 12743 * Where: 12744 * PS = pkt_swap 12745 * SS = status_swap 12746 * The message is interpreted as follows: 12747 * dword0 - b'0:7 - msg_type: This will be set to 12748 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 12749 * b'8:15 - pdev_id: 12750 * 0 (for rings at SOC/UMAC level), 12751 * 1/2/3 mac id (for rings at LMAC level) 12752 * b'16:23 - ring_id : Identify the ring to configure. 12753 * More details can be got from enum htt_srng_ring_id 12754 * b'24 - status_swap: 1 is to swap status TLV 12755 * b'25 - pkt_swap: 1 is to swap packet TLV 12756 * b'26:31 - rsvd1: reserved for future use 12757 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 12758 * in byte units. 12759 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 12760 * - b'16:31 - rsvd2: Reserved for future use 12761 * dword2 - b'0:31 - packet_type_enable_flags_0: 12762 * Enable MGMT packet from 0b0000 to 0b1001 12763 * bits from low to high: FP, MD, MO - 3 bits 12764 * FP: Filter_Pass 12765 * MD: Monitor_Direct 12766 * MO: Monitor_Other 12767 * 10 mgmt subtypes * 3 bits -> 30 bits 12768 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 12769 * dword3 - b'0:31 - packet_type_enable_flags_1: 12770 * Enable MGMT packet from 0b1010 to 0b1111 12771 * bits from low to high: FP, MD, MO - 3 bits 12772 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 12773 * dword4 - b'0:31 - packet_type_enable_flags_2: 12774 * Enable CTRL packet from 0b0000 to 0b1001 12775 * bits from low to high: FP, MD, MO - 3 bits 12776 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 12777 * dword5 - b'0:31 - packet_type_enable_flags_3: 12778 * Enable CTRL packet from 0b1010 to 0b1111, 12779 * MCAST_DATA, UCAST_DATA, NULL_DATA 12780 * bits from low to high: FP, MD, MO - 3 bits 12781 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 12782 * dword6 - b'0:31 - tlv_filter_in_flags: 12783 * Filter in Attention/MPDU/PPDU/Header/User tlvs 12784 * Refer to CFG_TLV_FILTER_IN_FLAG defs 12785 */ 12786 12787 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12788 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12789 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 12790 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 12791 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 12792 12793 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 12794 12795 enum htt_rx_filter_tlv_flags { 12796 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 12797 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 12798 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 12799 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 12800 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 12801 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 12802 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 12803 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 12804 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 12805 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 12806 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 12807 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 12808 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 12809 }; 12810 12811 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 12812 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 12813 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 12814 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 12815 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 12816 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 12817 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 12818 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 12819 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 12820 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 12821 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 12822 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 12823 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 12824 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 12825 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 12826 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 12827 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 12828 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 12829 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 12830 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 12831 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 12832 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 12833 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 12834 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 12835 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 12836 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 12837 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 12838 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 12839 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 12840 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 12841 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 12842 }; 12843 12844 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 12845 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 12846 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 12847 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 12848 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 12849 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 12850 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 12851 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 12852 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 12853 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 12854 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 12855 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 12856 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 12857 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 12858 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 12859 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 12860 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 12861 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 12862 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 12863 }; 12864 12865 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 12866 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 12867 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 12868 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 12869 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 12870 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 12871 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 12872 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 12873 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 12874 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 12875 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 12876 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 12877 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 12878 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 12879 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 12880 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 12881 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 12882 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 12883 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 12884 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 12885 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 12886 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 12887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 12888 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 12889 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 12890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 12891 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 12892 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 12893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 12894 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 12895 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 12896 }; 12897 12898 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 12899 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 12900 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 12901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 12902 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 12903 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 12904 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 12905 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 12906 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 12907 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 12908 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 12909 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 12910 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 12911 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 12912 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 12913 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 12914 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 12915 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 12916 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 12917 }; 12918 12919 enum htt_rx_data_pkt_filter_tlv_flasg3 { 12920 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 12921 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 12922 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 12923 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 12924 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 12925 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 12926 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 12927 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 12928 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 12929 }; 12930 12931 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 12932 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12933 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12934 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12935 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12936 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12937 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12938 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12939 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12940 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12941 12942 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 12943 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12944 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12945 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12946 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12947 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12948 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12949 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12950 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12951 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12952 12953 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 12954 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12955 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12956 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12957 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12958 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12959 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12960 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12961 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12962 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12963 12964 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12965 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12966 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12967 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12968 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12969 12970 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12971 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12972 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12973 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12974 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12975 12976 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12977 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12978 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12979 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12980 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12981 12982 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12983 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12984 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12985 12986 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12987 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12988 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12989 12990 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12991 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12992 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12993 12994 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12995 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12996 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12997 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12998 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12999 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 13000 13001 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 13002 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 13003 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 13004 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 13005 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 13006 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 13007 13008 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 13009 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 13010 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 13011 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 13012 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 13013 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 13014 13015 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 13016 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 13017 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 13018 13019 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 13020 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 13021 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 13022 13023 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 13024 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 13025 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 13026 13027 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 13028 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 13029 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 13030 13031 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 13032 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 13033 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 13034 13035 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 13036 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 13037 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 13038 13039 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 13040 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 13041 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 13042 13043 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 13044 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 13045 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 13046 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 13047 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 13048 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 13049 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 13050 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 13051 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 13052 13053 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 13054 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 13055 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 13056 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 13057 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 13058 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 13059 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 13060 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 13061 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 13062 13063 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 13064 13065 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 13066 13067 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 13068 13069 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 13070 13071 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 13072 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 13073 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 13074 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 13075 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 13076 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 13077 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 13078 13079 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 13080 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 13081 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 13082 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 13083 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 13084 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 13085 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 13086 13087 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 13088 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 13089 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 13090 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 13091 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 13092 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 13093 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 13094 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 13095 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 13096 13097 struct htt_rx_ring_selection_cfg_cmd { 13098 uint32_t info0; 13099 uint32_t info1; 13100 uint32_t pkt_type_en_flags0; 13101 uint32_t pkt_type_en_flags1; 13102 uint32_t pkt_type_en_flags2; 13103 uint32_t pkt_type_en_flags3; 13104 uint32_t rx_filter_tlv; 13105 } __packed; 13106 13107 struct htt_rx_ring_tlv_filter { 13108 uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */ 13109 uint32_t pkt_filter_flags0; /* MGMT */ 13110 uint32_t pkt_filter_flags1; /* MGMT */ 13111 uint32_t pkt_filter_flags2; /* CTRL */ 13112 uint32_t pkt_filter_flags3; /* DATA */ 13113 }; 13114 13115 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 13116 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 13117 13118 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 13119 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 13120 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 13121 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 13122 13123 /* Enumeration for full monitor mode destination ring select 13124 * 0 - REO destination ring select 13125 * 1 - FW destination ring select 13126 * 2 - SW destination ring select 13127 * 3 - Release destination ring select 13128 */ 13129 enum htt_rx_full_mon_release_ring { 13130 HTT_RX_MON_RING_REO, 13131 HTT_RX_MON_RING_FW, 13132 HTT_RX_MON_RING_SW, 13133 HTT_RX_MON_RING_RELEASE, 13134 }; 13135 13136 struct htt_rx_full_monitor_mode_cfg_cmd { 13137 uint32_t info0; 13138 uint32_t cfg; 13139 } __packed; 13140 13141 /* HTT message target->host */ 13142 13143 enum htt_t2h_msg_type { 13144 HTT_T2H_MSG_TYPE_VERSION_CONF, 13145 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 13146 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 13147 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 13148 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 13149 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 13150 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 13151 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 13152 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 13153 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 13154 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 13155 }; 13156 13157 #define HTT_TARGET_VERSION_MAJOR 3 13158 13159 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 13160 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 13161 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 13162 13163 struct htt_t2h_version_conf_msg { 13164 uint32_t version; 13165 } __packed; 13166 13167 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 13168 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 13169 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 13170 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 13171 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 13172 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 13173 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 13174 13175 struct htt_t2h_peer_map_event { 13176 uint32_t info; 13177 uint32_t mac_addr_l32; 13178 uint32_t info1; 13179 uint32_t info2; 13180 } __packed; 13181 13182 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 13183 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 13184 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 13185 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 13186 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 13187 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 13188 13189 struct htt_t2h_peer_unmap_event { 13190 uint32_t info; 13191 uint32_t mac_addr_l32; 13192 uint32_t info1; 13193 } __packed; 13194 13195 struct htt_resp_msg { 13196 union { 13197 struct htt_t2h_version_conf_msg version_msg; 13198 struct htt_t2h_peer_map_event peer_map_ev; 13199 struct htt_t2h_peer_unmap_event peer_unmap_ev; 13200 }; 13201 } __packed; 13202 13203 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 13204 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 13205 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 13206 13207 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 13208 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 13209 13210 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 13211 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 13212 13213 enum htt_backpressure_umac_ringid { 13214 HTT_SW_RING_IDX_REO_REO2SW1_RING, 13215 HTT_SW_RING_IDX_REO_REO2SW2_RING, 13216 HTT_SW_RING_IDX_REO_REO2SW3_RING, 13217 HTT_SW_RING_IDX_REO_REO2SW4_RING, 13218 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 13219 HTT_SW_RING_IDX_REO_REO2TCL_RING, 13220 HTT_SW_RING_IDX_REO_REO2FW_RING, 13221 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 13222 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 13223 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 13224 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 13225 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 13226 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 13227 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 13228 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 13229 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 13230 HTT_SW_RING_IDX_REO_REO_CMD_RING, 13231 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 13232 HTT_SW_UMAC_RING_IDX_MAX, 13233 }; 13234 13235 enum htt_backpressure_lmac_ringid { 13236 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 13237 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 13238 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 13239 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 13240 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 13241 HTT_SW_RING_IDX_RXDMA2FW_RING, 13242 HTT_SW_RING_IDX_RXDMA2SW_RING, 13243 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 13244 HTT_SW_RING_IDX_RXDMA2REO_RING, 13245 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 13246 HTT_SW_RING_IDX_MONITOR_BUF_RING, 13247 HTT_SW_RING_IDX_MONITOR_DESC_RING, 13248 HTT_SW_RING_IDX_MONITOR_DEST_RING, 13249 HTT_SW_LMAC_RING_IDX_MAX, 13250 }; 13251 13252 /* ppdu stats 13253 * 13254 * @details 13255 * The following field definitions describe the format of the HTT target 13256 * to host ppdu stats indication message. 13257 * 13258 * 13259 * |31 16|15 12|11 10|9 8|7 0 | 13260 * |----------------------------------------------------------------------| 13261 * | payload_size | rsvd |pdev_id|mac_id | msg type | 13262 * |----------------------------------------------------------------------| 13263 * | ppdu_id | 13264 * |----------------------------------------------------------------------| 13265 * | Timestamp in us | 13266 * |----------------------------------------------------------------------| 13267 * | reserved | 13268 * |----------------------------------------------------------------------| 13269 * | type-specific stats info | 13270 * | (see htt_ppdu_stats.h) | 13271 * |----------------------------------------------------------------------| 13272 * Header fields: 13273 * - MSG_TYPE 13274 * Bits 7:0 13275 * Purpose: Identifies this is a PPDU STATS indication 13276 * message. 13277 * Value: 0x1d 13278 * - mac_id 13279 * Bits 9:8 13280 * Purpose: mac_id of this ppdu_id 13281 * Value: 0-3 13282 * - pdev_id 13283 * Bits 11:10 13284 * Purpose: pdev_id of this ppdu_id 13285 * Value: 0-3 13286 * 0 (for rings at SOC level), 13287 * 1/2/3 PDEV -> 0/1/2 13288 * - payload_size 13289 * Bits 31:16 13290 * Purpose: total tlv size 13291 * Value: payload_size in bytes 13292 */ 13293 13294 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 13295 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 13296 13297 struct ath12k_htt_ppdu_stats_msg { 13298 uint32_t info; 13299 uint32_t ppdu_id; 13300 uint32_t timestamp; 13301 uint32_t rsvd; 13302 uint8_t data[]; 13303 } __packed; 13304 13305 struct htt_tlv { 13306 uint32_t header; 13307 uint8_t *value; 13308 } __packed; 13309 13310 #define HTT_TLV_TAG GENMASK(11, 0) 13311 #define HTT_TLV_LEN GENMASK(23, 12) 13312 13313 enum HTT_PPDU_STATS_BW { 13314 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 13315 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 13316 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 13317 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 13318 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 13319 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 13320 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 13321 }; 13322 13323 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 13324 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 13325 /* bw - HTT_PPDU_STATS_BW */ 13326 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 13327 13328 struct htt_ppdu_stats_common { 13329 uint32_t ppdu_id; 13330 uint16_t sched_cmdid; 13331 uint8_t ring_id; 13332 uint8_t num_users; 13333 uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 13334 uint32_t chain_mask; 13335 uint32_t fes_duration_us; /* frame exchange sequence */ 13336 uint32_t ppdu_sch_eval_start_tstmp_us; 13337 uint32_t ppdu_sch_end_tstmp_us; 13338 uint32_t ppdu_start_tstmp_us; 13339 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 13340 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 13341 */ 13342 uint16_t phy_mode; 13343 uint16_t bw_mhz; 13344 } __packed; 13345 13346 enum htt_ppdu_stats_gi { 13347 HTT_PPDU_STATS_SGI_0_8_US, 13348 HTT_PPDU_STATS_SGI_0_4_US, 13349 HTT_PPDU_STATS_SGI_1_6_US, 13350 HTT_PPDU_STATS_SGI_3_2_US, 13351 }; 13352 13353 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 13354 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 13355 13356 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 13357 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 13358 13359 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 13360 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 13361 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 13362 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 13363 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 13364 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 13365 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 13366 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 13367 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 13368 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 13369 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 13370 13371 #define HTT_USR_RATE_PREAMBLE(_val) \ 13372 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 13373 #define HTT_USR_RATE_BW(_val) \ 13374 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 13375 #define HTT_USR_RATE_NSS(_val) \ 13376 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 13377 #define HTT_USR_RATE_MCS(_val) \ 13378 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 13379 #define HTT_USR_RATE_GI(_val) \ 13380 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 13381 #define HTT_USR_RATE_DCM(_val) \ 13382 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 13383 13384 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 13385 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 13386 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 13387 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 13388 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 13389 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 13390 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 13391 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 13392 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 13393 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 13394 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 13395 13396 struct htt_ppdu_stats_user_rate { 13397 uint8_t tid_num; 13398 uint8_t reserved0; 13399 uint16_t sw_peer_id; 13400 uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 13401 uint16_t ru_end; 13402 uint16_t ru_start; 13403 uint16_t resp_ru_end; 13404 uint16_t resp_ru_start; 13405 uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 13406 uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 13407 /* Note: resp_rate_info is only valid for if resp_type is UL */ 13408 uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 13409 } __packed; 13410 13411 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 13412 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 13413 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 13414 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 13415 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 13416 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 13417 13418 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 13419 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 13420 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 13421 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 13422 #define HTT_TX_INFO_RATECODE(_flags) \ 13423 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 13424 #define HTT_TX_INFO_PEERID(_flags) \ 13425 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 13426 13427 struct htt_tx_ppdu_stats_info { 13428 struct htt_tlv tlv_hdr; 13429 uint32_t tx_success_bytes; 13430 uint32_t tx_retry_bytes; 13431 uint32_t tx_failed_bytes; 13432 uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 13433 uint16_t tx_success_msdus; 13434 uint16_t tx_retry_msdus; 13435 uint16_t tx_failed_msdus; 13436 uint16_t tx_duration; /* united in us */ 13437 } __packed; 13438 13439 enum htt_ppdu_stats_usr_compln_status { 13440 HTT_PPDU_STATS_USER_STATUS_OK, 13441 HTT_PPDU_STATS_USER_STATUS_FILTERED, 13442 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 13443 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 13444 HTT_PPDU_STATS_USER_STATUS_ABORT, 13445 }; 13446 13447 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 13448 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 13449 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 13450 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 13451 13452 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 13453 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 13454 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 13455 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 13456 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 13457 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 13458 13459 struct htt_ppdu_stats_usr_cmpltn_cmn { 13460 uint8_t status; 13461 uint8_t tid_num; 13462 uint16_t sw_peer_id; 13463 /* RSSI value of last ack packet (units = dB above noise floor) */ 13464 uint32_t ack_rssi; 13465 uint16_t mpdu_tried; 13466 uint16_t mpdu_success; 13467 uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 13468 } __packed; 13469 13470 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 13471 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 13472 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 13473 13474 #define HTT_PPDU_STATS_NON_QOS_TID 16 13475 13476 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 13477 uint32_t ppdu_id; 13478 uint16_t sw_peer_id; 13479 uint16_t reserved0; 13480 uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 13481 uint16_t current_seq; 13482 uint16_t start_seq; 13483 uint32_t success_bytes; 13484 } __packed; 13485 13486 struct htt_ppdu_stats_usr_cmn_array { 13487 struct htt_tlv tlv_hdr; 13488 uint32_t num_ppdu_stats; 13489 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 13490 * elements. 13491 * tx_ppdu_stats_info is variable length, with length = 13492 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 13493 */ 13494 struct htt_tx_ppdu_stats_info tx_ppdu_info[]; 13495 } __packed; 13496 13497 struct htt_ppdu_user_stats { 13498 uint16_t peer_id; 13499 uint32_t tlv_flags; 13500 bool is_valid_peer_id; 13501 struct htt_ppdu_stats_user_rate rate; 13502 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 13503 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 13504 }; 13505 13506 #define HTT_PPDU_STATS_MAX_USERS 8 13507 #define HTT_PPDU_DESC_MAX_DEPTH 16 13508 13509 struct htt_ppdu_stats { 13510 struct htt_ppdu_stats_common common; 13511 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 13512 }; 13513 13514 struct htt_ppdu_stats_info { 13515 uint32_t ppdu_id; 13516 struct htt_ppdu_stats ppdu_stats; 13517 #if 0 13518 struct list_head list; 13519 #endif 13520 }; 13521 13522 /* @brief target -> host packet log message 13523 * 13524 * @details 13525 * The following field definitions describe the format of the packet log 13526 * message sent from the target to the host. 13527 * The message consists of a 4-octet header,followed by a variable number 13528 * of 32-bit character values. 13529 * 13530 * |31 16|15 12|11 10|9 8|7 0| 13531 * |------------------------------------------------------------------| 13532 * | payload_size | rsvd |pdev_id|mac_id| msg type | 13533 * |------------------------------------------------------------------| 13534 * | payload | 13535 * |------------------------------------------------------------------| 13536 * - MSG_TYPE 13537 * Bits 7:0 13538 * Purpose: identifies this as a pktlog message 13539 * Value: HTT_T2H_MSG_TYPE_PKTLOG 13540 * - mac_id 13541 * Bits 9:8 13542 * Purpose: identifies which MAC/PHY instance generated this pktlog info 13543 * Value: 0-3 13544 * - pdev_id 13545 * Bits 11:10 13546 * Purpose: pdev_id 13547 * Value: 0-3 13548 * 0 (for rings at SOC level), 13549 * 1/2/3 PDEV -> 0/1/2 13550 * - payload_size 13551 * Bits 31:16 13552 * Purpose: explicitly specify the payload size 13553 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 13554 */ 13555 struct htt_pktlog_msg { 13556 uint32_t hdr; 13557 uint8_t payload[]; 13558 }; 13559 13560 /* @brief host -> target FW extended statistics retrieve 13561 * 13562 * @details 13563 * The following field definitions describe the format of the HTT host 13564 * to target FW extended stats retrieve message. 13565 * The message specifies the type of stats the host wants to retrieve. 13566 * 13567 * |31 24|23 16|15 8|7 0| 13568 * |-----------------------------------------------------------| 13569 * | reserved | stats type | pdev_mask | msg type | 13570 * |-----------------------------------------------------------| 13571 * | config param [0] | 13572 * |-----------------------------------------------------------| 13573 * | config param [1] | 13574 * |-----------------------------------------------------------| 13575 * | config param [2] | 13576 * |-----------------------------------------------------------| 13577 * | config param [3] | 13578 * |-----------------------------------------------------------| 13579 * | reserved | 13580 * |-----------------------------------------------------------| 13581 * | cookie LSBs | 13582 * |-----------------------------------------------------------| 13583 * | cookie MSBs | 13584 * |-----------------------------------------------------------| 13585 * Header fields: 13586 * - MSG_TYPE 13587 * Bits 7:0 13588 * Purpose: identifies this is a extended stats upload request message 13589 * Value: 0x10 13590 * - PDEV_MASK 13591 * Bits 8:15 13592 * Purpose: identifies the mask of PDEVs to retrieve stats from 13593 * Value: This is a overloaded field, refer to usage and interpretation of 13594 * PDEV in interface document. 13595 * Bit 8 : Reserved for SOC stats 13596 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 13597 * Indicates MACID_MASK in DBS 13598 * - STATS_TYPE 13599 * Bits 23:16 13600 * Purpose: identifies which FW statistics to upload 13601 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 13602 * - Reserved 13603 * Bits 31:24 13604 * - CONFIG_PARAM [0] 13605 * Bits 31:0 13606 * Purpose: give an opaque configuration value to the specified stats type 13607 * Value: stats-type specific configuration value 13608 * Refer to htt_stats.h for interpretation for each stats sub_type 13609 * - CONFIG_PARAM [1] 13610 * Bits 31:0 13611 * Purpose: give an opaque configuration value to the specified stats type 13612 * Value: stats-type specific configuration value 13613 * Refer to htt_stats.h for interpretation for each stats sub_type 13614 * - CONFIG_PARAM [2] 13615 * Bits 31:0 13616 * Purpose: give an opaque configuration value to the specified stats type 13617 * Value: stats-type specific configuration value 13618 * Refer to htt_stats.h for interpretation for each stats sub_type 13619 * - CONFIG_PARAM [3] 13620 * Bits 31:0 13621 * Purpose: give an opaque configuration value to the specified stats type 13622 * Value: stats-type specific configuration value 13623 * Refer to htt_stats.h for interpretation for each stats sub_type 13624 * - Reserved [31:0] for future use. 13625 * - COOKIE_LSBS 13626 * Bits 31:0 13627 * Purpose: Provide a mechanism to match a target->host stats confirmation 13628 * message with its preceding host->target stats request message. 13629 * Value: LSBs of the opaque cookie specified by the host-side requestor 13630 * - COOKIE_MSBS 13631 * Bits 31:0 13632 * Purpose: Provide a mechanism to match a target->host stats confirmation 13633 * message with its preceding host->target stats request message. 13634 * Value: MSBs of the opaque cookie specified by the host-side requestor 13635 */ 13636 13637 struct htt_ext_stats_cfg_hdr { 13638 uint8_t msg_type; 13639 uint8_t pdev_mask; 13640 uint8_t stats_type; 13641 uint8_t reserved; 13642 } __packed; 13643 13644 struct htt_ext_stats_cfg_cmd { 13645 struct htt_ext_stats_cfg_hdr hdr; 13646 uint32_t cfg_param0; 13647 uint32_t cfg_param1; 13648 uint32_t cfg_param2; 13649 uint32_t cfg_param3; 13650 uint32_t reserved; 13651 uint32_t cookie_lsb; 13652 uint32_t cookie_msb; 13653 } __packed; 13654 13655 /* htt stats config default params */ 13656 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 13657 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 13658 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 13659 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 13660 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 13661 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 13662 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 13663 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 13664 13665 /* HTT_DBG_EXT_STATS_PEER_INFO 13666 * PARAMS: 13667 * @config_param0: 13668 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 13669 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 13670 * [Bit31 : Bit16] sw_peer_id 13671 * @config_param1: 13672 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 13673 * 0 bit htt_peer_stats_cmn_tlv 13674 * 1 bit htt_peer_details_tlv 13675 * 2 bit htt_tx_peer_rate_stats_tlv 13676 * 3 bit htt_rx_peer_rate_stats_tlv 13677 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 13678 * 5 bit htt_rx_tid_stats_tlv 13679 * 6 bit htt_msdu_flow_stats_tlv 13680 * @config_param2: [Bit31 : Bit0] mac_addr31to0 13681 * @config_param3: [Bit15 : Bit0] mac_addr47to32 13682 * [Bit31 : Bit16] reserved 13683 */ 13684 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 13685 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 13686 13687 /* Used to set different configs to the specified stats type.*/ 13688 struct htt_ext_stats_cfg_params { 13689 uint32_t cfg0; 13690 uint32_t cfg1; 13691 uint32_t cfg2; 13692 uint32_t cfg3; 13693 }; 13694 13695 /* @brief target -> host extended statistics upload 13696 * 13697 * @details 13698 * The following field definitions describe the format of the HTT target 13699 * to host stats upload confirmation message. 13700 * The message contains a cookie echoed from the HTT host->target stats 13701 * upload request, which identifies which request the confirmation is 13702 * for, and a single stats can span over multiple HTT stats indication 13703 * due to the HTT message size limitation so every HTT ext stats indication 13704 * will have tag-length-value stats information elements. 13705 * The tag-length header for each HTT stats IND message also includes a 13706 * status field, to indicate whether the request for the stat type in 13707 * question was fully met, partially met, unable to be met, or invalid 13708 * (if the stat type in question is disabled in the target). 13709 * A Done bit 1's indicate the end of the of stats info elements. 13710 * 13711 * 13712 * |31 16|15 12|11|10 8|7 5|4 0| 13713 * |--------------------------------------------------------------| 13714 * | reserved | msg type | 13715 * |--------------------------------------------------------------| 13716 * | cookie LSBs | 13717 * |--------------------------------------------------------------| 13718 * | cookie MSBs | 13719 * |--------------------------------------------------------------| 13720 * | stats entry length | rsvd | D| S | stat type | 13721 * |--------------------------------------------------------------| 13722 * | type-specific stats info | 13723 * | (see htt_stats.h) | 13724 * |--------------------------------------------------------------| 13725 * Header fields: 13726 * - MSG_TYPE 13727 * Bits 7:0 13728 * Purpose: Identifies this is a extended statistics upload confirmation 13729 * message. 13730 * Value: 0x1c 13731 * - COOKIE_LSBS 13732 * Bits 31:0 13733 * Purpose: Provide a mechanism to match a target->host stats confirmation 13734 * message with its preceding host->target stats request message. 13735 * Value: LSBs of the opaque cookie specified by the host-side requestor 13736 * - COOKIE_MSBS 13737 * Bits 31:0 13738 * Purpose: Provide a mechanism to match a target->host stats confirmation 13739 * message with its preceding host->target stats request message. 13740 * Value: MSBs of the opaque cookie specified by the host-side requestor 13741 * 13742 * Stats Information Element tag-length header fields: 13743 * - STAT_TYPE 13744 * Bits 7:0 13745 * Purpose: identifies the type of statistics info held in the 13746 * following information element 13747 * Value: htt_dbg_ext_stats_type 13748 * - STATUS 13749 * Bits 10:8 13750 * Purpose: indicate whether the requested stats are present 13751 * Value: htt_dbg_ext_stats_status 13752 * - DONE 13753 * Bits 11 13754 * Purpose: 13755 * Indicates the completion of the stats entry, this will be the last 13756 * stats conf HTT segment for the requested stats type. 13757 * Value: 13758 * 0 -> the stats retrieval is ongoing 13759 * 1 -> the stats retrieval is complete 13760 * - LENGTH 13761 * Bits 31:16 13762 * Purpose: indicate the stats information size 13763 * Value: This field specifies the number of bytes of stats information 13764 * that follows the element tag-length header. 13765 * It is expected but not required that this length is a multiple of 13766 * 4 bytes. 13767 */ 13768 13769 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 13770 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 13771 13772 struct ath12k_htt_extd_stats_msg { 13773 uint32_t info0; 13774 uint64_t cookie; 13775 uint32_t info1; 13776 uint8_t data[]; 13777 } __packed; 13778 13779 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 13780 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 13781 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 13782 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 13783 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 13784 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 13785 13786 /* 13787 * hal_rx.h 13788 */ 13789 13790 #define HAL_RX_MPDU_ERR_FCS BIT(0) 13791 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1) 13792 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2) 13793 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3) 13794 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4) 13795 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5) 13796 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) 13797 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) 13798