1 /* $OpenBSD: amlmmc.c,v 1.12 2022/01/09 05:42:37 jsg Exp $ */
2 /*
3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21 #include <sys/malloc.h>
22
23 #include <machine/intr.h>
24 #include <machine/bus.h>
25 #include <machine/fdt.h>
26
27 #include <dev/ofw/openfirm.h>
28 #include <dev/ofw/ofw_clock.h>
29 #include <dev/ofw/ofw_gpio.h>
30 #include <dev/ofw/ofw_pinctrl.h>
31 #include <dev/ofw/ofw_regulator.h>
32 #include <dev/ofw/fdt.h>
33
34 #include <dev/sdmmc/sdmmcvar.h>
35
36 #define SD_EMMC_CLOCK 0x0000
37 #define SD_EMMC_CLOCK_ALWAYS_ON (1 << 28)
38 #define SD_EMMC_CLOCK_RX_PHASE_0 (0 << 12)
39 #define SD_EMMC_CLOCK_RX_PHASE_90 (1 << 12)
40 #define SD_EMMC_CLOCK_RX_PHASE_180 (2 << 12)
41 #define SD_EMMC_CLOCK_RX_PHASE_270 (3 << 12)
42 #define SD_EMMC_CLOCK_TX_PHASE_0 (0 << 10)
43 #define SD_EMMC_CLOCK_TX_PHASE_90 (1 << 10)
44 #define SD_EMMC_CLOCK_TX_PHASE_180 (2 << 10)
45 #define SD_EMMC_CLOCK_TX_PHASE_270 (3 << 10)
46 #define SD_EMMC_CLOCK_CO_PHASE_0 (0 << 8)
47 #define SD_EMMC_CLOCK_CO_PHASE_90 (1 << 8)
48 #define SD_EMMC_CLOCK_CO_PHASE_180 (2 << 8)
49 #define SD_EMMC_CLOCK_CO_PHASE_270 (3 << 8)
50 #define SD_EMMC_CLOCK_CLK_SRC_24M (0 << 6)
51 #define SD_EMMC_CLOCK_CLK_SRC_FCLK (1 << 6)
52 #define SD_EMMC_CLOCK_DIV_MAX 63
53 #define SD_EMMC_DELAY1 0x0004
54 #define SD_EMMC_DELAY2 0x0008
55 #define SD_EMMC_ADJUST 0x000c
56 #define SD_EMMC_ADJUST_ADJ_FIXED (1 << 13)
57 #define SD_EMMC_ADJUST_ADJ_DELAY_MASK (0x3f << 16)
58 #define SD_EMMC_ADJUST_ADJ_DELAY_SHIFT 16
59 #define SD_EMMC_START 0x0040
60 #define SD_EMMC_START_START (1 << 1)
61 #define SD_EMMC_START_STOP (0 << 1)
62 #define SD_EMMC_CFG 0x0044
63 #define SD_EMMC_CFG_ERR_ABORT (1 << 27)
64 #define SD_EMMC_CFG_AUTO_CLK (1 << 23)
65 #define SD_EMMC_CFG_STOP_CLOCK (1 << 22)
66 #define SD_EMMC_CFG_SDCLK_ALWAYS_ON (1 << 18)
67 #define SD_EMMC_CFG_RC_CC_MASK (0xf << 12)
68 #define SD_EMMC_CFG_RC_CC_16 (0x4 << 12)
69 #define SD_EMMC_CFG_RESP_TIMEOUT_MASK (0xf << 8)
70 #define SD_EMMC_CFG_RESP_TIMEOUT_256 (0x8 << 8)
71 #define SD_EMMC_CFG_BL_LEN_MASK (0xf << 4)
72 #define SD_EMMC_CFG_BL_LEN_SHIFT 4
73 #define SD_EMMC_CFG_BL_LEN_512 (0x9 << 4)
74 #define SD_EMMC_CFG_DDR (1 << 2)
75 #define SD_EMMC_CFG_BUS_WIDTH_MASK (0x3 << 0)
76 #define SD_EMMC_CFG_BUS_WIDTH_1 (0x0 << 0)
77 #define SD_EMMC_CFG_BUS_WIDTH_4 (0x1 << 0)
78 #define SD_EMMC_CFG_BUS_WIDTH_8 (0x2 << 0)
79 #define SD_EMMC_STATUS 0x0048
80 #define SD_EMMC_STATUS_END_OF_CHAIN (1 << 13)
81 #define SD_EMMC_STATUS_DESC_TIMEOUT (1 << 12)
82 #define SD_EMMC_STATUS_RESP_TIMEOUT (1 << 11)
83 #define SD_EMMC_STATUS_MASK 0x00003fff
84 #define SD_EMMC_STATUS_ERR_MASK 0x000007ff
85 #define SD_EMMC_IRQ_EN 0x004c
86 #define SD_EMMC_IRQ_EN_MASK SD_EMMC_STATUS_MASK
87 #define SD_EMMC_CMD_CFG 0x0050
88 #define SD_EMMC_CMD_CFG_BLOCK_MODE (1 << 9)
89 #define SD_EMMC_CMD_CFG_R1B (1 << 10)
90 #define SD_EMMC_CMD_CFG_END_OF_CHAIN (1 << 11)
91 #define SD_EMMC_CMD_CFG_TIMEOUT_1024 (10 << 12)
92 #define SD_EMMC_CMD_CFG_TIMEOUT_4096 (12 << 12)
93 #define SD_EMMC_CMD_CFG_NO_RESP (1 << 16)
94 #define SD_EMMC_CMD_CFG_NO_CMD (1 << 17)
95 #define SD_EMMC_CMD_CFG_DATA_IO (1 << 18)
96 #define SD_EMMC_CMD_CFG_DATA_WR (1 << 19)
97 #define SD_EMMC_CMD_CFG_RESP_NOCRC (1 << 20)
98 #define SD_EMMC_CMD_CFG_RESP_128 (1 << 21)
99 #define SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT 24
100 #define SD_EMMC_CMD_CFG_OWNER (1U << 31)
101 #define SD_EMMC_CMD_ARG 0x0054
102 #define SD_EMMC_CMD_DAT 0x0058
103 #define SD_EMMC_CMD_RSP 0x005c
104 #define SD_EMMC_CMD_RSP1 0x0060
105 #define SD_EMMC_CMD_RSP2 0x0064
106 #define SD_EMMC_CMD_RSP3 0x0068
107
108 #define HREAD4(sc, reg) \
109 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
110 #define HWRITE4(sc, reg, val) \
111 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
112 #define HSET4(sc, reg, bits) \
113 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
114 #define HCLR4(sc, reg, bits) \
115 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
116
117 struct amlmmc_desc {
118 uint32_t cmd_cfg;
119 uint32_t cmd_arg;
120 uint32_t data_addr;
121 uint32_t resp_addr;
122 };
123
124 #define AMLMMC_NDESC (PAGE_SIZE / sizeof(struct amlmmc_desc))
125 #define AMLMMC_MAXSEGSZ 0x20000
126
127 struct amlmmc_softc {
128 struct device sc_dev;
129 bus_space_tag_t sc_iot;
130 bus_space_handle_t sc_ioh;
131 bus_dma_tag_t sc_dmat;
132 bus_dmamap_t sc_dmap;
133
134 void *sc_ih;
135 uint32_t sc_status;
136
137 bus_dmamap_t sc_desc_map;
138 bus_dma_segment_t sc_desc_segs[1];
139 int sc_desc_nsegs;
140 caddr_t sc_desc;
141
142 int sc_node;
143 uint32_t sc_clkin0;
144 uint32_t sc_clkin1;
145 uint32_t sc_gpio[4];
146 uint32_t sc_vmmc;
147 uint32_t sc_vqmmc;
148 uint32_t sc_pwrseq;
149 uint32_t sc_vdd;
150 uint32_t sc_ocr;
151
152 int sc_blklen;
153 struct device *sc_sdmmc;
154 };
155
156 int amlmmc_match(struct device *, void *, void *);
157 void amlmmc_attach(struct device *, struct device *, void *);
158
159 const struct cfattach amlmmc_ca = {
160 sizeof (struct amlmmc_softc), amlmmc_match, amlmmc_attach
161 };
162
163 struct cfdriver amlmmc_cd = {
164 NULL, "amlmmc", DV_DULL
165 };
166
167 int amlmmc_alloc_descriptors(struct amlmmc_softc *);
168 void amlmmc_free_descriptors(struct amlmmc_softc *);
169 int amlmmc_intr(void *);
170
171 void amlmmc_pwrseq_reset(uint32_t);
172
173 int amlmmc_host_reset(sdmmc_chipset_handle_t);
174 uint32_t amlmmc_host_ocr(sdmmc_chipset_handle_t);
175 int amlmmc_host_maxblklen(sdmmc_chipset_handle_t);
176 int amlmmc_card_detect(sdmmc_chipset_handle_t);
177 int amlmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
178 int amlmmc_bus_clock(sdmmc_chipset_handle_t, int, int);
179 int amlmmc_bus_width(sdmmc_chipset_handle_t, int);
180 void amlmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
181 int amlmmc_signal_voltage(sdmmc_chipset_handle_t, int);
182 int amlmmc_execute_tuning(sdmmc_chipset_handle_t, int);
183
184 struct sdmmc_chip_functions amlmmc_chip_functions = {
185 .host_reset = amlmmc_host_reset,
186 .host_ocr = amlmmc_host_ocr,
187 .host_maxblklen = amlmmc_host_maxblklen,
188 .card_detect = amlmmc_card_detect,
189 .bus_power = amlmmc_bus_power,
190 .bus_clock = amlmmc_bus_clock,
191 .bus_width = amlmmc_bus_width,
192 .exec_command = amlmmc_exec_command,
193 .signal_voltage = amlmmc_signal_voltage,
194 .execute_tuning = amlmmc_execute_tuning,
195 };
196
197 int
amlmmc_match(struct device * parent,void * match,void * aux)198 amlmmc_match(struct device *parent, void *match, void *aux)
199 {
200 struct fdt_attach_args *faa = aux;
201
202 return (OF_is_compatible(faa->fa_node, "amlogic,meson-axg-mmc") ||
203 OF_is_compatible(faa->fa_node, "amlogic,meson-sm1-mmc"));
204 }
205
206 void
amlmmc_attach(struct device * parent,struct device * self,void * aux)207 amlmmc_attach(struct device *parent, struct device *self, void *aux)
208 {
209 struct amlmmc_softc *sc = (struct amlmmc_softc *)self;
210 struct fdt_attach_args *faa = aux;
211 struct sdmmcbus_attach_args saa;
212 uint32_t cfg, width;
213 int error;
214
215 if (faa->fa_nreg < 1) {
216 printf(": no registers\n");
217 return;
218 }
219
220 sc->sc_iot = faa->fa_iot;
221 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
222 faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
223 printf(": can't map registers\n");
224 return;
225 }
226
227 sc->sc_dmat = faa->fa_dmat;
228 error = amlmmc_alloc_descriptors(sc);
229 if (error) {
230 printf(": can't allocate descriptors\n");
231 goto unmap;
232 }
233 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, AMLMMC_NDESC,
234 AMLMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap);
235 if (error) {
236 printf(": can't create DMA map\n");
237 goto free;
238 }
239
240 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO,
241 amlmmc_intr, sc, sc->sc_dev.dv_xname);
242 if (sc->sc_ih == NULL) {
243 printf(": can't establish interrupt\n");
244 goto destroy;
245 }
246
247 sc->sc_node = faa->fa_node;
248 printf("\n");
249
250 pinctrl_byname(faa->fa_node, "default");
251
252 clock_enable_all(faa->fa_node);
253 reset_deassert_all(faa->fa_node);
254
255 sc->sc_clkin0 = clock_get_frequency(faa->fa_node, "clkin0");
256 sc->sc_clkin1 = clock_get_frequency(faa->fa_node, "clkin1");
257
258 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio,
259 sizeof(sc->sc_gpio));
260 if (sc->sc_gpio[0])
261 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT);
262
263 sc->sc_vmmc = OF_getpropint(sc->sc_node, "vmmc-supply", 0);
264 sc->sc_vqmmc = OF_getpropint(sc->sc_node, "vqmmc-supply", 0);
265 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0);
266
267 /* XXX Pretend we only support 3.3V for now. */
268 sc->sc_ocr = MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
269
270 /* Initialize timings and block size. */
271 cfg = SD_EMMC_CFG_ERR_ABORT;
272 cfg |= SD_EMMC_CFG_RC_CC_16;
273 cfg |= SD_EMMC_CFG_RESP_TIMEOUT_256;
274 cfg |= SD_EMMC_CFG_BL_LEN_512;
275 HWRITE4(sc, SD_EMMC_CFG, cfg);
276
277 /* Clear status bits & enable interrupts. */
278 HWRITE4(sc, SD_EMMC_STATUS, SD_EMMC_STATUS_MASK);
279 HWRITE4(sc, SD_EMMC_IRQ_EN, SD_EMMC_IRQ_EN_MASK);
280
281 /* Reset eMMC. */
282 if (sc->sc_pwrseq)
283 amlmmc_pwrseq_reset(sc->sc_pwrseq);
284
285 memset(&saa, 0, sizeof(saa));
286 saa.saa_busname = "sdmmc";
287 saa.sct = &amlmmc_chip_functions;
288 saa.sch = sc;
289 saa.dmat = sc->sc_dmat;
290 saa.dmap = sc->sc_dmap;
291 saa.caps = SMC_CAPS_DMA;
292 saa.flags = SMF_STOP_AFTER_MULTIPLE;
293
294 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0)
295 saa.caps |= SMC_CAPS_MMC_HIGHSPEED;
296 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0)
297 saa.caps |= SMC_CAPS_SD_HIGHSPEED;
298 if (OF_getproplen(sc->sc_node, "mmc-ddr-1_8v") == 0)
299 saa.caps |= SMC_CAPS_MMC_DDR52;
300 if (OF_getproplen(sc->sc_node, "mmc-hs200-1_8v") == 0)
301 saa.caps |= SMC_CAPS_MMC_HS200;
302 if (OF_getproplen(sc->sc_node, "sd-uhs-sdr50") == 0)
303 saa.caps |= SMC_CAPS_UHS_SDR50;
304 #ifdef notyet
305 if (OF_getproplen(sc->sc_node, "sd-uhs-sdr104") == 0)
306 saa.caps |= SMC_CAPS_UHS_SDR104;
307 #endif
308
309 if (saa.caps & SMC_CAPS_UHS_MASK)
310 sc->sc_ocr |= MMC_OCR_S18A;
311
312 width = OF_getpropint(faa->fa_node, "bus-width", 1);
313 if (width >= 8)
314 saa.caps |= SMC_CAPS_8BIT_MODE;
315 if (width >= 4)
316 saa.caps |= SMC_CAPS_4BIT_MODE;
317
318 sc->sc_sdmmc = config_found(self, &saa, NULL);
319 return;
320
321 destroy:
322 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap);
323 free:
324 amlmmc_free_descriptors(sc);
325 unmap:
326 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size);
327 }
328
329 int
amlmmc_alloc_descriptors(struct amlmmc_softc * sc)330 amlmmc_alloc_descriptors(struct amlmmc_softc *sc)
331 {
332 int error, rseg;
333
334 /* Allocate descriptor memory */
335 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE,
336 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg,
337 BUS_DMA_WAITOK | BUS_DMA_ZERO);
338 if (error)
339 return error;
340 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg,
341 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
342 if (error) {
343 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg);
344 return error;
345 }
346 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,
347 0, BUS_DMA_WAITOK, &sc->sc_desc_map);
348 if (error) {
349 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE);
350 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg);
351 return error;
352 }
353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map,
354 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE);
355 if (error) {
356 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map);
357 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE);
358 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg);
359 return error;
360 }
361
362 sc->sc_desc_nsegs = rseg;
363 return 0;
364 }
365
366 void
amlmmc_free_descriptors(struct amlmmc_softc * sc)367 amlmmc_free_descriptors(struct amlmmc_softc *sc)
368 {
369 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_map);
370 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map);
371 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE);
372 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, sc->sc_desc_nsegs);
373 }
374
375 int
amlmmc_intr(void * arg)376 amlmmc_intr(void *arg)
377 {
378 struct amlmmc_softc *sc = arg;
379 uint32_t status;
380
381 status = HREAD4(sc, SD_EMMC_STATUS);
382 if ((status & SD_EMMC_STATUS_MASK) == 0)
383 return 0;
384
385 HWRITE4(sc, SD_EMMC_STATUS, status);
386 sc->sc_status = status & SD_EMMC_STATUS_MASK;
387 wakeup(sc);
388 return 1;
389 }
390
391 void
amlmmc_set_blklen(struct amlmmc_softc * sc,int blklen)392 amlmmc_set_blklen(struct amlmmc_softc *sc, int blklen)
393 {
394 uint32_t cfg;
395
396 if (blklen == sc->sc_blklen)
397 return;
398
399 cfg = HREAD4(sc, SD_EMMC_CFG);
400 cfg &= ~SD_EMMC_CFG_BL_LEN_MASK;
401 cfg |= (fls(blklen) - 1) << SD_EMMC_CFG_BL_LEN_SHIFT;
402 HWRITE4(sc, SD_EMMC_CFG, cfg);
403 sc->sc_blklen = blklen;
404 }
405
406 void
amlmmc_pwrseq_reset(uint32_t phandle)407 amlmmc_pwrseq_reset(uint32_t phandle)
408 {
409 uint32_t *gpios, *gpio;
410 int node;
411 int len;
412
413 node = OF_getnodebyphandle(phandle);
414 if (node == 0)
415 return;
416
417 if (!OF_is_compatible(node, "mmc-pwrseq-emmc"))
418 return;
419
420 len = OF_getproplen(node, "reset-gpios");
421 if (len <= 0)
422 return;
423
424 gpios = malloc(len, M_TEMP, M_WAITOK);
425 OF_getpropintarray(node, "reset-gpios", gpios, len);
426
427 gpio = gpios;
428 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {
429 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT);
430 gpio_controller_set_pin(gpio, 1);
431 delay(1);
432 gpio_controller_set_pin(gpio, 0);
433 delay(200);
434 gpio = gpio_controller_next_pin(gpio);
435 }
436
437 free(gpios, M_TEMP, len);
438 }
439
440 int
amlmmc_host_reset(sdmmc_chipset_handle_t sch)441 amlmmc_host_reset(sdmmc_chipset_handle_t sch)
442 {
443 printf("%s\n", __func__);
444 return 0;
445 }
446
447 uint32_t
amlmmc_host_ocr(sdmmc_chipset_handle_t sch)448 amlmmc_host_ocr(sdmmc_chipset_handle_t sch)
449 {
450 struct amlmmc_softc *sc = sch;
451 return sc->sc_ocr;
452 }
453
454 int
amlmmc_host_maxblklen(sdmmc_chipset_handle_t sch)455 amlmmc_host_maxblklen(sdmmc_chipset_handle_t sch)
456 {
457 return 512;
458 }
459
460 int
amlmmc_card_detect(sdmmc_chipset_handle_t sch)461 amlmmc_card_detect(sdmmc_chipset_handle_t sch)
462 {
463 struct amlmmc_softc *sc = sch;
464
465 if (OF_getproplen(sc->sc_node, "non-removable") == 0)
466 return 1;
467
468 if (sc->sc_gpio[0]) {
469 int inverted, val;
470
471 val = gpio_controller_get_pin(sc->sc_gpio);
472
473 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0);
474 return inverted ? !val : val;
475 }
476
477 return 1;
478 }
479
480 int
amlmmc_bus_power(sdmmc_chipset_handle_t sch,uint32_t ocr)481 amlmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
482 {
483 struct amlmmc_softc *sc = sch;
484 uint32_t vdd = 0;
485
486 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V))
487 vdd = 3300000;
488
489 /* enable mmc power */
490 if (sc->sc_vmmc && vdd > 0)
491 regulator_enable(sc->sc_vmmc);
492
493 if (sc->sc_vqmmc && vdd > 0)
494 regulator_enable(sc->sc_vqmmc);
495
496 delay(10000);
497
498 sc->sc_vdd = vdd;
499 return 0;
500 }
501
502 int
amlmmc_bus_clock(sdmmc_chipset_handle_t sch,int freq,int timing)503 amlmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)
504 {
505 struct amlmmc_softc *sc = sch;
506 uint32_t div, clock;
507
508 /* XXX The ODROID-N2 eMMC doesn't work properly above 150 MHz. */
509 if (freq > 150000)
510 freq = 150000;
511
512 pinctrl_byname(sc->sc_node, "clk-gate");
513
514 if (freq == 0)
515 return 0;
516
517 /* Convert clock frequency from kHz to Hz. */
518 freq = freq * 1000;
519
520 /* Double the clock rate for DDR modes. */
521 if (timing == SDMMC_TIMING_MMC_DDR52)
522 freq = freq * 2;
523
524 if (freq < (sc->sc_clkin1 / SD_EMMC_CLOCK_DIV_MAX)) {
525 div = (sc->sc_clkin0 + freq - 1) / freq;
526 clock = SD_EMMC_CLOCK_CLK_SRC_24M | div;
527 } else {
528 div = (sc->sc_clkin1 + freq - 1) / freq;
529 clock = SD_EMMC_CLOCK_CLK_SRC_FCLK | div;
530 }
531 if (div > SD_EMMC_CLOCK_DIV_MAX)
532 return EINVAL;
533
534 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK);
535
536 if (timing == SDMMC_TIMING_MMC_DDR52)
537 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR);
538 else
539 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR);
540
541 clock |= SD_EMMC_CLOCK_ALWAYS_ON;
542 clock |= SD_EMMC_CLOCK_CO_PHASE_180;
543 clock |= SD_EMMC_CLOCK_TX_PHASE_0;
544 clock |= SD_EMMC_CLOCK_RX_PHASE_0;
545 HWRITE4(sc, SD_EMMC_CLOCK, clock);
546
547 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK);
548
549 pinctrl_byname(sc->sc_node, "default");
550
551 return 0;
552 }
553
554 int
amlmmc_bus_width(sdmmc_chipset_handle_t sch,int width)555 amlmmc_bus_width(sdmmc_chipset_handle_t sch, int width)
556 {
557 struct amlmmc_softc *sc = sch;
558 uint32_t cfg;
559
560 cfg = HREAD4(sc, SD_EMMC_CFG);
561 cfg &= ~SD_EMMC_CFG_BUS_WIDTH_MASK;
562 switch (width) {
563 case 1:
564 cfg |= SD_EMMC_CFG_BUS_WIDTH_1;
565 break;
566 case 4:
567 cfg |= SD_EMMC_CFG_BUS_WIDTH_4;
568 break;
569 case 8:
570 cfg |= SD_EMMC_CFG_BUS_WIDTH_8;
571 break;
572 default:
573 return EINVAL;
574 }
575 HWRITE4(sc, SD_EMMC_CFG, cfg);
576
577 return 0;
578 }
579
580 void
amlmmc_exec_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)581 amlmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
582 {
583 struct amlmmc_softc *sc = sch;
584 uint32_t cmd_cfg, status;
585 uint32_t data_addr = 0;
586 int s;
587
588 KASSERT(sc->sc_status == 0);
589
590 /* Setup descriptor flags. */
591 cmd_cfg = cmd->c_opcode << SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT;
592 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
593 cmd_cfg |= SD_EMMC_CMD_CFG_NO_RESP;
594 if (ISSET(cmd->c_flags, SCF_RSP_136))
595 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_128;
596 if (ISSET(cmd->c_flags, SCF_RSP_BSY))
597 cmd_cfg |= SD_EMMC_CMD_CFG_R1B;
598 if (!ISSET(cmd->c_flags, SCF_RSP_CRC))
599 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_NOCRC;
600 if (cmd->c_datalen > 0) {
601 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_IO;
602 if (cmd->c_datalen >= cmd->c_blklen)
603 cmd_cfg |= SD_EMMC_CMD_CFG_BLOCK_MODE;
604 if (!ISSET(cmd->c_flags, SCF_CMD_READ))
605 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_WR;
606 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_4096;
607 } else {
608 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_1024;
609 }
610 cmd_cfg |= SD_EMMC_CMD_CFG_OWNER;
611
612 /* If we have multiple DMA segments we need to use descriptors. */
613 if (cmd->c_datalen > 0 &&
614 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) {
615 struct amlmmc_desc *desc = (struct amlmmc_desc *)sc->sc_desc;
616 int seg;
617
618 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
619 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr;
620 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len;
621
622 if (seg == cmd->c_dmamap->dm_nsegs - 1)
623 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN;
624
625 KASSERT((addr & 0x7) == 0);
626 desc[seg].cmd_cfg = cmd_cfg | (len / cmd->c_blklen);
627 desc[seg].cmd_arg = cmd->c_arg;
628 desc[seg].data_addr = addr;
629 desc[seg].resp_addr = 0;
630 cmd_cfg |= SD_EMMC_CMD_CFG_NO_CMD;
631 }
632
633 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
634 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc),
635 BUS_DMASYNC_PREWRITE);
636 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_START |
637 sc->sc_desc_map->dm_segs[0].ds_addr);
638 goto wait;
639 }
640
641 /* Bounce if we don't have a DMA map. */
642 if (cmd->c_datalen > 0 && !cmd->c_dmamap) {
643 /* Abuse DMA descriptor memory as bounce buffer. */
644 KASSERT(cmd->c_datalen <= PAGE_SIZE);
645 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
646 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
647 cmd->c_datalen, BUS_DMASYNC_PREREAD);
648 } else {
649 memcpy(sc->sc_desc, cmd->c_data, cmd->c_datalen);
650 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
651 cmd->c_datalen, BUS_DMASYNC_PREWRITE);
652 }
653 }
654
655 if (cmd->c_datalen > 0) {
656 if (cmd->c_datalen >= cmd->c_blklen) {
657 amlmmc_set_blklen(sc, cmd->c_blklen);
658 cmd_cfg |= cmd->c_datalen / cmd->c_blklen;
659 } else {
660 cmd_cfg |= cmd->c_datalen;
661 }
662
663 if (cmd->c_dmamap)
664 data_addr = cmd->c_dmamap->dm_segs[0].ds_addr;
665 else
666 data_addr = sc->sc_desc_map->dm_segs[0].ds_addr;
667 }
668
669 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN;
670
671 KASSERT((data_addr & 0x7) == 0);
672 HWRITE4(sc, SD_EMMC_CMD_CFG, cmd_cfg);
673 HWRITE4(sc, SD_EMMC_CMD_DAT, data_addr);
674 HWRITE4(sc, SD_EMMC_CMD_RSP, 0);
675 bus_space_barrier(sc->sc_iot, sc->sc_ioh, SD_EMMC_CMD_CFG,
676 SD_EMMC_CMD_RSP1 - SD_EMMC_CMD_CFG, BUS_SPACE_BARRIER_WRITE);
677 HWRITE4(sc, SD_EMMC_CMD_ARG, cmd->c_arg);
678
679 wait:
680 s = splbio();
681 while (sc->sc_status == 0) {
682 if (tsleep_nsec(sc, PWAIT, "amlmmc", 10000000000))
683 break;
684 }
685 status = sc->sc_status;
686 sc->sc_status = 0;
687 splx(s);
688
689 if (!ISSET(status, SD_EMMC_STATUS_END_OF_CHAIN))
690 cmd->c_error = ETIMEDOUT;
691 else if (ISSET(status, SD_EMMC_STATUS_DESC_TIMEOUT))
692 cmd->c_error = ETIMEDOUT;
693 else if (ISSET(status, SD_EMMC_STATUS_RESP_TIMEOUT))
694 cmd->c_error = ETIMEDOUT;
695 else if (ISSET(status, SD_EMMC_STATUS_ERR_MASK))
696 cmd->c_error = EIO;
697
698 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
699 if (ISSET(cmd->c_flags, SCF_RSP_136)) {
700 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP);
701 cmd->c_resp[1] = HREAD4(sc, SD_EMMC_CMD_RSP1);
702 cmd->c_resp[2] = HREAD4(sc, SD_EMMC_CMD_RSP2);
703 cmd->c_resp[3] = HREAD4(sc, SD_EMMC_CMD_RSP3);
704 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) {
705 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
706 (cmd->c_resp[1] << 24);
707 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
708 (cmd->c_resp[2] << 24);
709 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
710 (cmd->c_resp[3] << 24);
711 cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
712 }
713 } else {
714 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP);
715 }
716 }
717
718 /* Unbounce if we don't have a DMA map. */
719 if (cmd->c_datalen > 0 && !cmd->c_dmamap) {
720 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
721 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
722 cmd->c_datalen, BUS_DMASYNC_POSTREAD);
723 memcpy(cmd->c_data, sc->sc_desc, cmd->c_datalen);
724 } else {
725 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
726 cmd->c_datalen, BUS_DMASYNC_POSTWRITE);
727 }
728 }
729
730 /* Cleanup descriptors. */
731 if (cmd->c_datalen > 0 &&
732 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) {
733 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_STOP);
734 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
735 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc),
736 BUS_DMASYNC_POSTWRITE);
737 }
738
739 SET(cmd->c_flags, SCF_ITSDONE);
740 }
741
742 int
amlmmc_signal_voltage(sdmmc_chipset_handle_t sch,int signal_voltage)743 amlmmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage)
744 {
745 struct amlmmc_softc *sc = sch;
746 uint32_t vccq;
747
748 if (sc->sc_vqmmc == 0)
749 return ENODEV;
750
751 switch (signal_voltage) {
752 case SDMMC_SIGNAL_VOLTAGE_180:
753 vccq = 1800000;
754 break;
755 case SDMMC_SIGNAL_VOLTAGE_330:
756 vccq = 3300000;
757 break;
758 default:
759 return EINVAL;
760 }
761
762 if (regulator_get_voltage(sc->sc_vqmmc) == vccq)
763 return 0;
764
765 return regulator_set_voltage(sc->sc_vqmmc, vccq);
766 }
767
768 int
amlmmc_execute_tuning(sdmmc_chipset_handle_t sch,int timing)769 amlmmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)
770 {
771 struct amlmmc_softc *sc = sch;
772 struct sdmmc_command cmd;
773 uint32_t adjust, cfg, div;
774 int opcode, delay;
775 char data[128];
776
777 switch (timing) {
778 case SDMMC_TIMING_MMC_HS200:
779 opcode = MMC_SEND_TUNING_BLOCK_HS200;
780 break;
781 case SDMMC_TIMING_UHS_SDR50:
782 case SDMMC_TIMING_UHS_SDR104:
783 opcode = MMC_SEND_TUNING_BLOCK;
784 break;
785 default:
786 return EINVAL;
787 }
788
789 cfg = HREAD4(sc, SD_EMMC_CFG);
790 div = HREAD4(sc, SD_EMMC_CLOCK) & SD_EMMC_CLOCK_DIV_MAX;
791
792 adjust = HREAD4(sc, SD_EMMC_ADJUST);
793 adjust |= SD_EMMC_ADJUST_ADJ_FIXED;
794 HWRITE4(sc, SD_EMMC_ADJUST, adjust);
795
796 for (delay = 0; delay < div; delay++) {
797 adjust &= ~SD_EMMC_ADJUST_ADJ_DELAY_MASK;
798 adjust |= (delay << SD_EMMC_ADJUST_ADJ_DELAY_SHIFT);
799 HWRITE4(sc, SD_EMMC_ADJUST, adjust);
800
801 memset(&cmd, 0, sizeof(cmd));
802 cmd.c_opcode = opcode;
803 cmd.c_arg = 0;
804 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1;
805 if (cfg & SD_EMMC_CFG_BUS_WIDTH_8) {
806 cmd.c_blklen = cmd.c_datalen = 128;
807 } else {
808 cmd.c_blklen = cmd.c_datalen = 64;
809 }
810 cmd.c_data = data;
811
812 amlmmc_exec_command(sch, &cmd);
813 if (cmd.c_error == 0)
814 return 0;
815 }
816
817 adjust = HREAD4(sc, SD_EMMC_ADJUST);
818 adjust &= ~SD_EMMC_ADJUST_ADJ_FIXED;
819 HWRITE4(sc, SD_EMMC_ADJUST, adjust);
820
821 return EIO;
822 }
823