1 /* $OpenBSD: fpu_implode.c,v 1.11 2024/03/29 21:08:10 miod Exp $ */
2 /* $NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */
3
4 /*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
11 *
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
42 */
43
44 /*
45 * FPU subroutines: `implode' internal format numbers into the machine's
46 * `packed binary' format.
47 */
48
49 #include <sys/types.h>
50 #include <sys/systm.h>
51
52 #include <machine/fsr.h>
53 #include <machine/ieee.h>
54 #include <machine/instr.h>
55 #include <machine/reg.h>
56
57 #include <sparc64/fpu/fpu_arith.h>
58 #include <sparc64/fpu/fpu_emu.h>
59 #include <sparc64/fpu/fpu_extern.h>
60
61 static int fpu_round(struct fpemu *, struct fpn *);
62 static int toinf(struct fpemu *, int);
63
64 /*
65 * Round a number (algorithm from Motorola MC68882 manual, modified for
66 * our internal format). Set inexact exception if rounding is required.
67 * Return true iff we rounded up.
68 *
69 * After rounding, we discard the guard and round bits by shifting right
70 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
71 * This saves effort later.
72 *
73 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
74 * responsibility to fix this if necessary.
75 */
76 static int
fpu_round(struct fpemu * fe,struct fpn * fp)77 fpu_round(struct fpemu *fe, struct fpn *fp)
78 {
79 u_int m0, m1, m2, m3;
80 int gr, s;
81
82 m0 = fp->fp_mant[0];
83 m1 = fp->fp_mant[1];
84 m2 = fp->fp_mant[2];
85 m3 = fp->fp_mant[3];
86 gr = m3 & 3;
87 s = fp->fp_sticky;
88
89 /* mant >>= FP_NG */
90 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
91 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
92 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
93 m0 >>= FP_NG;
94
95 if ((gr | s) == 0) /* result is exact: no rounding needed */
96 goto rounddown;
97
98 fe->fe_cx |= FSR_NX; /* inexact */
99
100 /* Go to rounddown to round down; break to round up. */
101 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) {
102
103 case FSR_RD_RN:
104 default:
105 /*
106 * Round only if guard is set (gr & 2). If guard is set,
107 * but round & sticky both clear, then we want to round
108 * but have a tie, so round to even, i.e., add 1 iff odd.
109 */
110 if ((gr & 2) == 0)
111 goto rounddown;
112 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
113 break;
114 goto rounddown;
115
116 case FSR_RD_RZ:
117 /* Round towards zero, i.e., down. */
118 goto rounddown;
119
120 case FSR_RD_RM:
121 /* Round towards -Inf: up if negative, down if positive. */
122 if (fp->fp_sign)
123 break;
124 goto rounddown;
125
126 case FSR_RD_RP:
127 /* Round towards +Inf: up if positive, down otherwise. */
128 if (!fp->fp_sign)
129 break;
130 goto rounddown;
131 }
132
133 /* Bump low bit of mantissa, with carry. */
134 FPU_ADDS(m3, m3, 1);
135 FPU_ADDCS(m2, m2, 0);
136 FPU_ADDCS(m1, m1, 0);
137 FPU_ADDC(m0, m0, 0);
138 fp->fp_mant[0] = m0;
139 fp->fp_mant[1] = m1;
140 fp->fp_mant[2] = m2;
141 fp->fp_mant[3] = m3;
142 return (1);
143
144 rounddown:
145 fp->fp_mant[0] = m0;
146 fp->fp_mant[1] = m1;
147 fp->fp_mant[2] = m2;
148 fp->fp_mant[3] = m3;
149 return (0);
150 }
151
152 /*
153 * For overflow: return true if overflow is to go to +/-Inf, according
154 * to the sign of the overflowing result. If false, overflow is to go
155 * to the largest magnitude value instead.
156 */
157 static int
toinf(struct fpemu * fe,int sign)158 toinf(struct fpemu *fe, int sign)
159 {
160 int inf;
161
162 /* look at rounding direction */
163 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) {
164
165 default:
166 case FSR_RD_RN: /* the nearest value is always Inf */
167 inf = 1;
168 break;
169
170 case FSR_RD_RZ: /* toward 0 => never towards Inf */
171 inf = 0;
172 break;
173
174 case FSR_RD_RP: /* toward +Inf iff positive */
175 inf = sign == 0;
176 break;
177
178 case FSR_RD_RM: /* toward -Inf iff negative */
179 inf = sign;
180 break;
181 }
182 return (inf);
183 }
184
185 /*
186 * fpn -> int (int value returned as return value).
187 *
188 * N.B.: this conversion always rounds towards zero (this is a peculiarity
189 * of the SPARC instruction set).
190 */
191 u_int
fpu_ftoi(struct fpemu * fe,struct fpn * fp)192 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
193 {
194 u_int i;
195 int sign, exp;
196
197 sign = fp->fp_sign;
198 switch (fp->fp_class) {
199
200 case FPC_ZERO:
201 return (0);
202
203 case FPC_NUM:
204 /*
205 * If exp >= 2^32, overflow. Otherwise shift value right
206 * into last mantissa word (this will not exceed 0xffffffff),
207 * shifting any guard and round bits out into the sticky
208 * bit. Then ``round'' towards zero, i.e., just set an
209 * inexact exception if sticky is set (see fpu_round()).
210 * If the result is > 0x80000000, or is positive and equals
211 * 0x80000000, overflow; otherwise the last fraction word
212 * is the result.
213 */
214 if ((exp = fp->fp_exp) >= 32)
215 break;
216 /* NB: the following includes exp < 0 cases */
217 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
218 fe->fe_cx |= FSR_NX;
219 i = fp->fp_mant[3];
220 if (i >= ((u_int)0x80000000 + sign))
221 break;
222 return (sign ? -i : i);
223
224 default: /* Inf, qNaN, sNaN */
225 break;
226 }
227 /* overflow: replace any inexact exception with invalid */
228 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
229 return (0x7fffffff + sign);
230 }
231
232 /*
233 * fpn -> extended int (high bits of int value returned as return value).
234 *
235 * N.B.: this conversion always rounds towards zero (this is a peculiarity
236 * of the SPARC instruction set).
237 */
238 u_int
fpu_ftox(struct fpemu * fe,struct fpn * fp,u_int * res)239 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
240 {
241 u_int64_t i;
242 int sign, exp;
243
244 sign = fp->fp_sign;
245 switch (fp->fp_class) {
246
247 case FPC_ZERO:
248 i = 0;
249 goto out;
250
251 case FPC_NUM:
252 /*
253 * If exp >= 2^64, overflow. Otherwise shift value right
254 * into last mantissa word (this will not exceed 0xffffffffffffffff),
255 * shifting any guard and round bits out into the sticky
256 * bit. Then ``round'' towards zero, i.e., just set an
257 * inexact exception if sticky is set (see fpu_round()).
258 * If the result is > 0x8000000000000000, or is positive and equals
259 * 0x8000000000000000, overflow; otherwise the last fraction word
260 * is the result.
261 */
262 if ((exp = fp->fp_exp) >= 64)
263 break;
264 /* NB: the following includes exp < 0 cases */
265 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
266 fe->fe_cx |= FSR_NX;
267 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
268 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
269 break;
270 if (sign)
271 i = -i;
272 goto out;
273
274 default: /* Inf, qNaN, sNaN */
275 break;
276 }
277 /* overflow: replace any inexact exception with invalid */
278 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
279 i = 0x7fffffffffffffffLL + sign;
280 out:
281 res[1] = i & 0xffffffff;
282 return (i >> 32);
283 }
284
285 /*
286 * fpn -> single (32 bit single returned as return value).
287 * We assume <= 29 bits in a single-precision fraction (1.f part).
288 */
289 u_int
fpu_ftos(struct fpemu * fe,struct fpn * fp)290 fpu_ftos(struct fpemu *fe, struct fpn *fp)
291 {
292 u_int sign = fp->fp_sign << 31;
293 int exp;
294
295 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
296 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
297
298 /* Take care of non-numbers first. */
299 if (ISNAN(fp)) {
300 /*
301 * Preserve upper bits of NaN, per SPARC V8 appendix N.
302 * Note that fp->fp_mant[0] has the quiet bit set,
303 * even if it is classified as a signalling NaN.
304 */
305 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
306 exp = SNG_EXP_INFNAN;
307 goto done;
308 }
309 if (ISINF(fp))
310 return (sign | SNG_EXP(SNG_EXP_INFNAN));
311 if (ISZERO(fp))
312 return (sign);
313
314 /*
315 * Normals (including subnormals). Drop all the fraction bits
316 * (including the explicit ``implied'' 1 bit) down into the
317 * single-precision range. If the number is subnormal, move
318 * the ``implied'' 1 into the explicit range as well, and shift
319 * right to introduce leading zeroes. Rounding then acts
320 * differently for normals and subnormals: the largest subnormal
321 * may round to the smallest normal (1.0 x 2^minexp), or may
322 * remain subnormal. In the latter case, signal an underflow
323 * if the result was inexact or if underflow traps are enabled.
324 *
325 * Rounding a normal, on the other hand, always produces another
326 * normal (although either way the result might be too big for
327 * single precision, and cause an overflow). If rounding a
328 * normal produces 2.0 in the fraction, we need not adjust that
329 * fraction at all, since both 1.0 and 2.0 are zero under the
330 * fraction mask.
331 *
332 * Note that the guard and round bits vanish from the number after
333 * rounding.
334 */
335 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
336 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
337 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
338 if (fpu_round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
339 return (sign | SNG_EXP(1) | 0);
340 if ((fe->fe_cx & FSR_NX) ||
341 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
342 fe->fe_cx |= FSR_UF;
343 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
344 }
345 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
346 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
347 #ifdef DIAGNOSTIC
348 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
349 panic("fpu_ftos");
350 #endif
351 if (fpu_round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
352 exp++;
353 if (exp >= SNG_EXP_INFNAN) {
354 /* overflow to inf or to max single */
355 fe->fe_cx |= FSR_OF | FSR_NX;
356 if (toinf(fe, sign))
357 return (sign | SNG_EXP(SNG_EXP_INFNAN));
358 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
359 }
360 done:
361 /* phew, made it */
362 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
363 }
364
365 /*
366 * fpn -> double (32 bit high-order result returned; 32-bit low order result
367 * left in res[1]). Assumes <= 61 bits in double precision fraction.
368 *
369 * This code mimics fpu_ftos; see it for comments.
370 */
371 u_int
fpu_ftod(struct fpemu * fe,struct fpn * fp,u_int * res)372 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
373 {
374 u_int sign = fp->fp_sign << 31;
375 int exp;
376
377 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
378 #define DBL_MASK (DBL_EXP(1) - 1)
379
380 if (ISNAN(fp)) {
381 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
382 exp = DBL_EXP_INFNAN;
383 goto done;
384 }
385 if (ISINF(fp)) {
386 sign |= DBL_EXP(DBL_EXP_INFNAN);
387 goto zero;
388 }
389 if (ISZERO(fp)) {
390 zero: res[1] = 0;
391 return (sign);
392 }
393
394 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
395 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
396 if (fpu_round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
397 res[1] = 0;
398 return (sign | DBL_EXP(1) | 0);
399 }
400 if ((fe->fe_cx & FSR_NX) ||
401 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
402 fe->fe_cx |= FSR_UF;
403 exp = 0;
404 goto done;
405 }
406 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
407 if (fpu_round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
408 exp++;
409 if (exp >= DBL_EXP_INFNAN) {
410 fe->fe_cx |= FSR_OF | FSR_NX;
411 if (toinf(fe, sign)) {
412 res[1] = 0;
413 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
414 }
415 res[1] = ~0;
416 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
417 }
418 done:
419 res[1] = fp->fp_mant[3];
420 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
421 }
422
423 /*
424 * fpn -> extended (32 bit high-order result returned; low-order fraction
425 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
426 * our internal format *is* extended precision, plus 2 bits for guard/round,
427 * so we can avoid a small bit of work.
428 */
429 u_int
fpu_ftoq(struct fpemu * fe,struct fpn * fp,u_int * res)430 fpu_ftoq(struct fpemu *fe, struct fpn *fp, u_int *res)
431 {
432 u_int sign = fp->fp_sign << 31;
433 int exp;
434
435 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
436 #define EXT_MASK (EXT_EXP(1) - 1)
437
438 if (ISNAN(fp)) {
439 (void) fpu_shr(fp, 2); /* since we are not rounding */
440 exp = EXT_EXP_INFNAN;
441 goto done;
442 }
443 if (ISINF(fp)) {
444 sign |= EXT_EXP(EXT_EXP_INFNAN);
445 goto zero;
446 }
447 if (ISZERO(fp)) {
448 zero: res[1] = res[2] = res[3] = 0;
449 return (sign);
450 }
451
452 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
453 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
454 if (fpu_round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
455 res[1] = res[2] = res[3] = 0;
456 return (sign | EXT_EXP(1) | 0);
457 }
458 if ((fe->fe_cx & FSR_NX) ||
459 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
460 fe->fe_cx |= FSR_UF;
461 exp = 0;
462 goto done;
463 }
464 /* Since internal == extended, no need to shift here. */
465 if (fpu_round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
466 exp++;
467 if (exp >= EXT_EXP_INFNAN) {
468 fe->fe_cx |= FSR_OF | FSR_NX;
469 if (toinf(fe, sign)) {
470 res[1] = res[2] = res[3] = 0;
471 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
472 }
473 res[1] = res[2] = res[3] = ~0;
474 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
475 }
476 done:
477 res[1] = fp->fp_mant[1];
478 res[2] = fp->fp_mant[2];
479 res[3] = fp->fp_mant[3];
480 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
481 }
482
483 /*
484 * Implode an fpn, writing the result into the given space.
485 */
486 void
fpu_implode(struct fpemu * fe,struct fpn * fp,int type,u_int * space)487 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
488 {
489 DPRINTF(FPE_INSN, ("fpu_implode: "));
490 switch (type) {
491
492 case FTYPE_LNG:
493 space[0] = fpu_ftox(fe, fp, space);
494 DPRINTF(FPE_INSN, ("LNG %x %x\n", space[0], space[1]));
495 break;
496
497 case FTYPE_INT:
498 space[0] = fpu_ftoi(fe, fp);
499 DPRINTF(FPE_INSN, ("INT %x\n", space[0]));
500 break;
501
502 case FTYPE_SNG:
503 space[0] = fpu_ftos(fe, fp);
504 DPRINTF(FPE_INSN, ("SNG %x\n", space[0]));
505 break;
506
507 case FTYPE_DBL:
508 space[0] = fpu_ftod(fe, fp, space);
509 DPRINTF(FPE_INSN, ("DBL %x %x\n", space[0], space[1]));
510 break;
511
512 case FTYPE_EXT:
513 /* funky rounding precision options ?? */
514 space[0] = fpu_ftoq(fe, fp, space);
515 DPRINTF(FPE_INSN, ("EXT %x %x %x %x\n", space[0], space[1],
516 space[2], space[3]));
517 break;
518
519 default:
520 panic("fpu_implode");
521 }
522 }
523