xref: /openbsd-src/sys/arch/riscv64/include/bus.h (revision b0d2811898b6af5f105845a12bf9d62865077da0)
1 /*	$OpenBSD: bus.h,v 1.7 2024/11/18 05:32:39 jsg Exp $	*/
2 
3 /*
4  * Copyright (c) 2003-2004 Opsycon AB Sweden.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #ifndef _MACHINE_BUS_H_
28 #define _MACHINE_BUS_H_
29 
30 #ifdef __STDC__
31 #define CAT(a,b)	a##b
32 #define CAT3(a,b,c)	a##b##c
33 #else
34 #define CAT(a,b)	a/**/b
35 #define CAT3(a,b,c)	a/**/b/**/c
36 #endif
37 
38 /*
39  * Bus access types.
40  */
41 struct bus_space;
42 typedef u_long bus_addr_t;
43 typedef u_long bus_size_t;
44 typedef u_long bus_space_handle_t;
45 typedef struct bus_space *bus_space_tag_t;
46 typedef struct bus_space bus_space_t;
47 
48 struct bus_space {
49 	bus_addr_t	bus_base;
50 	void		*bus_private;
51 	u_int8_t	(*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
52 			  bus_size_t);
53 	void		(*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
54 			  bus_size_t, u_int8_t);
55 	u_int16_t	(*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
56 			  bus_size_t);
57 	void		(*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
58 			  bus_size_t, u_int16_t);
59 	u_int32_t	(*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
60 			  bus_size_t);
61 	void		(*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
62 			  bus_size_t, u_int32_t);
63 	u_int64_t	(*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
64 			  bus_size_t);
65 	void		(*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
66 			  bus_size_t, u_int64_t);
67 	void		(*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
68 			  bus_addr_t, u_int8_t *, bus_size_t);
69 	void		(*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
70 			  bus_addr_t, const u_int8_t *, bus_size_t);
71 	void		(*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
72 			  bus_addr_t, u_int8_t *, bus_size_t);
73 	void		(*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
74 			  bus_addr_t, const u_int8_t *, bus_size_t);
75 	void		(*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
76 			  bus_addr_t, u_int8_t *, bus_size_t);
77 	void		(*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
78 			  bus_addr_t, const u_int8_t *, bus_size_t);
79 	int		(*_space_map)(bus_space_tag_t , bus_addr_t,
80 			  bus_size_t, int, bus_space_handle_t *);
81 	void		(*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
82 			  bus_size_t);
83 	int		(*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
84 			  bus_size_t, bus_size_t, bus_space_handle_t *);
85 	void *		(*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
86 	paddr_t		(*_space_mmap)(bus_space_tag_t, bus_addr_t, off_t,
87 			  int, int);
88 };
89 
90 #define	bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
91 #define	bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
92 #define	bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
93 #define	bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
94 
95 #define	bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
96 #define	bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
97 #define	bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
98 #define	bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
99 
100 #define	bus_space_read_raw_2(t, h, o) \
101 	(*(t)->_space_read_2)((t), (h), (o))
102 #define	bus_space_read_raw_4(t, h, o) \
103 	(*(t)->_space_read_4)((t), (h), (o))
104 #define	bus_space_read_raw_8(t, h, o) \
105 	(*(t)->_space_read_8)((t), (h), (o))
106 
107 #define	bus_space_write_raw_2(t, h, o, v) \
108 	(*(t)->_space_write_2)((t), (h), (o), (v))
109 #define	bus_space_write_raw_4(t, h, o, v) \
110 	(*(t)->_space_write_4)((t), (h), (o), (v))
111 #define	bus_space_write_raw_8(t, h, o, v) \
112 	(*(t)->_space_write_8)((t), (h), (o), (v))
113 
114 #define	bus_space_read_raw_multi_2(t, h, a, b, l) \
115 	(*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
116 #define	bus_space_read_raw_multi_4(t, h, a, b, l) \
117 	(*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
118 #define	bus_space_read_raw_multi_8(t, h, a, b, l) \
119 	(*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
120 
121 #define	bus_space_write_raw_multi_2(t, h, a, b, l) \
122 	(*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
123 #define	bus_space_write_raw_multi_4(t, h, a, b, l) \
124 	(*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
125 #define	bus_space_write_raw_multi_8(t, h, a, b, l) \
126 	(*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
127 
128 #define	bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
129 #define	bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
130 #define	bus_space_subregion(t, h, o, s, p) \
131     (*(t)->_space_subregion)((t), (h), (o), (s), (p))
132 
133 #define BUS_SPACE_MAP_CACHEABLE		0x01
134 #define BUS_SPACE_MAP_LINEAR		0x02
135 #define BUS_SPACE_MAP_PREFETCHABLE	0x04
136 
137 extern bus_space_t riscv64_bs_tag;
138 
139 #define	bus_space_vaddr(t, h)	(*(t)->_space_vaddr)((t), (h))
140 #define	bus_space_mmap(t, a, o, p, f) \
141     (*(t)->_space_mmap)((t), (a), (o), (p), (f))
142 
143 /*----------------------------------------------------------------------------*/
144 #define bus_space_read_multi(n,m)					      \
145 static __inline void							      \
146 CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,     \
147      bus_size_t o, CAT3(u_int,m,_t) *x, size_t cnt)			      \
148 {									      \
149 	while (cnt--)							      \
150 		*x++ = CAT(bus_space_read_,n)(bst, bsh, o);		      \
151 }
152 
153 bus_space_read_multi(1,8)
154 bus_space_read_multi(2,16)
155 bus_space_read_multi(4,32)
156 bus_space_read_multi(8,64)
157 
158 /*----------------------------------------------------------------------------*/
159 #define bus_space_read_region(n,m)					      \
160 static __inline void							      \
161 CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,    \
162      bus_addr_t ba, CAT3(u_int,m,_t) *x, size_t cnt)			      \
163 {									      \
164 	while (cnt--) {							      \
165 		*x++ = CAT(bus_space_read_,n)(bst, bsh, ba);		      \
166 		ba += (n);						      \
167 	}								      \
168 }
169 
170 bus_space_read_region(1,8)
171 bus_space_read_region(2,16)
172 bus_space_read_region(4,32)
173 bus_space_read_region(8,64)
174 
175 /*----------------------------------------------------------------------------*/
176 #define bus_space_read_raw_region(n,m)					      \
177 static __inline void							      \
178 CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst,			      \
179      bus_space_handle_t bsh,						      \
180      bus_addr_t ba, u_int8_t *x, size_t cnt)				      \
181 {									      \
182 	cnt >>= ((n) >> 1);						      \
183 	while (cnt--) {							      \
184 		CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n));	      \
185 		ba += (n);						      \
186 		x += (n);						      \
187 	}								      \
188 }
189 
190 bus_space_read_raw_region(2,16)
191 bus_space_read_raw_region(4,32)
192 bus_space_read_raw_region(8,64)
193 
194 /*----------------------------------------------------------------------------*/
195 #define bus_space_write_multi(n,m)					      \
196 static __inline void							      \
197 CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,    \
198      bus_size_t o, const CAT3(u_int,m,_t) *x, size_t cnt)		      \
199 {									      \
200 	while (cnt--)							      \
201 		CAT(bus_space_write_,n)(bst, bsh, o, *x++);		      \
202 }
203 
204 bus_space_write_multi(1,8)
205 bus_space_write_multi(2,16)
206 bus_space_write_multi(4,32)
207 bus_space_write_multi(8,64)
208 
209 /*----------------------------------------------------------------------------*/
210 #define bus_space_write_region(n,m)					      \
211 static __inline void							      \
212 CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,   \
213      bus_addr_t ba, const CAT3(u_int,m,_t) *x, size_t cnt)		      \
214 {									      \
215 	while (cnt--) {							      \
216 		CAT(bus_space_write_,n)(bst, bsh, ba, *x++);		      \
217 		ba += (n);						      \
218 	}								      \
219 }
220 
221 bus_space_write_region(1,8)
222 bus_space_write_region(2,16)
223 bus_space_write_region(4,32)
224 bus_space_write_region(8,64)
225 
226 /*----------------------------------------------------------------------------*/
227 #define bus_space_write_raw_region(n,m)					      \
228 static __inline void							      \
229 CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst,			      \
230      bus_space_handle_t bsh,						      \
231      bus_addr_t ba, const u_int8_t *x, size_t cnt)		              \
232 {									      \
233 	cnt >>= ((n) >> 1);						      \
234 	while (cnt--) {							      \
235 		CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n));      \
236 		ba += (n);						      \
237 		x += (n);						      \
238 	}								      \
239 }
240 
241 bus_space_write_raw_region(2,16)
242 bus_space_write_raw_region(4,32)
243 bus_space_write_raw_region(8,64)
244 
245 /*----------------------------------------------------------------------------*/
246 #define bus_space_set_region(n,m)					      \
247 static __inline void							      \
248 CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,     \
249      bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt)			      \
250 {									      \
251 	while (cnt--) {							      \
252 		CAT(bus_space_write_,n)(bst, bsh, ba, x);		      \
253 		ba += (n);						      \
254 	}								      \
255 }
256 
257 bus_space_set_region(1,8)
258 bus_space_set_region(2,16)
259 bus_space_set_region(4,32)
260 bus_space_set_region(8,64)
261 
262 /*----------------------------------------------------------------------------*/
263 static __inline void
264 bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
265 	bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
266 {
267 	char *s = (char *)(h1 + o1);
268 	char *d = (char *)(h2 + o2);
269 
270 	__asm volatile ("fence w,o" ::: "memory");
271 	while (c--)
272 		*d++ = *s++;
273 	__asm volatile ("fence io,iwr" ::: "memory");
274 }
275 
276 
277 static __inline void
278 bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
279 	bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
280 {
281 	short *s = (short *)(h1 + o1);
282 	short *d = (short *)(h2 + o2);
283 
284 	__asm volatile ("fence w,o" ::: "memory");
285 	while (c--)
286 		*d++ = *s++;
287 	__asm volatile ("fence io,iwr" ::: "memory");
288 }
289 
290 static __inline void
291 bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
292 	bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
293 {
294 	int *s = (int *)(h1 + o1);
295 	int *d = (int *)(h2 + o2);
296 
297 	__asm volatile ("fence w,o" ::: "memory");
298 	while (c--)
299 		*d++ = *s++;
300 	__asm volatile ("fence io,iwr" ::: "memory");
301 }
302 
303 static __inline void
304 bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
305 	bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
306 {
307 	int64_t *s = (int64_t *)(h1 + o1);
308 	int64_t *d = (int64_t *)(h2 + o2);
309 
310 	__asm volatile ("fence w,o" ::: "memory");
311 	while (c--)
312 		*d++ = *s++;
313 	__asm volatile ("fence io,iwr" ::: "memory");
314 }
315 
316 /*----------------------------------------------------------------------------*/
317 /*
318  * Bus read/write barrier methods.
319  *
320  *	void bus_space_barrier(bus_space_tag_t tag,
321  *	    bus_space_handle_t bsh, bus_size_t offset,
322  *	    bus_size_t len, int flags);
323  *
324  */
325 static inline void
326 bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
327     bus_size_t length, int flags)
328 {
329 	__asm__ volatile ("fence iorw,iorw" ::: "memory");
330 }
331 #define BUS_SPACE_BARRIER_READ  0x01		/* force read barrier */
332 #define BUS_SPACE_BARRIER_WRITE 0x02		/* force write barrier */
333 
334 #define	BUS_DMA_WAITOK		0x0000
335 #define	BUS_DMA_NOWAIT		0x0001
336 #define	BUS_DMA_ALLOCNOW	0x0002
337 #define	BUS_DMA_COHERENT	0x0008
338 #define	BUS_DMA_BUS1		0x0010	/* placeholders for bus functions... */
339 #define	BUS_DMA_BUS2		0x0020
340 #define	BUS_DMA_BUS3		0x0040
341 #define	BUS_DMA_BUS4		0x0080
342 #define	BUS_DMA_READ		0x0100	/* mapping is device -> memory only */
343 #define	BUS_DMA_WRITE		0x0200	/* mapping is memory -> device only */
344 #define	BUS_DMA_STREAMING	0x0400	/* hint: sequential, unidirectional */
345 #define	BUS_DMA_ZERO		0x0800	/* zero memory in dmamem_alloc */
346 #define	BUS_DMA_NOCACHE		0x1000
347 #define	BUS_DMA_64BIT		0x2000	/* device handles 64bit dva */
348 
349 /* Forwards needed by prototypes below. */
350 struct mbuf;
351 struct proc;
352 struct uio;
353 
354 #define	BUS_DMASYNC_POSTREAD	0x0001
355 #define BUS_DMASYNC_POSTWRITE	0x0002
356 #define BUS_DMASYNC_PREREAD	0x0004
357 #define BUS_DMASYNC_PREWRITE	0x0008
358 
359 typedef struct machine_bus_dma_tag	*bus_dma_tag_t;
360 typedef struct machine_bus_dmamap	*bus_dmamap_t;
361 
362 /*
363  *	bus_dma_segment_t
364  *
365  *	Describes a single contiguous DMA transaction.  Values
366  *	are suitable for programming into DMA registers.
367  */
368 struct machine_bus_dma_segment {
369 	bus_addr_t	ds_addr;	/* DMA address */
370 	bus_size_t	ds_len;		/* length of transfer */
371 
372 	paddr_t		_ds_paddr;	/* CPU address */
373 	vaddr_t		_ds_vaddr;	/* CPU address */
374 	int		_ds_coherent;	/* Coherently mapped */
375 };
376 typedef struct machine_bus_dma_segment	bus_dma_segment_t;
377 
378 /*
379  *	bus_dma_tag_t
380  *
381  *	A machine-dependent opaque type describing the implementation of
382  *	DMA for a given bus.
383  */
384 
385 struct machine_bus_dma_tag {
386 	void	*_cookie;		/* cookie used in the guts */
387 	int	_flags;			/* misc. flags */
388 
389 	/*
390 	 * DMA mapping methods.
391 	 */
392 	int	(*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
393 		    bus_size_t, bus_size_t, int, bus_dmamap_t *);
394 	void	(*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
395 	int	(*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
396 		    bus_size_t, struct proc *, int);
397 	int	(*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
398 		    struct mbuf *, int);
399 	int	(*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
400 		    struct uio *, int);
401 	int	(*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
402 		    bus_dma_segment_t *, int, bus_size_t, int);
403 	int	(*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
404 		    bus_size_t, struct proc *, int, paddr_t *, int *, int);
405 	void	(*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
406 	void	(*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
407 		    bus_addr_t, bus_size_t, int);
408 
409 	/*
410 	 * DMA memory utility functions.
411 	 */
412 	int	(*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
413 		    bus_size_t, bus_dma_segment_t *, int, int *, int);
414 	void	(*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
415 	int	(*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
416 		    int, size_t, caddr_t *, int);
417 	void	(*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
418 	paddr_t	(*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
419 		    int, off_t, int, int);
420 
421 	/*
422 	 * internal memory address translation information.
423 	 */
424 	bus_addr_t _dma_mask;
425 };
426 
427 #define	bus_dmamap_create(t, s, n, m, b, f, p)			\
428 	(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
429 #define	bus_dmamap_destroy(t, p)				\
430 	(*(t)->_dmamap_destroy)((t), (p))
431 #define	bus_dmamap_load(t, m, b, s, p, f)			\
432 	(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
433 #define	bus_dmamap_load_mbuf(t, m, b, f)			\
434 	(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
435 #define	bus_dmamap_load_uio(t, m, u, f)				\
436 	(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
437 #define	bus_dmamap_load_raw(t, m, sg, n, s, f)			\
438 	(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
439 #define	bus_dmamap_unload(t, p)					\
440 	(*(t)->_dmamap_unload)((t), (p))
441 #define	bus_dmamap_sync(t, p, a, l, o)				\
442 	(void)((t)->_dmamap_sync ?				\
443 	    (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
444 
445 #define	bus_dmamem_alloc(t, s, a, b, sg, n, r, f)		\
446 	(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
447 #define	bus_dmamem_free(t, sg, n)				\
448 	(*(t)->_dmamem_free)((t), (sg), (n))
449 #define	bus_dmamem_map(t, sg, n, s, k, f)			\
450 	(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
451 #define	bus_dmamem_unmap(t, k, s)				\
452 	(*(t)->_dmamem_unmap)((t), (k), (s))
453 #define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
454 	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
455 
456 int	_dmamap_create(bus_dma_tag_t, bus_size_t, int,
457 	    bus_size_t, bus_size_t, int, bus_dmamap_t *);
458 void	_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
459 int	_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
460 	    bus_size_t, struct proc *, int);
461 int	_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
462 int	_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
463 int	_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
464 	    bus_dma_segment_t *, int, bus_size_t, int);
465 int	_dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
466 	    bus_size_t, struct proc *, int, paddr_t *, int *, int);
467 void	_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
468 void	_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
469 	    bus_size_t, int);
470 
471 int	_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
472 	    bus_size_t, bus_dma_segment_t *, int, int *, int);
473 void	_dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
474 int	_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
475 	    int, size_t, caddr_t *, int);
476 void	_dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
477 paddr_t	_dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
478 int	_dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
479 	    bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
480 
481 /*
482  *	bus_dmamap_t
483  *
484  *	Describes a DMA mapping.
485  */
486 struct machine_bus_dmamap {
487 	/*
488 	 * PRIVATE MEMBERS: not for use by machine-independent code.
489 	 */
490 	bus_size_t	_dm_size;	/* largest DMA transfer mappable */
491 	int		_dm_segcnt;	/* number of segs this map can map */
492 	bus_size_t	_dm_maxsegsz;	/* largest possible segment */
493 	bus_size_t	_dm_boundary;	/* don't cross this */
494 	int		_dm_flags;	/* misc. flags */
495 
496 	void		*_dm_cookie;	/* cookie for bus-specific functions */
497 
498 	/*
499 	 * PUBLIC MEMBERS: these are used by machine-independent code.
500 	 */
501 	bus_size_t	dm_mapsize;	/* size of the mapping */
502 	int		dm_nsegs;	/* # valid segments in mapping */
503 	bus_dma_segment_t dm_segs[1];	/* segments; variable length */
504 };
505 
506 int	generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
507 	    bus_space_handle_t *);
508 void	generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
509 int	generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
510 	    bus_size_t, bus_space_handle_t *);
511 void	*generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
512 paddr_t	generic_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
513 uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
514 uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
515 uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
516 uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
517 void	generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
518 	    bus_addr_t, uint8_t *, bus_size_t);
519 void	generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
520 	    uint8_t);
521 void	generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
522 	    uint16_t);
523 void	generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
524 	    uint32_t);
525 void	generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
526 	    uint64_t);
527 void	generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
528 	    bus_addr_t, const uint8_t *, bus_size_t);
529 void	generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
530 	    bus_addr_t, uint8_t *, bus_size_t);
531 void	generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
532 	    bus_addr_t, const uint8_t *, bus_size_t);
533 void	generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
534 	    bus_addr_t, uint8_t *, bus_size_t);
535 void	generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
536 	    bus_addr_t, const uint8_t *, bus_size_t);
537 
538 #endif /* _MACHINE_BUS_H_ */
539