1 /* $OpenBSD: bus.h,v 1.27 2024/05/22 05:51:49 jsg Exp $ */
2
3 /*
4 * Copyright (c) 1997 Per Fogelstrom. All rights reserved.
5 * Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Christopher G. Demetriou
18 * for the NetBSD Project.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _MACHINE_BUS_H_
35 #define _MACHINE_BUS_H_
36
37 #include <machine/pio.h>
38
39 #ifdef __STDC__
40 #define CAT(a,b) a##b
41 #define CAT3(a,b,c) a##b##c
42 #else
43 #define CAT(a,b) a/**/b
44 #define CAT3(a,b,c) a/**/b/**/c
45 #endif
46
47 /*
48 * Bus access types.
49 */
50 typedef u_long bus_addr_t;
51 typedef u_long bus_size_t;
52 typedef u_long bus_space_handle_t;
53 typedef struct ppc_bus_space *bus_space_tag_t;
54
55 struct ppc_bus_space {
56 u_int32_t bus_base;
57 u_int32_t bus_size;
58 u_int8_t bus_io; /* IO or memory */
59 };
60 #define POWERPC_BUS_TAG_BASE(x) ((x)->bus_base)
61
62 /*
63 * Access methods for bus resources
64 */
65 int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
66 bus_size_t size, int flags, bus_space_handle_t *bshp);
67 void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
68 bus_size_t size);
69 int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
70 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
71 int bus_space_alloc(bus_space_tag_t tag, bus_addr_t rstart,
72 bus_addr_t rend, bus_size_t size, bus_size_t alignment,
73 bus_size_t boundary, int flags, bus_addr_t *addrp,
74 bus_space_handle_t *handlep);
75 void bus_space_free(bus_space_tag_t tag, bus_space_handle_t handle,
76 bus_size_t size);
77 paddr_t bus_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
78
79 #define BUS_SPACE_MAP_CACHEABLE 0x01
80 #define BUS_SPACE_MAP_LINEAR 0x02
81 #define BUS_SPACE_MAP_PREFETCHABLE 0x04
82
83 /*
84 * void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t);
85 *
86 * Get the kernel virtual address for the mapped bus space.
87 * Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR.
88 */
89 #define bus_space_vaddr(t, h) ((void *)(h))
90
91 #define bus_space_read(n,m) \
92 static __inline CAT3(u_int,m,_t) \
93 CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
94 bus_addr_t ba) \
95 { \
96 return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \
97 }
98
99 bus_space_read(1,8)
100 bus_space_read(2,16)
101 bus_space_read(4,32)
102
103 #define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
104
105 #define bus_space_write(n,m) \
106 static __inline void \
107 CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
108 bus_addr_t ba, CAT3(u_int,m,_t) x) \
109 { \
110 CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \
111 }
112
113 bus_space_write(1,8)
114 bus_space_write(2,16)
115 bus_space_write(4,32)
116
117 #define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
118
119 #define bus_space_read_raw(n,m) \
120 static __inline CAT3(u_int,m,_t) \
121 CAT(bus_space_read_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
122 bus_addr_t ba) \
123 { \
124 return CAT(in,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \
125 }
126
127 bus_space_read_raw(1,8)
128 bus_space_read_raw(2,16)
129 bus_space_read_raw(4,32)
130
131 #define bus_space_read_raw_8 !!! bus_space_read_raw_8 unimplemented !!!
132
133 #define bus_space_write_raw(n,m) \
134 static __inline void \
135 CAT(bus_space_write_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
136 bus_addr_t ba, CAT3(u_int,m,_t) x) \
137 { \
138 CAT(out,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \
139 }
140
141 bus_space_write_raw(1,8)
142 bus_space_write_raw(2,16)
143 bus_space_write_raw(4,32)
144
145 #define bus_space_write_raw_8 !!! bus_space_write_raw_8 unimplemented !!!
146
147 #define bus_space_read_multi(n, m) \
148 static __inline void \
149 CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
150 bus_size_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
151 { \
152 while (cnt--) \
153 *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
154 }
155
156 bus_space_read_multi(1,8)
157 bus_space_read_multi(2,16)
158 bus_space_read_multi(4,32)
159
160 #define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
161
162
163 #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
164
165 #define bus_space_write_multi(n, m) \
166 static __inline void \
167 CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
168 bus_size_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
169 { \
170 while (cnt--) \
171 CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
172 }
173
174 bus_space_write_multi(1,8)
175 bus_space_write_multi(2,16)
176 bus_space_write_multi(4,32)
177
178 #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
179
180 /*
181 * void bus_space_read_region_N(bus_space_tag_t tag,
182 * bus_space_handle_t bsh, bus_size_t offset,
183 * u_intN_t *addr, size_t count);
184 *
185 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
186 * described by tag/handle and starting at `offset' and copy into
187 * buffer provided.
188 */
189 #define __BA(t, h, o) ((void *)((h) + (o)))
190
191 static __inline void
bus_space_read_region_1(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int8_t * addr,size_t count)192 bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
193 bus_size_t offset, u_int8_t *addr, size_t count)
194 {
195 volatile u_int8_t *s = __BA(tag, bsh, offset);
196
197 while (count--)
198 *addr++ = *s++;
199 __asm volatile("eieio; sync");
200 }
201
202 static __inline void
bus_space_read_region_2(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int16_t * addr,size_t count)203 bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
204 bus_size_t offset, u_int16_t *addr, size_t count)
205 {
206 volatile u_int16_t *s = __BA(tag, bsh, offset);
207
208 while (count--)
209 __asm volatile("lhbrx %0, 0, %1" :
210 "=r"(*addr++) : "r"(s++));
211 __asm volatile("eieio; sync");
212 }
213
214 static __inline void
bus_space_read_region_4(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int32_t * addr,size_t count)215 bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
216 bus_size_t offset, u_int32_t *addr, size_t count)
217 {
218 volatile u_int32_t *s = __BA(tag, bsh, offset);
219
220 while (count--)
221 __asm volatile("lwbrx %0, 0, %1" :
222 "=r"(*addr++) : "r"(s++));
223 __asm volatile("eieio; sync");
224 }
225
226 #if 0 /* Cause a link error for bus_space_read_region_8 */
227 #define bus_space_read_region_8 !!! unimplemented !!!
228 #endif
229
230
231 /*
232 * void bus_space_write_region_N(bus_space_tag_t tag,
233 * bus_space_handle_t bsh, bus_size_t offset,
234 * const u_intN_t *addr, size_t count);
235 *
236 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
237 * to bus space described by tag/handle starting at `offset'.
238 */
239
240 static __inline void
bus_space_write_region_1(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,const u_int8_t * addr,size_t count)241 bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
242 bus_size_t offset, const u_int8_t *addr, size_t count)
243 {
244 volatile u_int8_t *d = __BA(tag, bsh, offset);
245
246 while (count--)
247 *d++ = *addr++;
248 __asm volatile("eieio; sync");
249 }
250
251 static __inline void
bus_space_write_region_2(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,const u_int16_t * addr,size_t count)252 bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
253 bus_size_t offset, const u_int16_t *addr, size_t count)
254 {
255 volatile u_int16_t *d = __BA(tag, bsh, offset);
256
257 while (count--)
258 __asm volatile("sthbrx %0, 0, %1" ::
259 "r"(*addr++), "r"(d++));
260 __asm volatile("eieio; sync");
261 }
262
263 static __inline void
bus_space_write_region_4(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,const u_int32_t * addr,size_t count)264 bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
265 bus_size_t offset, const u_int32_t *addr, size_t count)
266 {
267 volatile u_int32_t *d = __BA(tag, bsh, offset);
268
269 while (count--)
270 __asm volatile("stwbrx %0, 0, %1" ::
271 "r"(*addr++), "r"(d++));
272 __asm volatile("eieio; sync");
273 }
274
275 #if 0
276 #define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!!
277 #endif
278
279 /*
280 * void bus_space_read_raw_region_N(bus_space_tag_t tag,
281 * bus_space_handle_t bsh, bus_size_t offset,
282 * u_intN_t *addr, size_t count);
283 *
284 * Read `count' bytes from bus space described by tag/handle and starting
285 * at `offset' and copy into buffer provided w/o bus-host byte swapping.
286 */
287
288 static __inline void
bus_space_read_raw_region_2(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int8_t * addr,size_t count)289 bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
290 bus_size_t offset, u_int8_t *addr, size_t count)
291 {
292 volatile u_int16_t *s = __BA(tag, bsh, offset);
293 u_int16_t *laddr = (void *)addr;
294
295 count = count >> 1;
296
297 while (count--)
298 *laddr++ = *s++;
299 __asm volatile("eieio; sync");
300 }
301
302 static __inline void
bus_space_read_raw_region_4(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int8_t * addr,size_t count)303 bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
304 bus_size_t offset, u_int8_t *addr, size_t count)
305 {
306 volatile u_int32_t *s = __BA(tag, bsh, offset);
307 u_int32_t *laddr = (void *)addr;
308
309 count = count >> 2;
310
311 while (count--)
312 *laddr++ = *s++;
313 __asm volatile("eieio; sync");
314 }
315
316 #if 0 /* Cause a link error for bus_space_read_raw_region_8 */
317 #define bus_space_read_raw_region_8 \
318 !!! bus_space_read_raw_region_8 unimplemented !!!
319 #endif
320
321
322 /*
323 * void bus_space_write_raw_region_N(bus_space_tag_t tag,
324 * bus_space_handle_t bsh, bus_size_t offset,
325 * const u_intN_t *addr, size_t count);
326 *
327 * Write `count' bytes from the buffer provided to bus space described
328 * by tag/handle starting at `offset' w/o host-bus byte swapping.
329 */
330
331 static __inline void
bus_space_write_raw_region_2(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,const u_int8_t * addr,size_t count)332 bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
333 bus_size_t offset, const u_int8_t *addr, size_t count)
334 {
335 volatile u_int16_t *d = __BA(tag, bsh, offset);
336 const u_int16_t *laddr = (void *)addr;
337
338 count = count >> 1;
339
340 while (count--)
341 *d++ = *laddr++;
342 __asm volatile("eieio; sync");
343 }
344
345 static __inline void
bus_space_write_raw_region_4(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,const u_int8_t * addr,size_t count)346 bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
347 bus_size_t offset, const u_int8_t *addr, size_t count)
348 {
349 volatile u_int32_t *d = __BA(tag, bsh, offset);
350 const u_int32_t *laddr = (void *)addr;
351
352 count = count >> 2;
353
354 while (count--)
355 *d++ = *laddr++;
356 __asm volatile("eieio; sync");
357 }
358
359 #if 0
360 #define bus_space_write_raw_region_8 \
361 !!! bus_space_write_raw_region_8 unimplemented !!!
362 #endif
363
364 /*
365 * void bus_space_set_multi_N(bus_space_tag_t tag,
366 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
367 * size_t count);
368 *
369 * Write the 1, 2, 4, or 8 byte value `val' to bus space described
370 * by tag/handle/offset `count' times.
371 */
372 static __inline void bus_space_set_multi_1(bus_space_tag_t,
373 bus_space_handle_t, bus_size_t, u_int8_t, size_t);
374 static __inline void bus_space_set_multi_2(bus_space_tag_t,
375 bus_space_handle_t, bus_size_t, u_int16_t, size_t);
376 static __inline void bus_space_set_multi_4(bus_space_tag_t,
377 bus_space_handle_t, bus_size_t, u_int32_t, size_t);
378
379 static __inline void
bus_space_set_multi_1(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int8_t val,size_t count)380 bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
381 bus_size_t offset, u_int8_t val, size_t count)
382 {
383 volatile u_int8_t *d = __BA(tag, bsh, offset);
384
385 while (count--)
386 *d = val;
387 __asm__ volatile("eieio; sync");
388 }
389
390 static __inline void
bus_space_set_multi_2(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int16_t val,size_t count)391 bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
392 bus_size_t offset, u_int16_t val, size_t count)
393 {
394 volatile u_int16_t *d = __BA(tag, bsh, offset);
395
396 while (count--)
397 __asm__ volatile("sthbrx %0, 0, %1" ::
398 "r"(val), "r"(d));
399 __asm__ volatile("eieio; sync");
400 }
401
402 static __inline void
bus_space_set_multi_4(bus_space_tag_t tag,bus_space_handle_t bsh,bus_size_t offset,u_int32_t val,size_t count)403 bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
404 bus_size_t offset, u_int32_t val, size_t count)
405 {
406 volatile u_int32_t *d = __BA(tag, bsh, offset);
407
408 while (count--)
409 __asm__ volatile("stwbrx %0, 0, %1" ::
410 "r"(val), "r"(d));
411 __asm__ volatile("eieio; sync");
412 }
413
414 #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!!
415
416 /* These are OpenBSD extensions to the general NetBSD bus interface. */
417 void
418 bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
419 bus_addr_t ba, u_int8_t *dst, bus_size_t size);
420 void
421 bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
422 bus_addr_t ba, u_int8_t *dst, bus_size_t size);
423 #define bus_space_read_raw_multi_8 \
424 !!! bus_space_read_raw_multi_8 not implemented !!!
425
426 void
427 bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
428 bus_addr_t ba, const u_int8_t *src, bus_size_t size);
429 void
430 bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
431 bus_addr_t ba, const u_int8_t *src, bus_size_t size);
432 #define bus_space_write_raw_multi_8 \
433 !!! bus_space_write_raw_multi_8 not implemented !!!
434
435 void
436 bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
437 u_int8_t val, bus_size_t c);
438 void
439 bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
440 u_int16_t val, bus_size_t c);
441 void
442 bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
443 u_int32_t val, bus_size_t c);
444 #define bus_space_set_region_8 \
445 !!! bus_space_set_region_8 not implemented !!!
446
447 void
448 bus_space_copy_1(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
449 bus_size_t o1, bus_size_t o2, bus_size_t c);
450 void
451 bus_space_copy_2(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
452 bus_size_t o1, bus_size_t o2, bus_size_t c);
453 void
454 bus_space_copy_4(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
455 bus_size_t o1, bus_size_t o2, bus_size_t c);
456 #define bus_space_copy_8 \
457 !!! bus_space_copy_8 not implemented !!!
458
459 /*
460 * Bus read/write barrier methods.
461 *
462 * void bus_space_barrier(bus_space_tag_t tag,
463 * bus_space_handle_t bsh, bus_size_t offset,
464 * bus_size_t len, int flags);
465 *
466 * Note: powerpc does not currently implement barriers, but we must
467 * provide the flags to MI code.
468 * the processor does have eieio which is effectively the barrier
469 * operator, however due to how memory is mapped this should? not
470 * be required.
471 */
472 #define bus_space_barrier(t, h, o, l, f) \
473 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
474 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
475 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
476
477 #define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */
478 #define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */
479 #define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */
480 #define BUS_DMA_COHERENT 0x0008 /* hint: map memory DMA coherent */
481 #define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
482 #define BUS_DMA_BUS2 0x0020
483 #define BUS_DMA_BUS3 0x0040
484 #define BUS_DMA_BUS4 0x0080
485 #define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
486 #define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
487 #define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
488 #define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
489 #define BUS_DMA_NOCACHE 0x1000 /* map memory uncached */
490 #define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
491
492
493 /* Forwards needed by prototypes below. */
494 struct mbuf;
495 struct proc;
496 struct uio;
497
498 #define BUS_DMASYNC_POSTREAD 0x01
499 #define BUS_DMASYNC_POSTWRITE 0x02
500 #define BUS_DMASYNC_PREREAD 0x04
501 #define BUS_DMASYNC_PREWRITE 0x08
502
503 typedef struct powerpc_bus_dma_tag *bus_dma_tag_t;
504 typedef struct powerpc_bus_dmamap *bus_dmamap_t;
505
506 /*
507 * bus_dma_segment_t
508 *
509 * Describes a single contiguous DMA transaction. Values
510 * are suitable for programming into DMA registers.
511 */
512 struct powerpc_bus_dma_segment {
513 bus_addr_t ds_addr; /* DMA address */
514 bus_size_t ds_len; /* length of transfer */
515 };
516 typedef struct powerpc_bus_dma_segment bus_dma_segment_t;
517
518 /*
519 * bus_dma_tag_t
520 *
521 * A machine-dependent opaque type describing the implementation of
522 * DMA for a given bus.
523 */
524
525 struct powerpc_bus_dma_tag {
526 void *_cookie; /* cookie used in the guts */
527
528 /*
529 * DMA mapping methods.
530 */
531 int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
532 bus_size_t, bus_size_t, int, bus_dmamap_t *);
533 void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
534 int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
535 bus_size_t, struct proc *, int);
536 int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
537 struct mbuf *, int);
538 int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
539 struct uio *, int);
540 int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
541 bus_dma_segment_t *, int, bus_size_t, int);
542 void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
543 void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
544 bus_addr_t, bus_size_t, int);
545
546 /*
547 * DMA memory utility functions.
548 */
549 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
550 bus_size_t, bus_dma_segment_t *, int, int *, int);
551 int (*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t,
552 bus_size_t, bus_dma_segment_t *, int, int *, int,
553 bus_addr_t, bus_addr_t);
554 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
555 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
556 int, size_t, caddr_t *, int);
557 void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
558 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
559 int, off_t, int, int);
560 };
561
562 #define bus_dmamap_create(t, s, n, m, b, f, p) \
563 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
564 #define bus_dmamap_destroy(t, p) \
565 (*(t)->_dmamap_destroy)((t), (p))
566 #define bus_dmamap_load(t, m, b, s, p, f) \
567 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
568 #define bus_dmamap_load_mbuf(t, m, b, f) \
569 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
570 #define bus_dmamap_load_uio(t, m, u, f) \
571 (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
572 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \
573 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
574 #define bus_dmamap_unload(t, p) \
575 (*(t)->_dmamap_unload)((t), (p))
576 #define bus_dmamap_sync(t, p, a, l, o) \
577 (void)((t)->_dmamap_sync ? \
578 (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
579
580 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
581 (*(t)->_dmamem_alloc)((t)->_cookie, (s), (a), (b), (sg), (n), (r), (f))
582 #define bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h) \
583 (*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg), \
584 (n), (r), (f), (l), (h))
585 #define bus_dmamem_free(t, sg, n) \
586 (*(t)->_dmamem_free)((t)->_cookie, (sg), (n))
587 #define bus_dmamem_map(t, sg, n, s, k, f) \
588 (*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
589 #define bus_dmamem_unmap(t, k, s) \
590 (*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
591 #define bus_dmamem_mmap(t, sg, n, o, p, f) \
592 (*(t)->_dmamem_mmap)((t)->_cookie, (sg), (n), (o), (p), (f))
593
594 int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
595 bus_size_t, bus_size_t, int, bus_dmamap_t *);
596 void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
597 int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
598 bus_size_t, struct proc *, int);
599 int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
600 int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
601 int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
602 bus_dma_segment_t *, int, bus_size_t, int);
603 void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
604 void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, bus_size_t,
605 int);
606
607 int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
608 bus_size_t, bus_dma_segment_t *, int, int *, int);
609 int _dmamem_alloc_range( bus_dma_tag_t, bus_size_t, bus_size_t,
610 bus_size_t, bus_dma_segment_t *, int, int *, int,
611 bus_addr_t, bus_addr_t);
612 void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
613 int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
614 int, size_t, caddr_t *, int);
615 void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
616 paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
617
618 /*
619 * bus_dmamap_t
620 *
621 * Describes a DMA mapping.
622 */
623 struct powerpc_bus_dmamap {
624 /*
625 * PRIVATE MEMBERS: not for use by machine-independent code.
626 */
627 bus_size_t _dm_size; /* largest DMA transfer mappable */
628 int _dm_segcnt; /* number of segs this map can map */
629 bus_size_t _dm_maxsegsz; /* largest possible segment */
630 bus_size_t _dm_boundary; /* don't cross this */
631 int _dm_flags; /* misc. flags */
632
633 void *_dm_cookie; /* cookie for bus-specific functions */
634
635 /*
636 * PUBLIC MEMBERS: these are used by machine-independent code.
637 */
638 bus_size_t dm_mapsize; /* size of the mapping */
639 int dm_nsegs; /* # valid segments in mapping */
640 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
641 };
642
643 #endif /* _MACHINE_BUS_H_ */
644