1 /* $OpenBSD: bus.h,v 1.8 2020/04/14 17:35:28 kettenis Exp $ */
2
3 /*
4 * Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #ifndef _MACHINE_BUS_H_
28 #define _MACHINE_BUS_H_
29
30 #ifdef __STDC__
31 #define CAT(a,b) a##b
32 #define CAT3(a,b,c) a##b##c
33 #else
34 #define CAT(a,b) a/**/b
35 #define CAT3(a,b,c) a/**/b/**/c
36 #endif
37
38 /*
39 * Bus access types.
40 */
41 struct mips_bus_space;
42 typedef u_long bus_addr_t;
43 typedef u_long bus_size_t;
44 typedef u_long bus_space_handle_t;
45 typedef struct mips_bus_space *bus_space_tag_t;
46
47 struct mips_bus_space {
48 bus_addr_t bus_base;
49 void *bus_private;
50 u_int8_t (*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
51 bus_size_t);
52 void (*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
53 bus_size_t, u_int8_t);
54 u_int16_t (*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
55 bus_size_t);
56 void (*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
57 bus_size_t, u_int16_t);
58 u_int32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
59 bus_size_t);
60 void (*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
61 bus_size_t, u_int32_t);
62 u_int64_t (*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
63 bus_size_t);
64 void (*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
65 bus_size_t, u_int64_t);
66 void (*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
67 bus_addr_t, u_int8_t *, bus_size_t);
68 void (*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
69 bus_addr_t, const u_int8_t *, bus_size_t);
70 void (*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
71 bus_addr_t, u_int8_t *, bus_size_t);
72 void (*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
73 bus_addr_t, const u_int8_t *, bus_size_t);
74 void (*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
75 bus_addr_t, u_int8_t *, bus_size_t);
76 void (*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
77 bus_addr_t, const u_int8_t *, bus_size_t);
78 int (*_space_map)(bus_space_tag_t , bus_addr_t,
79 bus_size_t, int, bus_space_handle_t *);
80 void (*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
81 bus_size_t);
82 int (*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
83 bus_size_t, bus_size_t, bus_space_handle_t *);
84 void * (*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
85 paddr_t (*_space_mmap)(bus_space_tag_t, bus_addr_t, off_t,
86 int, int);
87 };
88
89 #define bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
90 #define bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
91 #define bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
92 #define bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
93
94 #define bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
95 #define bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
96 #define bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
97 #define bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
98
99 #define bus_space_read_raw_multi_2(t, h, a, b, l) \
100 (*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
101 #define bus_space_read_raw_multi_4(t, h, a, b, l) \
102 (*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
103 #define bus_space_read_raw_multi_8(t, h, a, b, l) \
104 (*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
105
106 #define bus_space_write_raw_multi_2(t, h, a, b, l) \
107 (*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
108 #define bus_space_write_raw_multi_4(t, h, a, b, l) \
109 (*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
110 #define bus_space_write_raw_multi_8(t, h, a, b, l) \
111 (*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
112
113 #define bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
114 #define bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
115 #define bus_space_subregion(t, h, o, s, p) \
116 (*(t)->_space_subregion)((t), (h), (o), (s), (p))
117
118 #define BUS_SPACE_MAP_CACHEABLE 0x01
119 #define BUS_SPACE_MAP_LINEAR 0x02
120 #define BUS_SPACE_MAP_PREFETCHABLE 0x04
121
122 #define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
123 #define bus_space_mmap(t, a, o, p, f) \
124 (*(t)->_space_mmap)((t), (a), (o), (p), (f))
125
126 /*----------------------------------------------------------------------------*/
127 #define bus_space_read_multi(n,m) \
128 static __inline void \
129 CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
130 bus_size_t o, CAT3(u_int,m,_t) *x, size_t cnt) \
131 { \
132 while (cnt--) \
133 *x++ = CAT(bus_space_read_,n)(bst, bsh, o); \
134 }
135
136 bus_space_read_multi(1,8)
137 bus_space_read_multi(2,16)
138 bus_space_read_multi(4,32)
139 bus_space_read_multi(8,64)
140
141 /*----------------------------------------------------------------------------*/
142 #define bus_space_read_region(n,m) \
143 static __inline void \
144 CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
145 bus_addr_t ba, CAT3(u_int,m,_t) *x, size_t cnt) \
146 { \
147 while (cnt--) { \
148 *x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
149 ba += (n); \
150 } \
151 }
152
153 bus_space_read_region(1,8)
154 bus_space_read_region(2,16)
155 bus_space_read_region(4,32)
156 bus_space_read_region(8,64)
157
158 /*----------------------------------------------------------------------------*/
159 #define bus_space_read_raw_region(n,m) \
160 static __inline void \
161 CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst, \
162 bus_space_handle_t bsh, \
163 bus_addr_t ba, u_int8_t *x, size_t cnt) \
164 { \
165 cnt >>= ((n) >> 1); \
166 while (cnt--) { \
167 CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n)); \
168 ba += (n); \
169 x += (n); \
170 } \
171 }
172
173 bus_space_read_raw_region(2,16)
174 bus_space_read_raw_region(4,32)
175 bus_space_read_raw_region(8,64)
176
177 /*----------------------------------------------------------------------------*/
178 #define bus_space_write_multi(n,m) \
179 static __inline void \
180 CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
181 bus_size_t o, const CAT3(u_int,m,_t) *x, size_t cnt) \
182 { \
183 while (cnt--) \
184 CAT(bus_space_write_,n)(bst, bsh, o, *x++); \
185 }
186
187 bus_space_write_multi(1,8)
188 bus_space_write_multi(2,16)
189 bus_space_write_multi(4,32)
190 bus_space_write_multi(8,64)
191
192 /*----------------------------------------------------------------------------*/
193 #define bus_space_write_region(n,m) \
194 static __inline void \
195 CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
196 bus_addr_t ba, const CAT3(u_int,m,_t) *x, size_t cnt) \
197 { \
198 while (cnt--) { \
199 CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
200 ba += (n); \
201 } \
202 }
203
204 bus_space_write_region(1,8)
205 bus_space_write_region(2,16)
206 bus_space_write_region(4,32)
207 bus_space_write_region(8,64)
208
209 /*----------------------------------------------------------------------------*/
210 #define bus_space_write_raw_region(n,m) \
211 static __inline void \
212 CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst, \
213 bus_space_handle_t bsh, \
214 bus_addr_t ba, const u_int8_t *x, size_t cnt) \
215 { \
216 cnt >>= ((n) >> 1); \
217 while (cnt--) { \
218 CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n)); \
219 ba += (n); \
220 x += (n); \
221 } \
222 }
223
224 bus_space_write_raw_region(2,16)
225 bus_space_write_raw_region(4,32)
226 bus_space_write_raw_region(8,64)
227
228 /*----------------------------------------------------------------------------*/
229 #define bus_space_set_region(n,m) \
230 static __inline void \
231 CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
232 bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt) \
233 { \
234 while (cnt--) { \
235 CAT(bus_space_write_,n)(bst, bsh, ba, x); \
236 ba += (n); \
237 } \
238 }
239
240 bus_space_set_region(1,8)
241 bus_space_set_region(2,16)
242 bus_space_set_region(4,32)
243 bus_space_set_region(8,64)
244
245 /*----------------------------------------------------------------------------*/
246 static __inline void
bus_space_copy_1(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)247 bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
248 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
249 {
250 char *s = (char *)(h1 + o1);
251 char *d = (char *)(h2 + o2);
252
253 while (c--)
254 *d++ = *s++;
255 }
256
257
258 static __inline void
bus_space_copy_2(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)259 bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
260 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
261 {
262 short *s = (short *)(h1 + o1);
263 short *d = (short *)(h2 + o2);
264
265 while (c--)
266 *d++ = *s++;
267 }
268
269 static __inline void
bus_space_copy_4(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)270 bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
271 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
272 {
273 int *s = (int *)(h1 + o1);
274 int *d = (int *)(h2 + o2);
275
276 while (c--)
277 *d++ = *s++;
278 }
279
280 static __inline void
bus_space_copy_8(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)281 bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
282 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
283 {
284 int64_t *s = (int64_t *)(h1 + o1);
285 int64_t *d = (int64_t *)(h2 + o2);
286
287 while (c--)
288 *d++ = *s++;
289 }
290
291 int generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
292 bus_space_handle_t *);
293 void generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
294 int generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
295 bus_size_t, bus_space_handle_t *);
296 void *generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
297 uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
298 uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
299 uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
300 uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
301 void generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
302 bus_addr_t, uint8_t *, bus_size_t);
303 void generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
304 uint8_t);
305 void generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
306 uint16_t);
307 void generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
308 uint32_t);
309 void generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
310 uint64_t);
311 void generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
312 bus_addr_t, const uint8_t *, bus_size_t);
313 void generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
314 bus_addr_t, uint8_t *, bus_size_t);
315 void generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
316 bus_addr_t, const uint8_t *, bus_size_t);
317 void generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
318 bus_addr_t, uint8_t *, bus_size_t);
319 void generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
320 bus_addr_t, const uint8_t *, bus_size_t);
321 paddr_t generic_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
322
323 /*----------------------------------------------------------------------------*/
324 /*
325 * Bus read/write barrier methods.
326 *
327 * void bus_space_barrier(bus_space_tag_t tag,
328 * bus_space_handle_t bsh, bus_size_t offset,
329 * bus_size_t len, int flags);
330 *
331 */
332 static inline void
bus_space_barrier(bus_space_tag_t t,bus_space_handle_t h,bus_size_t offset,bus_size_t length,int flags)333 bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
334 bus_size_t length, int flags)
335 {
336 __asm__ volatile ("sync" ::: "memory");
337 }
338 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
339 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
340
341 #define BUS_DMA_WAITOK 0x0000
342 #define BUS_DMA_NOWAIT 0x0001
343 #define BUS_DMA_ALLOCNOW 0x0002
344 #define BUS_DMA_COHERENT 0x0008
345 #define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
346 #define BUS_DMA_BUS2 0x0020
347 #define BUS_DMA_BUS3 0x0040
348 #define BUS_DMA_BUS4 0x0080
349 #define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
350 #define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
351 #define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
352 #define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
353 #define BUS_DMA_NOCACHE 0x1000
354 #define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
355
356 /* Forwards needed by prototypes below. */
357 struct mbuf;
358 struct proc;
359 struct uio;
360
361 #define BUS_DMASYNC_POSTREAD 0x0001
362 #define BUS_DMASYNC_POSTWRITE 0x0002
363 #define BUS_DMASYNC_PREREAD 0x0004
364 #define BUS_DMASYNC_PREWRITE 0x0008
365
366 typedef struct machine_bus_dma_tag *bus_dma_tag_t;
367 typedef struct machine_bus_dmamap *bus_dmamap_t;
368
369 /*
370 * bus_dma_segment_t
371 *
372 * Describes a single contiguous DMA transaction. Values
373 * are suitable for programming into DMA registers.
374 */
375 struct machine_bus_dma_segment {
376 bus_addr_t ds_addr; /* DMA address */
377 bus_size_t ds_len; /* length of transfer */
378
379 paddr_t _ds_paddr; /* CPU address */
380 vaddr_t _ds_vaddr; /* CPU address */
381 };
382 typedef struct machine_bus_dma_segment bus_dma_segment_t;
383
384 /*
385 * bus_dma_tag_t
386 *
387 * A machine-dependent opaque type describing the implementation of
388 * DMA for a given bus.
389 */
390
391 struct machine_bus_dma_tag {
392 void *_cookie; /* cookie used in the guts */
393
394 /*
395 * DMA mapping methods.
396 */
397 int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
398 bus_size_t, bus_size_t, int, bus_dmamap_t *);
399 void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
400 int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
401 bus_size_t, struct proc *, int);
402 int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
403 struct mbuf *, int);
404 int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
405 struct uio *, int);
406 int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
407 bus_dma_segment_t *, int, bus_size_t, int);
408 int (*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
409 bus_size_t, struct proc *, int, paddr_t *, int *, int);
410 void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
411 void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
412 bus_addr_t, bus_size_t, int);
413
414 /*
415 * DMA memory utility functions.
416 */
417 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
418 bus_size_t, bus_dma_segment_t *, int, int *, int);
419 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
420 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
421 int, size_t, caddr_t *, int);
422 void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
423 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
424 int, off_t, int, int);
425
426 /*
427 * internal memory address translation information.
428 */
429 bus_addr_t (*_pa_to_device)(paddr_t);
430 paddr_t (*_device_to_pa)(bus_addr_t);
431 bus_addr_t _dma_mask;
432 };
433
434 #define bus_dmamap_create(t, s, n, m, b, f, p) \
435 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
436 #define bus_dmamap_destroy(t, p) \
437 (*(t)->_dmamap_destroy)((t), (p))
438 #define bus_dmamap_load(t, m, b, s, p, f) \
439 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
440 #define bus_dmamap_load_mbuf(t, m, b, f) \
441 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
442 #define bus_dmamap_load_uio(t, m, u, f) \
443 (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
444 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \
445 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
446 #define bus_dmamap_unload(t, p) \
447 (*(t)->_dmamap_unload)((t), (p))
448 #define bus_dmamap_sync(t, p, a, l, o) \
449 (void)((t)->_dmamap_sync ? \
450 (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
451
452 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
453 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
454 #define bus_dmamem_free(t, sg, n) \
455 (*(t)->_dmamem_free)((t), (sg), (n))
456 #define bus_dmamem_map(t, sg, n, s, k, f) \
457 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
458 #define bus_dmamem_unmap(t, k, s) \
459 (*(t)->_dmamem_unmap)((t), (k), (s))
460 #define bus_dmamem_mmap(t, sg, n, o, p, f) \
461 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
462
463 int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
464 bus_size_t, bus_size_t, int, bus_dmamap_t *);
465 void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
466 int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
467 bus_size_t, struct proc *, int);
468 int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
469 int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
470 int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
471 bus_dma_segment_t *, int, bus_size_t, int);
472 int _dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
473 bus_size_t, struct proc *, int, paddr_t *, int *, int);
474 void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
475 void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
476 bus_size_t, int);
477
478 int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
479 bus_size_t, bus_dma_segment_t *, int, int *, int);
480 void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
481 int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
482 int, size_t, caddr_t *, int);
483 void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
484 paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
485 int _dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
486 bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
487
488 /*
489 * bus_dmamap_t
490 *
491 * Describes a DMA mapping.
492 */
493 struct machine_bus_dmamap {
494 /*
495 * PRIVATE MEMBERS: not for use by machine-independent code.
496 */
497 bus_size_t _dm_size; /* largest DMA transfer mappable */
498 int _dm_segcnt; /* number of segs this map can map */
499 bus_size_t _dm_maxsegsz; /* largest possible segment */
500 bus_size_t _dm_boundary; /* don't cross this */
501 int _dm_flags; /* misc. flags */
502
503 void *_dm_cookie; /* cookie for bus-specific functions */
504
505 /*
506 * PUBLIC MEMBERS: these are used by machine-independent code.
507 */
508 bus_size_t dm_mapsize; /* size of the mapping */
509 int dm_nsegs; /* # valid segments in mapping */
510 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
511 };
512
513 #endif /* _MACHINE_BUS_H_ */
514