1 /* $OpenBSD: pci_machdep.c,v 1.81 2025/01/23 11:24:34 kettenis Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.3 2003/05/07 21:33:58 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles M. Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/extent.h> 71 #include <sys/malloc.h> 72 73 #include <machine/bus.h> 74 75 #include <machine/pio.h> 76 #include <machine/intr.h> 77 #include <machine/biosvar.h> 78 79 #include <dev/isa/isareg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcidevs.h> 83 #include <dev/pci/ppbreg.h> 84 85 #include "ioapic.h" 86 87 #if NIOAPIC > 0 88 #include <machine/i82093var.h> 89 #include <machine/mpbiosvar.h> 90 #endif 91 92 #include "acpi.h" 93 94 #include "acpidmar.h" 95 #if NACPIDMAR > 0 96 #include <dev/acpi/acpidmar.h> 97 #endif 98 99 /* 100 * Memory Mapped Configuration space access. 101 * 102 * Since mapping the whole configuration space will cost us up to 103 * 256MB of kernel virtual memory, we use separate mappings per bus. 104 * The mappings are created on-demand, such that we only use kernel 105 * virtual memory for busses that are actually present. 106 */ 107 bus_addr_t pci_mcfg_addr; 108 int pci_mcfg_min_bus, pci_mcfg_max_bus; 109 bus_space_tag_t pci_mcfgt; 110 bus_space_handle_t pci_mcfgh[256]; 111 112 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 113 114 #define PCI_CONF_LOCK() \ 115 do { \ 116 mtx_enter(&pci_conf_lock); \ 117 } while (0) 118 119 #define PCI_CONF_UNLOCK() \ 120 do { \ 121 mtx_leave(&pci_conf_lock); \ 122 } while (0) 123 124 #define PCI_MODE1_ENABLE 0x80000000UL 125 #define PCI_MODE1_ADDRESS_REG 0x0cf8 126 #define PCI_MODE1_DATA_REG 0x0cfc 127 128 /* 129 * PCI doesn't have any special needs; just use the generic versions 130 * of these functions. 131 */ 132 struct bus_dma_tag pci_bus_dma_tag = { 133 NULL, /* _may_bounce */ 134 _bus_dmamap_create, 135 _bus_dmamap_destroy, 136 _bus_dmamap_load, 137 _bus_dmamap_load_mbuf, 138 _bus_dmamap_load_uio, 139 _bus_dmamap_load_raw, 140 _bus_dmamap_unload, 141 _bus_dmamap_sync, 142 _bus_dmamem_alloc, 143 _bus_dmamem_alloc_range, 144 _bus_dmamem_free, 145 _bus_dmamem_map, 146 _bus_dmamem_unmap, 147 _bus_dmamem_mmap, 148 }; 149 150 void 151 pci_mcfg_init(bus_space_tag_t iot, bus_addr_t addr, int segment, 152 int min_bus, int max_bus) 153 { 154 if (segment == 0) { 155 pci_mcfgt = iot; 156 pci_mcfg_addr = addr; 157 pci_mcfg_min_bus = min_bus; 158 pci_mcfg_max_bus = max_bus; 159 } 160 } 161 162 pci_chipset_tag_t 163 pci_lookup_segment(int segment, int bus) 164 { 165 KASSERT(segment == 0); 166 return NULL; 167 } 168 169 void 170 pci_attach_hook(struct device *parent, struct device *self, 171 struct pcibus_attach_args *pba) 172 { 173 } 174 175 int 176 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 177 { 178 return (32); 179 } 180 181 pcitag_t 182 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 183 { 184 if (bus >= 256 || device >= 32 || function >= 8) 185 panic("pci_make_tag: bad request"); 186 187 return (PCI_MODE1_ENABLE | 188 (bus << 16) | (device << 11) | (function << 8)); 189 } 190 191 void 192 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 193 { 194 if (bp != NULL) 195 *bp = (tag >> 16) & 0xff; 196 if (dp != NULL) 197 *dp = (tag >> 11) & 0x1f; 198 if (fp != NULL) 199 *fp = (tag >> 8) & 0x7; 200 } 201 202 int 203 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 204 { 205 int bus; 206 207 if (pci_mcfg_addr) { 208 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 209 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 210 return PCIE_CONFIG_SPACE_SIZE; 211 } 212 213 return PCI_CONFIG_SPACE_SIZE; 214 } 215 216 void 217 pci_mcfg_map_bus(int bus) 218 { 219 if (pci_mcfgh[bus]) 220 return; 221 222 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 223 0, &pci_mcfgh[bus])) 224 panic("pci_conf_read: cannot map mcfg space"); 225 } 226 227 pcireg_t 228 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 229 { 230 pcireg_t data; 231 int bus; 232 233 KASSERT((reg & 0x3) == 0); 234 235 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 236 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 237 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 238 pci_mcfg_map_bus(bus); 239 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 240 (tag & 0x000ff00) << 4 | reg); 241 return data; 242 } 243 } 244 245 PCI_CONF_LOCK(); 246 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 247 data = inl(PCI_MODE1_DATA_REG); 248 outl(PCI_MODE1_ADDRESS_REG, 0); 249 PCI_CONF_UNLOCK(); 250 251 return data; 252 } 253 254 void 255 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 256 { 257 int bus; 258 259 KASSERT((reg & 0x3) == 0); 260 261 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 262 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 263 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 264 pci_mcfg_map_bus(bus); 265 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 266 (tag & 0x000ff00) << 4 | reg, data); 267 return; 268 } 269 } 270 271 PCI_CONF_LOCK(); 272 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 273 outl(PCI_MODE1_DATA_REG, data); 274 outl(PCI_MODE1_ADDRESS_REG, 0); 275 PCI_CONF_UNLOCK(); 276 } 277 278 int 279 pci_msix_table_map(pci_chipset_tag_t pc, pcitag_t tag, 280 bus_space_tag_t memt, bus_space_handle_t *memh) 281 { 282 bus_addr_t base; 283 pcireg_t reg, table, type; 284 int bir, offset; 285 int off, tblsz; 286 287 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 288 panic("%s: no msix capability", __func__); 289 290 table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE); 291 bir = (table & PCI_MSIX_TABLE_BIR); 292 offset = (table & PCI_MSIX_TABLE_OFF); 293 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 294 295 bir = PCI_MAPREG_START + bir * 4; 296 type = pci_mapreg_type(pc, tag, bir); 297 if (pci_mapreg_info(pc, tag, bir, type, &base, NULL, NULL) || 298 _bus_space_map(memt, base + offset, tblsz * 16, 0, memh)) 299 return -1; 300 301 return 0; 302 } 303 304 void 305 pci_msix_table_unmap(pci_chipset_tag_t pc, pcitag_t tag, 306 bus_space_tag_t memt, bus_space_handle_t memh) 307 { 308 pcireg_t reg; 309 int tblsz; 310 311 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 312 panic("%s: no msix capability", __func__); 313 314 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 315 _bus_space_unmap(memt, memh, tblsz * 16, NULL); 316 } 317 318 /* 319 * We pack the MSI vector number into the lower 8 bits of the PCI tag 320 * and use that as the MSI/MSI-X "PIC" pin number. This allows us to 321 * address 256 MSI vectors which ought to be enough for anybody. 322 */ 323 #define PCI_MSI_VEC_MASK 0xff 324 #define PCI_MSI_VEC(pin) ((pin) & PCI_MSI_VEC_MASK) 325 #define PCI_MSI_TAG(pin) ((pin) & ~PCI_MSI_VEC_MASK) 326 #define PCI_MSI_PIN(tag, vec) ((tag) | (vec)) 327 328 void msi_hwmask(struct pic *, int); 329 void msi_hwunmask(struct pic *, int); 330 void msi_addroute(struct pic *, struct cpu_info *, int, int, int); 331 void msi_delroute(struct pic *, struct cpu_info *, int, int, int); 332 int msi_allocidtvec(struct pic *, int, int, int); 333 334 struct pic msi_pic = { 335 {0, {NULL}, NULL, 0, "msi", NULL, 0, 0}, 336 PIC_MSI, 337 #ifdef MULTIPROCESSOR 338 {}, 339 #endif 340 msi_hwmask, 341 msi_hwunmask, 342 msi_addroute, 343 msi_delroute, 344 msi_allocidtvec, 345 NULL, 346 ioapic_edge_stubs 347 }; 348 349 void 350 msi_hwmask(struct pic *pic, int pin) 351 { 352 pci_chipset_tag_t pc = NULL; /* XXX */ 353 pcitag_t tag = PCI_MSI_TAG(pin); 354 int vec = PCI_MSI_VEC(pin); 355 pcireg_t reg, mask; 356 int off; 357 358 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 359 return; 360 361 /* We can't mask if per-vector masking isn't implemented. */ 362 if ((reg & PCI_MSI_MC_PVMASK) == 0) 363 return; 364 365 if (reg & PCI_MSI_MC_C64) { 366 mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK64); 367 pci_conf_write(pc, tag, off + PCI_MSI_MASK64, 368 mask | (1U << vec)); 369 } else { 370 mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK32); 371 pci_conf_write(pc, tag, off + PCI_MSI_MASK32, 372 mask | (1U << vec)); 373 } 374 } 375 376 void 377 msi_hwunmask(struct pic *pic, int pin) 378 { 379 pci_chipset_tag_t pc = NULL; /* XXX */ 380 pcitag_t tag = PCI_MSI_TAG(pin); 381 int vec = PCI_MSI_VEC(pin); 382 pcireg_t reg, mask; 383 int off; 384 385 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 386 return; 387 388 /* We can't mask if per-vector masking isn't implemented. */ 389 if ((reg & PCI_MSI_MC_PVMASK) == 0) 390 return; 391 392 if (reg & PCI_MSI_MC_C64) { 393 mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK64); 394 pci_conf_write(pc, tag, off + PCI_MSI_MASK64, 395 mask & ~(1U << vec)); 396 } else { 397 mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK32); 398 pci_conf_write(pc, tag, off + PCI_MSI_MASK32, 399 mask & ~(1U << vec)); 400 } 401 } 402 403 void 404 msi_addroute(struct pic *pic, struct cpu_info *ci, int pin, int idtvec, 405 int type) 406 { 407 pci_chipset_tag_t pc = NULL; /* XXX */ 408 pcitag_t tag = PCI_MSI_TAG(pin); 409 int vec = PCI_MSI_VEC(pin); 410 pcireg_t reg, addr; 411 int off; 412 413 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 414 panic("%s: no msi capability", __func__); 415 416 if (vec != 0) 417 return; 418 419 addr = 0xfee00000UL | (ci->ci_apicid << 12); 420 421 if (reg & PCI_MSI_MC_C64) { 422 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 423 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 424 pci_conf_write(pc, tag, off + PCI_MSI_MD64, idtvec); 425 } else { 426 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 427 pci_conf_write(pc, tag, off + PCI_MSI_MD32, idtvec); 428 } 429 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 430 } 431 432 void 433 msi_delroute(struct pic *pic, struct cpu_info *ci, int pin, int idtvec, 434 int type) 435 { 436 pci_chipset_tag_t pc = NULL; /* XXX */ 437 pcitag_t tag = PCI_MSI_TAG(pin); 438 int vec = PCI_MSI_VEC(pin); 439 pcireg_t reg; 440 int off; 441 442 if (vec != 0) 443 return; 444 445 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) 446 pci_conf_write(pc, tag, off, reg & ~PCI_MSI_MC_MSIE); 447 } 448 449 int 450 msi_allocidtvec(struct pic *pic, int pin, int low, int high) 451 { 452 pci_chipset_tag_t pc = NULL; /* XXX */ 453 pcitag_t tag = PCI_MSI_TAG(pin); 454 int vec = PCI_MSI_VEC(pin); 455 int idtvec, mme, off; 456 pcireg_t reg; 457 458 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 459 panic("%s: no msi capability", __func__); 460 461 reg = pci_conf_read(pc, tag, off); 462 mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT); 463 if (vec >= (1 << mme)) 464 return 0; 465 466 if (vec == 0) { 467 idtvec = idt_vec_alloc_range(low, high, (1 << mme)); 468 if (reg & PCI_MSI_MC_C64) 469 pci_conf_write(pc, tag, off + PCI_MSI_MD64, idtvec); 470 else 471 pci_conf_write(pc, tag, off + PCI_MSI_MD32, idtvec); 472 } else { 473 if (reg & PCI_MSI_MC_C64) 474 reg = pci_conf_read(pc, tag, off + PCI_MSI_MD64); 475 else 476 reg = pci_conf_read(pc, tag, off + PCI_MSI_MD32); 477 KASSERT(reg > 0); 478 idtvec = reg + vec; 479 } 480 481 return idtvec; 482 } 483 484 int 485 pci_intr_enable_msivec(struct pci_attach_args *pa, int num_vec) 486 { 487 pci_chipset_tag_t pc = pa->pa_pc; 488 pcitag_t tag = pa->pa_tag; 489 pcireg_t reg; 490 int mmc, mme, off; 491 492 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 493 pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 494 return 1; 495 496 mmc = ((reg & PCI_MSI_MC_MMC_MASK) >> PCI_MSI_MC_MMC_SHIFT); 497 if (num_vec > (1 << mmc)) 498 return 1; 499 500 mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT); 501 while ((1 << mme) < num_vec) 502 mme++; 503 reg &= ~PCI_MSI_MC_MME_MASK; 504 reg |= (mme << PCI_MSI_MC_MME_SHIFT); 505 pci_conf_write(pc, tag, off, reg); 506 507 return 0; 508 } 509 510 int 511 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 512 { 513 pci_chipset_tag_t pc = pa->pa_pc; 514 pcitag_t tag = pa->pa_tag; 515 pcireg_t reg; 516 int off; 517 518 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 519 pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 520 return 1; 521 522 /* Make sure we only enable one MSI vector. */ 523 reg &= ~PCI_MSI_MC_MME_MASK; 524 pci_conf_write(pc, tag, off, reg); 525 526 ihp->tag = tag; 527 ihp->line = APIC_INT_VIA_MSG; 528 ihp->pin = 0; 529 return 0; 530 } 531 532 int 533 pci_intr_map_msivec(struct pci_attach_args *pa, int vec, 534 pci_intr_handle_t *ihp) 535 { 536 pci_chipset_tag_t pc = pa->pa_pc; 537 pcitag_t tag = pa->pa_tag; 538 pcireg_t reg; 539 int mme, off; 540 541 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 542 pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 543 return 1; 544 545 mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT); 546 if (vec >= (1 << mme)) 547 return 1; 548 549 ihp->tag = PCI_MSI_PIN(tag, vec); 550 ihp->line = APIC_INT_VIA_MSG; 551 ihp->pin = 0; 552 return 0; 553 } 554 555 void msix_hwmask(struct pic *, int); 556 void msix_hwunmask(struct pic *, int); 557 void msix_addroute(struct pic *, struct cpu_info *, int, int, int); 558 void msix_delroute(struct pic *, struct cpu_info *, int, int, int); 559 560 struct pic msix_pic = { 561 {0, {NULL}, NULL, 0, "msix", NULL, 0, 0}, 562 PIC_MSI, 563 #ifdef MULTIPROCESSOR 564 {}, 565 #endif 566 msix_hwmask, 567 msix_hwunmask, 568 msix_addroute, 569 msix_delroute, 570 NULL, 571 NULL, 572 ioapic_edge_stubs 573 }; 574 575 void 576 msix_hwmask(struct pic *pic, int pin) 577 { 578 pci_chipset_tag_t pc = NULL; /* XXX */ 579 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 580 bus_space_handle_t memh; 581 pcitag_t tag = PCI_MSI_TAG(pin); 582 int entry = PCI_MSI_VEC(pin); 583 pcireg_t reg; 584 uint32_t ctrl; 585 586 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 587 return; 588 589 KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg)); 590 591 if (pci_msix_table_map(pc, tag, memt, &memh)) 592 panic("%s: cannot map registers", __func__); 593 594 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 595 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 596 ctrl | PCI_MSIX_VC_MASK); 597 598 pci_msix_table_unmap(pc, tag, memt, memh); 599 } 600 601 void 602 msix_hwunmask(struct pic *pic, int pin) 603 { 604 pci_chipset_tag_t pc = NULL; /* XXX */ 605 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 606 bus_space_handle_t memh; 607 pcitag_t tag = PCI_MSI_TAG(pin); 608 int entry = PCI_MSI_VEC(pin); 609 pcireg_t reg; 610 uint32_t ctrl; 611 612 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 613 return; 614 615 if (pci_msix_table_map(pc, tag, memt, &memh)) 616 panic("%s: cannot map registers", __func__); 617 618 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 619 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 620 ctrl & ~PCI_MSIX_VC_MASK); 621 622 pci_msix_table_unmap(pc, tag, memt, memh); 623 } 624 625 void 626 msix_addroute(struct pic *pic, struct cpu_info *ci, int pin, int idtvec, 627 int type) 628 { 629 pci_chipset_tag_t pc = NULL; /* XXX */ 630 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 631 bus_space_handle_t memh; 632 pcitag_t tag = PCI_MSI_TAG(pin); 633 int entry = PCI_MSI_VEC(pin); 634 pcireg_t reg, addr; 635 uint32_t ctrl; 636 int off; 637 638 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 639 panic("%s: no msix capability", __func__); 640 641 KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg)); 642 643 if (pci_msix_table_map(pc, tag, memt, &memh)) 644 panic("%s: cannot map registers", __func__); 645 646 addr = 0xfee00000UL | (ci->ci_apicid << 12); 647 648 bus_space_write_4(memt, memh, PCI_MSIX_MA(entry), addr); 649 bus_space_write_4(memt, memh, PCI_MSIX_MAU32(entry), 0); 650 bus_space_write_4(memt, memh, PCI_MSIX_MD(entry), idtvec); 651 bus_space_barrier(memt, memh, PCI_MSIX_MA(entry), 16, 652 BUS_SPACE_BARRIER_WRITE); 653 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 654 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 655 ctrl & ~PCI_MSIX_VC_MASK); 656 657 pci_msix_table_unmap(pc, tag, memt, memh); 658 659 pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE); 660 } 661 662 void 663 msix_delroute(struct pic *pic, struct cpu_info *ci, int pin, int idtvec, 664 int type) 665 { 666 pci_chipset_tag_t pc = NULL; /* XXX */ 667 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 668 bus_space_handle_t memh; 669 pcitag_t tag = PCI_MSI_TAG(pin); 670 int entry = PCI_MSI_VEC(pin); 671 pcireg_t reg; 672 uint32_t ctrl; 673 674 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 675 return; 676 677 KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg)); 678 679 if (pci_msix_table_map(pc, tag, memt, &memh)) 680 return; 681 682 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 683 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 684 ctrl | PCI_MSIX_VC_MASK); 685 686 pci_msix_table_unmap(pc, tag, memt, memh); 687 } 688 689 int 690 pci_intr_map_msix(struct pci_attach_args *pa, int vec, pci_intr_handle_t *ihp) 691 { 692 pci_chipset_tag_t pc = pa->pa_pc; 693 pcitag_t tag = pa->pa_tag; 694 pcireg_t reg; 695 696 KASSERT(PCI_MSI_VEC(vec) == vec); 697 698 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 699 pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 700 return 1; 701 702 if (vec > PCI_MSIX_MC_TBLSZ(reg)) 703 return 1; 704 705 ihp->tag = PCI_MSI_PIN(tag, vec); 706 ihp->line = APIC_INT_VIA_MSGX; 707 ihp->pin = 0; 708 return 0; 709 } 710 711 int 712 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 713 { 714 int pin = pa->pa_rawintrpin; 715 int line = pa->pa_intrline; 716 #if NIOAPIC > 0 717 struct mp_intr_map *mip; 718 int bus, dev, func; 719 #endif 720 721 if (pin == 0) { 722 /* No IRQ used. */ 723 goto bad; 724 } 725 726 if (pin > PCI_INTERRUPT_PIN_MAX) { 727 printf("pci_intr_map: bad interrupt pin %d\n", pin); 728 goto bad; 729 } 730 731 ihp->tag = pa->pa_tag; 732 ihp->line = line; 733 ihp->pin = pin; 734 735 #if NIOAPIC > 0 736 pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 737 738 if (mp_busses != NULL) { 739 int mpspec_pin = (dev << 2) | (pin - 1); 740 741 if (bus < mp_nbusses) { 742 for (mip = mp_busses[bus].mb_intrs; 743 mip != NULL; mip = mip->next) { 744 if (&mp_busses[bus] == mp_isa_bus || 745 &mp_busses[bus] == mp_eisa_bus) 746 continue; 747 if (mip->bus_pin == mpspec_pin) { 748 ihp->line = mip->ioapic_ih | line; 749 return 0; 750 } 751 } 752 } 753 754 if (pa->pa_bridgetag) { 755 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 756 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 757 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 758 ihp->line |= line; 759 return 0; 760 } 761 } 762 /* 763 * No explicit PCI mapping found. This is not fatal, 764 * we'll try the ISA (or possibly EISA) mappings next. 765 */ 766 } 767 #endif 768 769 /* 770 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 771 * `unknown' or `no connection' on a PC. We assume that a device with 772 * `no connection' either doesn't have an interrupt (in which case the 773 * pin number should be 0, and would have been noticed above), or 774 * wasn't configured by the BIOS (in which case we punt, since there's 775 * no real way we can know how the interrupt lines are mapped in the 776 * hardware). 777 * 778 * XXX 779 * Since IRQ 0 is only used by the clock, and we can't actually be sure 780 * that the BIOS did its job, we also recognize that as meaning that 781 * the BIOS has not configured the device. 782 */ 783 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 784 goto bad; 785 786 if (line >= NUM_LEGACY_IRQS) { 787 printf("pci_intr_map: bad interrupt line %d\n", line); 788 goto bad; 789 } 790 if (line == 2) { 791 printf("pci_intr_map: changed line 2 to line 9\n"); 792 line = 9; 793 } 794 795 #if NIOAPIC > 0 796 if (mp_busses != NULL) { 797 if (mip == NULL && mp_isa_bus) { 798 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 799 mip = mip->next) { 800 if (mip->bus_pin == line) { 801 ihp->line = mip->ioapic_ih | line; 802 return 0; 803 } 804 } 805 } 806 #if NEISA > 0 807 if (mip == NULL && mp_eisa_bus) { 808 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 809 mip = mip->next) { 810 if (mip->bus_pin == line) { 811 ihp->line = mip->ioapic_ih | line; 812 return 0; 813 } 814 } 815 } 816 #endif 817 if (mip == NULL) { 818 printf("pci_intr_map: " 819 "bus %d dev %d func %d pin %d; line %d\n", 820 bus, dev, func, pin, line); 821 printf("pci_intr_map: no MP mapping found\n"); 822 } 823 } 824 #endif 825 826 return 0; 827 828 bad: 829 ihp->line = -1; 830 return 1; 831 } 832 833 const char * 834 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 835 { 836 static char irqstr[64]; 837 838 if (ih.line == 0) 839 panic("pci_intr_string: bogus handle 0x%x", ih.line); 840 841 if (ih.line & APIC_INT_VIA_MSG) 842 return ("msi"); 843 if (ih.line & APIC_INT_VIA_MSGX) 844 return ("msix"); 845 846 #if NIOAPIC > 0 847 if (ih.line & APIC_INT_VIA_APIC) 848 snprintf(irqstr, sizeof(irqstr), "apic %d int %d", 849 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 850 else 851 snprintf(irqstr, sizeof(irqstr), "irq %d", 852 pci_intr_line(pc, ih)); 853 #else 854 snprintf(irqstr, sizeof(irqstr), "irq %d", pci_intr_line(pc, ih)); 855 #endif 856 return (irqstr); 857 } 858 859 #include "acpiprt.h" 860 #if NACPIPRT > 0 861 void acpiprt_route_interrupt(int bus, int dev, int pin); 862 #endif 863 864 void * 865 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 866 int (*func)(void *), void *arg, const char *what) 867 { 868 return pci_intr_establish_cpu(pc, ih, level, NULL, func, arg, what); 869 } 870 871 void * 872 pci_intr_establish_cpu(pci_chipset_tag_t pc, pci_intr_handle_t ih, 873 int level, struct cpu_info *ci, 874 int (*func)(void *), void *arg, const char *what) 875 { 876 int pin, irq; 877 int bus, dev; 878 pcitag_t tag = ih.tag; 879 struct pic *pic; 880 881 if (ih.line & APIC_INT_VIA_MSG) { 882 return intr_establish(-1, &msi_pic, tag, IST_PULSE, level, 883 ci, func, arg, what); 884 } 885 if (ih.line & APIC_INT_VIA_MSGX) { 886 return intr_establish(-1, &msix_pic, tag, IST_PULSE, level, 887 ci, func, arg, what); 888 } 889 890 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 891 #if NACPIPRT > 0 892 acpiprt_route_interrupt(bus, dev, ih.pin); 893 #endif 894 895 pic = &i8259_pic; 896 pin = irq = ih.line; 897 898 #if NIOAPIC > 0 899 if (ih.line & APIC_INT_VIA_APIC) { 900 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih.line)); 901 if (pic == NULL) { 902 printf("pci_intr_establish: bad ioapic %d\n", 903 APIC_IRQ_APIC(ih.line)); 904 return NULL; 905 } 906 pin = APIC_IRQ_PIN(ih.line); 907 irq = APIC_IRQ_LEGACY_IRQ(ih.line); 908 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 909 irq = -1; 910 } 911 #endif 912 913 return intr_establish(irq, pic, pin, IST_LEVEL, level, ci, 914 func, arg, what); 915 } 916 917 void 918 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 919 { 920 intr_disestablish(cookie); 921 } 922 923 struct extent *pciio_ex; 924 struct extent *pcimem_ex; 925 struct extent *pcibus_ex; 926 927 void 928 pci_init_extents(void) 929 { 930 bios_memmap_t *bmp; 931 u_int64_t size; 932 933 if (pciio_ex == NULL) { 934 /* 935 * We only have 64K of addressable I/O space. 936 * However, since BARs may contain garbage, we cover 937 * the full 32-bit address space defined by PCI of 938 * which we only make the first 64K available. 939 */ 940 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 941 NULL, 0, EX_NOWAIT | EX_FILLED); 942 if (pciio_ex == NULL) 943 return; 944 extent_free(pciio_ex, 0, 0x10000, EX_NOWAIT); 945 } 946 947 if (pcimem_ex == NULL) { 948 /* 949 * Cover the 36-bit address space addressable by PAE 950 * here. As long as vendors continue to support 951 * 32-bit operating systems, we should never see BARs 952 * outside that region. 953 * 954 * Dell 13G servers have important devices outside the 955 * 36-bit address space. Until we can extract the address 956 * ranges from ACPI, expand the allowed range to suit. 957 */ 958 pcimem_ex = extent_create("pcimem", 0, 0xffffffffffffffffUL, 959 M_DEVBUF, NULL, 0, EX_NOWAIT); 960 if (pcimem_ex == NULL) 961 return; 962 extent_alloc_region(pcimem_ex, 0x40000000000UL, 963 0xfffffc0000000000UL, EX_NOWAIT); 964 965 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 966 /* 967 * Ignore address space beyond 4G. 968 */ 969 if (bmp->addr >= 0x100000000ULL) 970 continue; 971 size = bmp->size; 972 if (bmp->addr + size >= 0x100000000ULL) 973 size = 0x100000000ULL - bmp->addr; 974 975 /* Ignore zero-sized regions. */ 976 if (size == 0) 977 continue; 978 979 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 980 EX_NOWAIT)) 981 printf("memory map conflict 0x%llx/0x%llx\n", 982 bmp->addr, bmp->size); 983 } 984 985 /* Take out the video buffer area and BIOS areas. */ 986 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 987 EX_CONFLICTOK | EX_NOWAIT); 988 } 989 990 if (pcibus_ex == NULL) { 991 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 992 NULL, 0, EX_NOWAIT); 993 } 994 } 995 996 int 997 pci_probe_device_hook(pci_chipset_tag_t pc, struct pci_attach_args *pa) 998 { 999 #if NACPIDMAR > 0 1000 acpidmar_pci_hook(pc, pa); 1001 #endif 1002 return 0; 1003 } 1004 1005 #if NACPI > 0 1006 void acpi_pci_match(struct device *, struct pci_attach_args *); 1007 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 1008 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 1009 #endif 1010 1011 void 1012 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 1013 { 1014 #if NACPI > 0 1015 acpi_pci_match(dev, pa); 1016 #endif 1017 } 1018 1019 pcireg_t 1020 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 1021 { 1022 #if NACPI > 0 1023 return acpi_pci_min_powerstate(pc, tag); 1024 #else 1025 return pci_get_powerstate(pc, tag); 1026 #endif 1027 } 1028 1029 void 1030 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 1031 { 1032 #if NACPI > 0 1033 acpi_pci_set_powerstate(pc, tag, state, pre); 1034 #endif 1035 } 1036