1 /* $OpenBSD: i82093reg.h,v 1.8 2022/12/01 00:26:15 guenther Exp $ */ 2 /* $NetBSD: i82093reg.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Typically, the first apic lives here. 37 */ 38 #define IOAPIC_BASE_DEFAULT 0xfec00000 39 40 /* 41 * Memory-space registers. 42 */ 43 44 /* 45 * The externally visible registers are all 32 bits wide; 46 * store the register number of interest in IOAPIC_REG, and store/fetch 47 * the real value in IOAPIC_DATA. 48 */ 49 #define IOAPIC_REG 0x0000 50 #define IOAPIC_DATA 0x0010 51 52 /* 53 * Internal I/O APIC registers. 54 */ 55 56 #define IOAPIC_ID 0x00 57 58 #define IOAPIC_ID_SHIFT 24 59 #define IOAPIC_ID_MASK 0x0f000000 60 61 /* Version, and maximum interrupt pin number. */ 62 63 #define IOAPIC_VER 0x01 64 65 #define IOAPIC_VER_SHIFT 0 66 #define IOAPIC_VER_MASK 0x000000ff 67 68 #define IOAPIC_MAX_SHIFT 16 69 #define IOAPIC_MAX_MASK 0x00ff0000 70 71 /* 72 * Arbitration ID. Same format as IOAPIC_ID register. 73 */ 74 #define IOAPIC_ARB 0x02 75 76 /* 77 * Redirection table registers. 78 */ 79 80 #define IOAPIC_REDHI(pin) (0x11 + ((pin)<<1)) 81 #define IOAPIC_REDLO(pin) (0x10 + ((pin)<<1)) 82 83 #define IOAPIC_REDHI_DEST_SHIFT 24 /* destination. */ 84 #define IOAPIC_REDHI_DEST_MASK 0xff000000 85 86 #define IOAPIC_REDLO_MASK 0x00010000 /* 0=enabled; 1=masked */ 87 88 #define IOAPIC_REDLO_LEVEL 0x00008000 /* 0=edge, 1=level */ 89 #define IOAPIC_REDLO_RIRR 0x00004000 /* remote IRR; read only */ 90 #define IOAPIC_REDLO_ACTLO 0x00002000 /* 0=act. hi; 1=act. lo */ 91 #define IOAPIC_REDLO_DELSTS 0x00001000 /* 0=idle; 1=send pending */ 92 #define IOAPIC_REDLO_DSTMOD 0x00000800 /* 0=physical; 1=logical */ 93 94 #define IOAPIC_REDLO_DEL_MASK 0x00000700 /* del. mode mask */ 95 #define IOAPIC_REDLO_DEL_SHIFT 8 96 97 #define IOAPIC_REDLO_DEL_FIXED 0 98 #define IOAPIC_REDLO_DEL_LOPRI 1 99 #define IOAPIC_REDLO_DEL_SMI 2 100 #define IOAPIC_REDLO_DEL_NMI 4 101 #define IOAPIC_REDLO_DEL_INIT 5 102 #define IOAPIC_REDLO_DEL_EXTINT 7 103 104 #define IOAPIC_REDLO_VECTOR_MASK 0x000000ff /* delivery vector */ 105 106 #define IMCR_ADDR 0x22 107 #define IMCR_DATA 0x23 108 109 #define IMCR_REGISTER 0x70 110 #define IMCR_PIC 0x00 111 #define IMCR_APIC 0x01 112 113 #ifdef _KERNEL 114 115 #include <machine/codepatch.h> 116 117 #define ioapic_asm_ack(num) \ 118 CODEPATCH_START ;\ 119 movl $0,(local_apic+LAPIC_EOI)(%rip) ;\ 120 CODEPATCH_END(CPTAG_EOI) 121 122 123 #ifdef MULTIPROCESSOR 124 125 #ifdef notyet 126 #define ioapic_asm_lock(num) \ 127 movl $1,%esi ;\ 128 77: \ 129 xchgl %esi,PIC_LOCK(%rdi) ;\ 130 testl %esi,%esi ;\ 131 jne 77b 132 133 #define ioapic_asm_unlock(num) \ 134 movl $0,PIC_LOCK(%rdi) 135 #else 136 #define ioapic_asm_lock(num) 137 #define ioapic_asm_unlock(num) 138 #endif 139 140 #else 141 142 #define ioapic_asm_lock(num) 143 #define ioapic_asm_unlock(num) 144 145 #endif /* MULTIPROCESSOR */ 146 147 148 #define ioapic_mask(num) \ 149 movq IS_PIC(%r14),%rdi ;\ 150 ioapic_asm_lock(num) ;\ 151 movl IS_PIN(%r14),%esi ;\ 152 leaq 0x10(%rsi,%rsi,1),%rsi ;\ 153 movq IOAPIC_SC_REG(%rdi),%r15 ;\ 154 movl %esi, (%r15) ;\ 155 movq IOAPIC_SC_DATA(%rdi),%r15 ;\ 156 movl (%r15),%esi ;\ 157 orl $IOAPIC_REDLO_MASK,%esi ;\ 158 andl $~IOAPIC_REDLO_RIRR,%esi ;\ 159 movl %esi,(%r15) ;\ 160 ioapic_asm_unlock(num) 161 162 #define ioapic_unmask(num) \ 163 cmpq $IREENT_MAGIC,IF_ERR(%rsp) ;\ 164 jne 79f ;\ 165 movq IS_PIC(%r14),%rdi ;\ 166 ioapic_asm_lock(num) ;\ 167 movl IS_PIN(%r14),%esi ;\ 168 leaq 0x10(%rsi,%rsi,1),%rsi ;\ 169 movq IOAPIC_SC_REG(%rdi),%r15 ;\ 170 movq IOAPIC_SC_DATA(%rdi),%r13 ;\ 171 movl %esi, (%r15) ;\ 172 movl (%r13),%r12d ;\ 173 andl $~IOAPIC_REDLO_MASK,%r12d ;\ 174 andl $~IOAPIC_REDLO_RIRR,%r12d ;\ 175 movl %esi,(%r15) ;\ 176 movl %r12d,(%r13) ;\ 177 ioapic_asm_unlock(num) ;\ 178 79: 179 180 #endif 181